74LVX4245MTCX [ONSEMI]
带 3 状态输出的 8 位双电源转换收发器;
| 型号： | 74LVX4245MTCX |
| 厂家： | 
ONSEMI |
| 描述： | 带 3 状态输出的 8 位双电源转换收发器 PC 光电二极管 逻辑集成电路 |
| 文件： | 总10页 (文件大小：205K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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January 1993
Revised September 2003
74LVX4245
8-Bit Dual Supply Translating Transceiver
with 3-STATE Outputs
General Description
Features
■ Bidirectional interface between 5V and 3V buses
The LVX4245 is a dual-supply, 8-bit translating transceiver
that is designed to interface between a 5V bus and a 3V
bus in a mixed 3V/5V supply environment. The Transmit/
Receive (T/R) input determines the direction of data flow.
Transmit (active-HIGH) enables data from A Ports to B
Ports; Receive (active-LOW) enables data from B Ports to
A Ports. The Output Enable input, when HIGH, disables
both A and B Ports by placing them in a high impedance
condition. The A Port interfaces with the 5V bus; the B Port
interfaces with the 3V bus.
■ Control inputs compatible with TTL level
■ 5V data flow at A Port and 3V data flow at B Port
■ Outputs source/sink 24 mA at 5V bus; 12 mA at 3V bus
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
■ Implements patented EMI reduction circuitry
■ Functionally compatible with the 74 series 245
The LVX4245 is suitable for mixed voltage applications
such as laptop computers using 3.3V CPU’s and 5V LCD
displays.
Ordering Code:
Order Number Package Number
Package Description
74LVX4245WM
74LVX4245QSC
74LVX4245MTC
M24B
MQA24
MTC24
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
Description
Output Enable Input
OE
T/R
Transmit/Receive Input
A0–A7
B0–B7
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
Connection Diagram
Truth Table
Inputs
Outputs
OE
L
T/R
L
Bus B Data to Bus A
Bus A Data to Bus B
HIGH-Z State
L
H
H
X
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
© 2003 Fairchild Semiconductor Corporation
DS011540
www.fairchildsemi.com
Logic Diagram
www.fairchildsemi.com
2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions (Note 2)
Supply Voltage (VCCA, VCCB
)
−0.5V to +7.0V
DC Input Voltage (VI) @ OE, T/R
−0.5V to VCCA + 0.5V
Supply Voltage
DC Input/Output Voltage (VI/O
)
VCCA
4.5V to 5.5V
2.7V to 3.6V
0V to VCCA
@ An
@Bn
−0.5V to VCCA + 0.5V
−0.5V to VCCB + 0.5V
VCCB
Input Voltage (VI) @ OE, T/R
DC Input Diode Current (IIN
)
Input/Output Voltage (VI/O)
@ OE, T/R
±20 mA
±50 mA
@ An
@ Bn
0V to VCCA
0V to VCCB
−40°C to +85°C
8 ns/V
DC Output Diode Current (IOK
)
DC Output Source or Sink Current
(IO)
Free Air Operating Temperature (TA)
Minimum Input Edge Rate (∆t/∆V)
VIN from 30% to 70% of VCC
VCC @ 3.0V, 4.5V, 5.5V
±50 mA
DC VCC or Ground Current
per Output Pin (ICC or IGND
and Max Current @ ICCA
@ ICCB
)
±50 mA
±200 mA
±100 mA
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Storage Temperature Range
(TSTG
)
−65°C to +150°C
±300 mA
Note 2: Unused inputs must he held HIGH or LOW. They may not float.
DC Latch-Up Source or
Sink Current
DC Electrical Characteristics
VCCA
VCCB
(V)
T
A +25°C
TA = −40°C to +85°C
Symbol
Parameter
Units
Conditions
(V)
Typ
Guaranteed Limits
VIHA
Minimum
An, T/R,
5.5
4.5
5.0
5.0
3.3
3.3
3.6
2.7
2.0
2.0
2.0
2.0
2.0
VOUT ≤ 0.1V or
≥ VCC − 0.1V
HIGH Level
Input Voltage
OE
Bn
2.0
2.0
2.0
V
VIHB
VILA
Maximum
An, T/R,
OE
5.5
4.5
5.0
5.0
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
3.3
3.3
2.7
3.6
3.0
3.0
3.0
3.0
2.7
3.0
3.0
3.0
3.0
2.7
0.8
0.8
0.8
0.8
4.4
0.8
0.8
0.8
0.8
4.4
VOUT ≤ 0.1V or
≥ VCC −0.1V
LOW Level
Input Voltage
V
V
VILB
Bn
VOHA
Minimum HIGH Level
Output Voltage
4.5
4.25
2.99
2.8
I
I
I
I
I
I
I
I
I
I
OUT = −100 µA
OH = −24 mA
OUT = −100 µA
OH = −12 mA
OL = −8 mA
3.86
2.9
3.76
2.9
2.4
2.4
0.1
0.44
0.1
0.4
0.4
VOHB
2.4
V
V
2.5
2.4
VOLA
Maximum LOW Level
Output Voltage
0.002
0.18
0.002
0.1
0.1
OUT =100 µA
OL = 24 mA
0.36
0.1
VOLB
OUT = 100 µA
OL = 12 mA
0.31
0.31
V
0.1
OL = 8 mA
IIN
Maximum Input
Leakage Current
@ OE, T/R
VI = VCCA, GND
5.5
5.5
3.6
3.6
±0.1
±0.5
±1.0
±5.0
µA
IOZA
IOZB
∆ICC
Maximum 3-STATE
Output Leakage
@ An
VI = VIL, VIH
µA OE = VCCA
VO = VCCA, GND
Maximum 3-STATE
Output Leakage
@ Bn
VI = VIL, VIH
µA OE = VCCA
5.5
5.5
5.5
3.6
3.6
3.6
±0.5
1.35
0.35
±5.0
1.5
VO = VCCB, GND
Maximum ICCT/Input
@ An, T/R, OE
Input @ Bn
1.0
mA VI = VCCA − 2.1V
0.5
mA VI = VCCB − 0.6V
3
www.fairchildsemi.com
DC Electrical Characteristics (Continued)
VCCA
(V)
VCCB
(V)
T
A +25°C
TA = −40°C to +85°C
Symbol
Parameter
Quiescent VCCA
Units
Conditions
Typ
Guaranteed Limits
ICCA
A
n = VCCA or GND
n = VCCB or GND,
Supply Current
5.5
5.5
3.6
3.6
8
5
80
µA
B
OE = GND T/R = GND
ICCB
Quiescent VCCB
Supply Current
A
n = VCCA or GND
n = VCCB or GND,
50
µA
B
OE = GND T/R = VCCA
VOLPA
VOLPB
VOLVA
VOLVB
VIHDA
VIHDB
VILDA
VILDB
Quiet Output Maximum
Dynamic VOL
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
1.5
0.8
(Note 4)(Note 5)
V
V
V
V
Quiet Output Minimum
Dynamic VOL
−1.2
−0.8
2.0
(Note 4)(Note 5)
(Note 4)(Note 6)
(Note 4)(Note 6)
Minimum HIGH Level
Dynamic Input Voltage
Maximum LOW Level
Dynamic Input Voltage
2.0
0.8
0.8
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: Worst case package.
Note 5: Max number of outputs defined as (n). Data inputs are driven 0V to VCC level; one output at GND.
Note 6: Max number of Data Inputs (n) switching. (n−1) inputs switching 0V to VCC level. Input-under-test switching:
VCC level to threshold (VIHD), OV to threshold (VILD), f = 1 MHz.
AC Electrical Characteristics
T
A = +25°C
L = 50 pF
CCA = 5V (Note 7)
CCB = 3.3V (Note 8)
T
A = −40°C to +85°C
T
A = −40°C to +85°C
L = 50 pF
CCA = 5V (Note 7)
CCB = 2.7V
C
C
L = 50 pF
C
Symbol
Parameters
V
V
CCA = 5V (Note 7)
V
Units
V
VCCB = 3.3V (Note 8)
V
Min
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Typ
5.1
5.3
5.4
5.5
6.5
6.7
5.2
5.8
6.0
3.3
3.9
2.9
Max
Min
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max
9.0
Min
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max
10.0
10.0
10.0
10.0
11.5
11.5
10.0
10.0
10.0
7.5
tPHL
Propagation Delay
8.5
8.5
8.5
8.5
10.0
10.0
9.0
9.0
9.5
6.5
7.0
6.5
ns
ns
ns
ns
ns
ns
tPLH
tPHL
tPLH
tPZL
A to B
9.0
Propagation Delay
B to A
9.0
9.0
Output Enable Time
OE to B
10.5
10.5
9.5
tPZH
tPZL
Output Enable Time
OE to A
tPZH
tPHZ
tPLZ
tPHZ
tPLZ
tOSHL
tOSLH
9.5
Output Disable Time
OE to B
10.0
7.0
Output Disable Time
OE to A
7.5
7.5
7.0
7.5
Output to Output
Skew (Note 9)
Data to Output
1.0
1.5
1.5
1.5
ns
Note 7: Voltage Range 5.0V is 5.0V ± 0.5V.
Note 8: Voltage Range 3.3V is 3.3V ± 0.3V.
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
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4
Capacitance
Symbol
Parameter
Input Capacitance
Typ
4.5
15
Units
pF
Conditions
VCC = Open
CIN
CI/O
Input/Output
Capacitance
pF
V
V
V
V
CCA = 5.0V
CCB = 3.3V
CCA = 5.0V
CCB = 3.3V
CPD
Power Dissipation
B→A
A→B
55
40
pF
pF
Capacitance (Note 10)
Note 10: CPD is measured at 10 MHz
8-Bit Dual Supply Translating Transceiver
The LVX4245 is a dual supply device capable of bidirec-
tional signal translation. This level shifting ability provides
an efficient interface between low voltage CPU local bus
with memory and a standard bus defined by 5V I/O levels.
The device control inputs can be controlled by either the
low voltage CPU and core logic or a bus arbitrator with 5V
I/O levels.
Manufactured on
a sub-micron CMOS process, the
LVX4245 is ideal for mixed voltage applications such as
notebook computers using 3.3V CPU’s and 5V peripheral
devices.
Power Up Considerations
To insure the system does not experience unnecessary ICC
pins are configured as inputs. With VCCA receiving
current draw, bus contention, or oscillations during power
up, the following guidelines should be adhered to (refer to
Table 1):
power first, the A I/O Port should be configured as inputs
to help guard against bus contention and oscillations.
•
A side data inputs should be driven to a valid logic level.
This will prevent excessive current draw.
•
•
•
Power up the control side of the device first. This is the
VCCA
.
The above steps will ensure that no bus contention or oscil-
lations, and therefore no excessive current draw occurs
during the power up cycling of these devices. These steps
will help prevent possible damage to the translator devices
and potential damage to other system components.
OE should ramp with or ahead of VCCA. This will help
guard against bus contention.
The Transmit/Receive control pin (T/R) should ramp with
or ahead of VCCA, this will ensure that the A Port data
TABLE 1. Low Voltage Translator Power Up Sequencing Table
A Side
I/O
B Side
I/O
Floatable Pin
Allowed
VCCA
VCCB
Device Type
T/R
OE
5V
3V
ramp
ramp
logic
74LVX4245
outputs
No
(power up 1st)
(power up 2nd)
with VCCA
with VCCA
0V or VCCA
Please reference Application Note AN-5001 for more detailed information on using Fairchild’s LVX Low Voltage Dual
Supply CMOS Translating Transceivers.
5
www.fairchildsemi.com
Applications: Mixed Mode Dual Supply Interface Solution
LVX4245 is designed to solve 3V/5V interfacing issues
when CMOS devices cannot tolerate I/O levels above their
applied VCC. If an I/O pin of 3V ICs is driven by 5V ICs, the
either a 3V system or a 5V system without any further work
to re-layout the board.
P-Channel transistor in 3V ICs will conduct causing current
flow from I/O bus to the 3V power supply. The resulting
high current flow can cause destruction of 3V ICs through
latchup effects. To prevent this problem, a current limiting
resistor is used typically under direct connection of 3V ICs
and 5V ICs, but it causes speed degradation.
In a better solution, the LVX4245 configures two different
output levels to handle the dual supply interface issues.
The “A” port is a dedicated 5V port to interface 5V ICs. The
“B” port is a dedicated port to interface 3V ICs. Figure 2
shows how LVX4245 fits into a system with 3V subsystem
and 5V subsystem.
This device is also configured as an 8-bit 245 transceiver,
giving the designer 3-STATE capabilities and the ability to
select either bidirectional or unidirectional modes. Since
the center 20 pins are also pin compatible to 74 series 245,
as shown in Figure 1, the designer could use this device in
FIGURE 1. LVX4245 Pin Arrangement is Compatible to
20-Pin 74 Series 245
FIGURE 2. LVX4245 Fits into a System with 3V Subsystem and 5V Subsystem
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6
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M24B
24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide
Package Number MQA24
7
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC24
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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www.fairchildsemi.com
8
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
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coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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相关型号：
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