74VCX163245MTDX [ONSEMI]

带 3 态输出的低压 16 位双电源转换收发器;
74VCX163245MTDX
型号: 74VCX163245MTDX
厂家: ONSEMI    ONSEMI
描述:

带 3 态输出的低压 16 位双电源转换收发器

文件: 总14页 (文件大小:454K)
中文:  中文翻译
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May 2007  
74VCX163245  
tm  
Low Voltage 16-Bit Dual Supply Translating  
Transceiver with 3-STATE Outputs  
Features  
General Description  
Bidirectional interface between busses ranging from  
The VCX163245 is a dual supply, 16-bit translating  
transceiver that is designed for 2 way asynchronous  
communication between busses at different supply volt-  
ages by providing true signal translation. The supply rails  
1.65V to 3.6V  
(1)  
Supports Live Insertion and Withdrawal  
Static Drive (I /I  
)
OH OL  
consist of V  
, which is a higher potential rail operating  
CCꢀ  
24mꢀ ꢁ 3.0V V  
CC  
CC  
CC  
at 2.3V to 3.6V and V  
, which is the lower potential  
CCB  
1ꢂmꢀ ꢁ 2.3V V  
6mꢀ ꢁ 1.65V V  
rail operating at 1.65V to 2.7V. (V  
must be less than  
CCB  
or equal to V  
for proper device operation). This dual  
CCꢀ  
supply design allows for translation from 1.ꢂV to 2.5V  
busses to busses at a higher potential, up to 3.3V.  
Uses proprietary Quiet Series™ noise/EMI reduction  
circuitry  
Functionally compatible with 74 series 16245  
Latchup performance exceeds 300mꢀ  
ESD performance:  
The Transmit/Receive (T/R) input determines the direc-  
tion of data flow. Transmit (active-HIGH) enables data  
from ꢀ Ports to B Ports; Receive (active-LOW) enables  
data from B Ports to ꢀ Ports. The Output Enable (OE)  
input, when HIGH, disables both ꢀ and B Ports by plac-  
ing them in a High-Z condition. The ꢀ Port interfaces  
with the higher voltage bus (2.7V to 3.3V); The B Port  
interfaces with the lower voltage bus (1.ꢂV to 2.5V). ꢀlso  
the VCX163245 is designed so that the control pins  
– Human Body Model >2000V  
– Machine model >200V  
ꢀlso packaged in plastic Fine-Pitch Ball Grid ꢀrray  
(FBGꢀ)  
Note:  
(T/R , OE ) are supplied by V .  
n
n
CCB  
1. To ensure the high impedance state during power up  
The 74VCX163245 is suitable for mixed voltage applica-  
tions such as notebook computers using a 1.ꢂV CPU and  
3.3V peripheral components. It is fabricated with an  
ꢀdvanced CMOS technology to achieve high speed oper-  
ation while maintaining low CMOS power dissipation.  
or power down, OE should be tied to V  
through a  
n
CCB  
pull up resistor. The minimum value of the resistor is  
determined by the current sourcing capability of the  
driver.  
Ordering Information  
Order Number  
Package Number  
Package Description  
(2)(3)  
74VCX163245G  
BGꢀ54ꢀ  
54-Ball Fine-Pitch Ball Grid ꢀrray (FBGꢀ), JEDEC MO-205,  
5.5mm Wide  
(3)  
74VCX163245MTD  
MTD4ꢂ  
4ꢂ-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC  
MO-153, 6.1mm Wide  
Notes:  
2. Ordering code “G” indicates Trays.  
3. Device also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Quiet Series™ is a trademark of Fairchild Semiconductor Corporation.  
©2000 Fairchild Semiconductor Corporation  
74VCX163245 Rev. 1.7  
www.fairchildsemi.com  
Connection Diagram  
Pin Assignment for TSSOP  
Pin Assignment for FBGA  
(Top Thru View)  
FBGA Pin Assignments  
1
2
3
4
5
6
A
B
C
D
E
F
B
NC  
T/R  
OE  
NC  
0
2
4
6
1
1
0
2
4
6
B
B
B
B
B
B
B
B
B
NC  
NC  
1
3
5
7
9
1
3
5
7
9
V
V
CCꢀ  
CCB  
GND GND  
GND GND  
GND GND  
B
B
B
B
10  
12  
14  
15  
10  
12  
14  
15  
G
H
J
B
B
V
V
11  
13  
CCB  
CCꢀ  
11  
13  
NC  
T/R  
NC  
OE  
NC  
NC  
2
2
Pin Descriptions  
Pin  
Description  
Names  
OE  
Output Enable Input (ꢀctive LOW)  
Transmit/Receive Input  
n
T/R  
n
ꢀ –ꢀ  
Side ꢀ Inputs or 3-STTE Outputs  
Side B Inputs or 3-STTE Outputs  
No Connect  
0
15  
B –B  
0
15  
NC  
Logic Diagram  
©2000 Fairchild Semiconductor Corporation  
74VCX163245 Rev. 1.7  
www.fairchildsemi.com  
2
Truth Tables  
Inputs  
OE T/R  
Inputs  
Outputs  
OE  
L
T/R  
L
Outputs  
2
2
1
1
L
L
L
H
X
Bus B –B Data to Bus ꢀ –ꢀ  
Bus B –B Data to Bus ꢀ –ꢀ  
15  
15  
0
7
0
7
Bus ꢀ –ꢀ Data to Bus B –B  
L
H
Bus ꢀ –ꢀ Data to Bus B –B  
0 7 0  
15  
15  
7
H
HIGH-Z State on ꢀ –ꢀ , B –B  
ꢂ 15 ꢂ 15  
H
X
HIGH Z State on ꢀ –ꢀ , B –B  
0 7 0 7  
H = HIGH Voltage Level  
L = LOW Voltage Level  
X = Immaterial (HIGH or LOW, inputs may not float)  
Z = High Impedance  
VCX163245 Translator Power Up Sequence Recommendations  
To guard against power up problems, some simple  
guidelines need to be adhered to. The VCX163245 is  
placed at logic LOW (0V) level, this will ensure that the  
B-side bus pins are configured as inputs to help guard  
against bus contention and oscillations. B-side Data  
Inputs should be driven to a valid logic level (0V or  
designed so that the control pins (T/R , OE ) are sup-  
n
n
plied by V  
. Therefore the first recommendation is to  
CCB  
begin by powering up the control side of the device,  
. The OE control pins should be ramped with or  
V
), this will prevent excessive current draw and oscil-  
CCB  
V
lations. V  
can then be powered up after V  
, how-  
CCB  
n
CCꢀ  
CCB  
ahead of V  
, this will guard against bus contentions  
ever V  
must be greater than or equal to V  
to  
CCB  
CCꢀ  
CCB  
and oscillations as all ꢀ Port and B Port outputs will be  
disabled. To ensure the high impedance state during  
ensure proper device operation. Upon completion of  
these steps the device can then be configured for the  
users desired operation. Following these steps will help  
to prevent possible damage to the translator device as  
well as other system components.  
power up or power down, OE should be tied to V  
n
CCB  
through a pull up resistor. The minimum value of the  
resistor is determined by the current sourcing capability  
of the driver. Second, the T/R control pins should be  
n
Logic Diagrams  
Please note that these diagrams are provided only for the understanding of logic operations and should not be used  
to estimate propagation delays.  
©2000 Fairchild Semiconductor Corporation  
74VCX163245 Rev. 1.7  
www.fairchildsemi.com  
3
Absolute Maximum Ratings  
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be  
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.  
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.  
The absolute maximum ratings are stress ratings only.  
Symbol  
Parameter  
Rating  
V
V
Supply Voltage  
–0.5V to +4.6V  
–0.5V to V  
CCꢀ  
CCB  
CCꢀ  
V
DC Input Voltage  
DC Output Voltage  
Outputs 3-STTE  
–0.5V to +4.6V  
I
V
I/O  
–0.5V to +4.6V  
(4)  
ꢀ Output ꢀctive  
–0.5V to V  
–0.5V to V  
+ 0.5V  
+ 0.5V  
–50mꢀ  
n
CCꢀ  
(4)  
B Output ꢀctive  
n
CCB  
I
DC Input Diode Current, V < 0V  
IK  
I
I
DC Output Diode Current  
OK  
V
< 0V  
–50mꢀ  
+50mꢀ  
50mꢀ  
O
V
> V  
CC  
O
I
/I  
DC Output Source/Sink Current  
DC V or Ground Current  
OH OL  
100mꢀ  
CC  
I
or Ground Supply Pin  
CC  
T
Storage Temperature  
–65°C to +150°C  
STG  
(5)  
Recommended Operating Conditions  
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended  
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not  
recommend exceeding them or designing to absolute maximum ratings.  
Symbol  
Parameter  
Rating  
(6)  
V
V
Power Supply  
2.3V to 3.6V  
1.65V to 2.7V  
CCꢀ  
CCB  
V
Input Voltage () ꢁ OE, T/R  
Input/Output Voltage ()  
0V to V  
I
CCB  
V
I/O  
B
0V to V  
0V to V  
n
n
CCꢀ  
CCB  
I
/I  
Output Current in I /I  
OH OL  
OH OL  
V
V
V
V
= 3.0V to 3.6V  
24mꢀ  
1ꢂmꢀ  
CCꢀ  
CCꢀ  
CCB  
CCB  
= 2.3V to 2.7V  
= 2.3V to 2.7V  
= 1.65V to 1.95V  
1ꢂmꢀ  
6mꢀ  
T
Free ꢀir Operating Temperature  
Minimum Input Edge Rate, V = 0.ꢂV to 2.0V, V = 3.0V  
–40°C to +ꢂ5°C  
10ns/V  
t/V  
Notes:  
4. I ꢀbsolute Maximum Rating must be observed.  
IN  
CC  
O
5. Unused inputs or I/O pins must be held HIGH or LOW. They may not float.  
6. Operation requires: V V  
CCB  
CCꢀ  
©2000 Fairchild Semiconductor Corporation  
74VCX163245 Rev. 1.7  
www.fairchildsemi.com  
4
DC Electrical Characteristics (1.65V < V  
1.95V, 2.3V < V  
2.7V)  
CCB  
CCꢀ  
Symbol  
Parameter  
V
(V)  
V
(V)  
Conditions  
Min.  
Max.  
Units  
CCB  
CCA  
V
V
HIGH Level Input  
Voltage  
1.65–1.95  
1.65–1.95  
1.65–1.95  
1.65–1.95  
1.65–1.95  
1.65  
2.3–2.7  
2.3–2.7  
2.3–2.7  
2.3–2.7  
2.3–2.7  
2.3–2.7  
2.3–2.7  
2.3  
1.6  
V
V
V
V
V
IHꢀ  
IHB  
n
B , T/R, OE  
0.65 x V  
CCB  
n
V
V
LOW Level Input  
Voltage  
0.7  
ILꢀ  
ILB  
n
B , T/R, OE  
0.35 x V  
n
CCB  
V
HIGH Level Output Voltage  
HIGH Level Output Voltage  
Low Level Output Voltage  
Low Level Output Voltage  
I
I
I
I
I
I
I
I
= –100µꢀ  
= –1ꢂmꢀ  
= –100µꢀ  
= –6mꢀ  
= 100µꢀ  
= 1ꢂmꢀ  
= 100µꢀ  
= 6mꢀ  
V
V
– 0.2  
OHꢀ  
OH  
OH  
OH  
OH  
OL  
OL  
OL  
OL  
CCꢀ  
CCB  
1.7  
V
1.65–1.95  
1.65–1.95  
1.65–1.95  
1.65  
– 0.2  
V
V
V
OHB  
1.25  
V
V
2.3–2.7  
2.3–2.7  
2.3–2.7  
2.3  
0.2  
0.6  
0.2  
0.3  
5.0  
OLꢀ  
1.65–1.95  
1.65–1.95  
1.65–1.95  
OLB  
I
Input Leakage Current ꢁ OE,  
T/R  
2.3–2.7 0V V 3.6V  
µꢀ  
µꢀ  
I
I
I
3-STTE Output Leakage  
1.65–1.95  
2.3–2.7 0V V 3.6V,  
10  
OZ  
O
,
OE = V  
CCB  
V = V or V  
IL  
I
IH  
I
Power Off Leakage Current  
Quiescent Supply Current,  
0
0
0 (V , V ) 3.6V  
10  
20  
µꢀ  
µꢀ  
OFF  
I
O
I
/I  
1.65–1.95  
2.3–2.7 ꢀ = V  
or GND,  
CCꢀ  
CCꢀ CCB  
n
per supply, V  
/ V  
CCꢀ  
CCB  
B , OE, &T/R = V  
n
CCB  
or GND  
1.65–1.95  
2.3–2.7  
V
V
ꢀn 3.6V,  
20  
µꢀ  
CCꢀ  
CCB  
B , OE,  
n
T/R 3.6V  
I  
Increase in I per Input, B ,  
T/R, OE  
1.65–1.95  
1.65–1.95  
2.3–2.7 V = V  
– 0.6V  
750  
750  
µꢀ  
µꢀ  
CC  
CC  
n
I
CCB  
Increase in I per Input, ꢀ  
2.3–2.7 V = V  
– 0.6V  
CC  
n
I
CCꢀ  
©2000 Fairchild Semiconductor Corporation  
74VCX163245 Rev. 1.7  
www.fairchildsemi.com  
5
DC Electrical Characteristics (1.65V < V  
1.95V, 3.0V < V  
3.6V)  
CCB  
CCꢀ  
Symbol  
Parameter  
V
(V)  
V
(V)  
CCA  
Conditions  
Min.  
Max.  
Units  
CCB  
V
V
HIGH Level Input  
Voltage  
1.65–1.95  
1.65–1.95  
1.65–1.95  
1.65–1.95  
1.65–1.95  
1.65  
3.0–3.6  
3.0–3.6  
3.0–3.6  
3.0–3.6  
3.0–3.6  
3.0–3.6  
3.0–3.6  
3.0  
2.0  
V
V
V
V
V
IHꢀ  
IHB  
n
B , T/R, OE  
0.65 x V  
CCB  
n
V
V
LOW Level Input  
Voltage  
0.ꢂ  
ILꢀ  
ILB  
n
B , T/R, OE  
0.35 x V  
n
CCB  
V
HIGH Level Output Voltage  
HIGH Level Output Voltage  
LOW Level Output Voltage  
LOW Level Output Voltage  
I
I
I
I
I
I
I
I
= –100µꢀ  
= –24mꢀ  
= –100µꢀ  
= –6mꢀ  
= 100µꢀ  
= 24mꢀ  
= 100µꢀ  
= 6mꢀ  
V
V
– 0.2  
OHꢀ  
OH  
OH  
OH  
OH  
OL  
OL  
OL  
OL  
CCꢀ  
CCꢀ  
2.2  
V
1.65–1.95  
1.65–1.95  
1.65–1.95  
1.65  
– 0.2  
V
V
V
OHB  
1.25  
V
V
3.0–3.6  
3.0–3.6  
3.0–3.6  
3.0  
0.2  
0.55  
0.2  
OLꢀ  
1.65–1.95  
1.65–1.95  
1.65–1.95  
OLB  
0.3  
I
Input Leakage Current ꢁ OE,  
T/R  
3.0–3.6 0V V 3.6V  
5.0  
µꢀ  
µꢀ  
I
I
I
3-STTE Output Leakage  
1.65–1.95  
3.0–3.6 0V V 3.6V,  
10  
OZ  
O
OE = V  
,
CCB  
V = V or V  
IL  
I
IH  
I
Power OFF Leakage Current  
Quiescent Supply Current,  
0
0
0 (V , V ) 3.6V  
10  
20  
µꢀ  
µꢀ  
OFF  
I
O
I
/I  
1.65–1.95  
3.0–3.6 ꢀ = V  
or GND,  
CCꢀ  
CCꢀ CCB  
n
per supply, V  
/V  
CCꢀ CCB  
B , OE, & T/R = V  
n
CCB  
or GND  
1.65–1.95  
3.0–3.6  
V
V
3.6V,  
20  
µꢀ  
CCꢀ  
CCB  
n
B , OE,  
n
T/R 3.6V  
I  
Increase in I per Input, B ,  
T/R, OE,  
1.65–1.95  
1.65–1.95  
3.0–3.6 V = V  
– 0.6V  
750  
750  
µꢀ  
µꢀ  
CC  
CC  
n
I
CCB  
Increase in I per Input, ꢀ  
3.0–3.6 V = V  
– 0.6V  
CC  
n
I
CCꢀ  
©2000 Fairchild Semiconductor Corporation  
74VCX163245 Rev. 1.7  
www.fairchildsemi.com  
6
DC Electrical Characteristics (2.3V < V  
2.7V, 3.0V V  
3.6V)  
CCB  
CCꢀ  
Symbol  
Parameter  
V
(V)  
V
(V)  
Conditions  
Min.  
2.0  
Max.  
Units  
CCB  
CCA  
V
V
HIGH Level Input  
Voltage  
2.3–2.7  
2.3–2.7  
2.3–2.7  
2.3–2.7  
2.3–2.7  
2.3  
3.0–3.6  
3.0–3.6  
3.0–3.6  
3.0–3.6  
3.0–3.6  
3.0–3.6  
3.0–3.6  
3.0  
V
V
V
V
V
IHꢀ  
IHB  
n
B , T/R, OE  
1.6  
n
V
V
LOW Level Input  
Voltage  
0.ꢂ  
0.7  
ILꢀ  
ILB  
n
B , T/R, OE  
n
V
HIGH Level Output Voltage  
HIGH Level Output Voltage  
LOW Level Output Voltage  
LOW Level Output Voltage  
I
I
I
I
I
I
I
I
= –100µꢀ  
= –24mꢀ  
= –100µꢀ  
= –1ꢂmꢀ  
= 100µꢀ  
= 24mꢀ  
V
V
– 0.2  
CCꢀ  
OHꢀ  
OH  
OH  
OH  
OH  
OL  
OL  
OL  
OL  
2.2  
– 0.2  
V
2.3–2.7  
2.3–2.7  
2.3–2.7  
2.3  
V
V
V
OHB  
CCB  
1.7  
V
V
3.0–3.6  
3.0–3.6  
3.0–3.6  
3.0  
0.2  
0.55  
0.2  
OLꢀ  
2.3–2.7  
2.3–2.7  
2.3–2.7  
= 100µꢀ  
= 1ꢂmꢀ  
OLB  
0.6  
I
Input Leakage Current ꢁ OE,  
T/R  
3.0–3.6  
0V V 3.6V  
5.0  
µꢀ  
µꢀ  
I
I
I
3-STTE Output Leakage ꢁ ꢀ  
2.3–2.7  
3.0–3.6  
0V V 3.6V,  
10  
OZ  
n
O
OE = V  
,
CCꢀ  
V = V or V  
IL  
I
IH  
I
Power OFF Leakage Current  
Quiescent Supply Current,  
0
0
0 (V , V ) 3.6V  
10  
20  
µꢀ  
µꢀ  
OFF  
I
O
I
/I  
2.3–2.7  
3.0–3.6  
= V  
or GND,  
CCꢀ  
CCꢀ CCB  
n
per supply, V  
/V  
CCꢀ CCB  
B , OE, & T/R = V  
n
CCB  
or GND  
2.3–2.7  
3.0–3.6  
V
V
3.6V,  
20  
µꢀ  
CCꢀ  
CCB  
n
B , OE,  
n
T/R 3.6V  
I  
Increase in I per Input, B ,  
T/R, OE  
2.3–2.7  
2.3–2.7  
3.0–3.6  
3.0–3.6  
V = V  
– 0.6V  
750  
750  
µꢀ  
µꢀ  
CC  
CC  
n
I
CCB  
Increase in I per Input, ꢀ  
V = V  
– 0.6V  
CC  
n
I
CCꢀ  
©2000 Fairchild Semiconductor Corporation  
74VCX163245 Rev. 1.7  
www.fairchildsemi.com  
7
AC Electrical Characteristics  
T
= –40°C to +85°C, C = 30 pF, R = 500Ω  
A
L
L
V
V
= 1.65V to 1.95V, V  
= 1.65V to 1.95V,  
V
CCB  
= 2.3V to 2.7V,  
= 3.0V to 3.6V  
CCB  
CCB  
= 2.3V to 2.7V  
V
= 3.0V to 3.6V  
V
CCA  
CCA  
CCA  
Symbol  
Parameter  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Units  
t
, t  
Propagation Delay,  
ꢀ to B  
1.5  
0.ꢂ  
1.5  
0.ꢂ  
0.ꢂ  
0.ꢂ  
5.ꢂ  
1.5  
0.6  
1.5  
0.6  
0.ꢂ  
0.6  
6.2  
0.ꢂ  
4.4  
ns  
PHL PLH  
t
, t  
Propagation Delay,  
B to ꢀ  
5.5  
ꢂ.3  
5.3  
4.6  
5.2  
0.05  
5.1  
ꢂ.2  
5.1  
4.5  
5.6  
0.5  
0.6  
0.ꢂ  
0.6  
0.ꢂ  
0.6  
4.0  
4.6  
4.0  
4.4  
4.ꢂ  
0.75  
ns  
ns  
ns  
ns  
ns  
ns  
PHL PLH  
t
t
t
t
, t  
Output Enable Time,  
OE to B  
PZL PZH  
, t  
Output Enable Time,  
OE to ꢀ  
PZL PZH  
, t  
Output Disable Time,  
OE to B  
PLZ PHZ  
, t  
Output Disable Time,  
OE to ꢀ  
PLZ PHZ  
t
, t  
Output to Output  
osHL osLH  
(7)  
Skew  
Note:  
7. Skew is defined as the absolute value of the difference between the actual propagation delay for any two  
separate outputs of the same device. The specification applies to any outputs switching in the same direction,  
either HIGH-to-LOW (t ) or LOW-to-HIGH (t ).  
osHL  
osLH  
Dynamic Switching Characteristics  
T = +25°C  
A
Symbol  
Parameter  
V
(V) V  
(V)  
Conditions  
Typical  
0.25  
0.25  
0.6  
Units  
CCB  
CCA  
V
Quiet Output Dynamic  
1.ꢂ  
2.5  
C = 30 pF, V = V  
,
V
OLP  
L
IH  
CC  
Peak V , ꢀ to B  
V
= 0V  
OL  
IL  
1.ꢂ  
2.5  
1.ꢂ  
1.ꢂ  
2.5  
1.ꢂ  
1.ꢂ  
2.5  
1.ꢂ  
1.ꢂ  
2.5  
1.ꢂ  
1.ꢂ  
2.5  
1.ꢂ  
1.ꢂ  
2.5  
3.3  
3.3  
2.5  
3.3  
3.3  
2.5  
3.3  
3.3  
2.5  
3.3  
3.3  
2.5  
3.3  
3.3  
2.5  
3.3  
3.3  
V
Quiet Output Dynamic  
C = 30 pF, V = V  
,
0.6  
V
V
V
V
V
OLP  
L
IH  
CC  
Peak V , B to ꢀ  
V
= 0V  
OL  
IL  
0.ꢂ  
0.ꢂ  
V
V
Quiet Output Dynamic  
C = 30 pF, V = V  
,
–0.25  
–0.25  
–0.6  
–0.6  
–0.ꢂ  
–0.ꢂ  
1.3  
OLV  
OLV  
OHV  
OHV  
L
IH  
CC  
Valley V , ꢀ to B  
V
= 0V  
OL  
IL  
Quiet Output Dynamic  
C = 30 pF, V = V  
,
L
IH  
CC  
Valley V , B to ꢀ  
V
= 0V  
OL  
IL  
V
V
Quiet Output Dynamic  
C = 30 pF, V = V  
,
L
IH  
CC  
Valley V , ꢀ to B  
V
= 0V  
OH  
IL  
1.3  
1.7  
Quiet Output Dynamic  
C = 30 pF, V = V  
,
1.7  
L
IH  
CC  
Valley V , B to ꢀ  
V
= 0V  
OH  
IL  
2.0  
2.0  
©2000 Fairchild Semiconductor Corporation  
74VCX163245 Rev. 1.7  
www.fairchildsemi.com  
Capacitance  
Symbol  
Parameter  
Conditions  
T = +25°C  
Units  
A
C
Input Capacitance  
V
or V  
= 2.5V, V  
= 3.3V, V = 0V  
5
pF  
IN  
I/O  
PD  
CCB  
CCꢀ  
CCꢀ  
CCꢀ  
I
CCꢀ/B  
C
C
Input/Output Capacitance  
V
= 2.5V, V  
= 3.3V, V = 0V  
6
pF  
pF  
CCB  
I
or V  
CCꢀ/B  
Power Dissipation Capacitance  
V
= 2.5V, V  
= 3.3V,  
20  
CCB  
V = 0V or V  
, f = 10MHz  
I
CCꢀ/B  
AC Loading and Waveforms  
Figure 1. AC Test Circuit  
Test  
Switch  
t
t
, t  
OPEN  
6V at V = 3.3 0.3V;  
PLH PHL  
, t  
PZL PLZ  
CC  
V
x 2 at V = 2.5 0.2V;  
CC  
CC  
1.ꢂV 0.15V  
t
, t  
GND  
PZH PHZ  
Figure 4. 3-STATE Output Low Enable and Disable  
Times for Low Voltage Logic  
t
= t 2.0 ns, 10% to 90%  
R
F
VCC  
Symbol 3.3V 0.3V 2.5V 0.2V 1.8V 0.15V  
V
1.5V  
1.5V  
V
V
/ 2  
/ 2  
V
V
/ 2  
/ 2  
mi  
CC  
CC  
CC  
CC  
Figure 2. Waveform for Inverting  
and Non-inverting Functions  
V
mo  
V
V
+ 0.3V  
V
+ 0.15V  
– 0.15V  
V
+ 0.15V  
– 0.15V  
t
= t 2.0 ns, 10% to 90%  
F
X
Y
OL  
OL  
OL  
R
V
V
– 0.3V  
V
V
OH  
OH  
OH  
Figure 3. 3-STATE Output High Enable and Disable  
Times for Low Voltage Logic  
t
= t 2.0 ns, 10% to 90%  
F
R
©2000 Fairchild Semiconductor Corporation  
74VCX163245 Rev. 1.7  
www.fairchildsemi.com  
9
Physical Dimensions  
Dimensions are in millimeters unless otherwise noted.  
Figure 5. 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide  
Package Number BGA54A  
©2000 Fairchild Semiconductor Corporation  
74VCX163245 Rev. 1.7  
www.fairchildsemi.com  
10  
Physical Dimensions (Continued)  
Dimensions are in millimeters unless otherwise noted.  
Figure 6. 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Package Number MTD48  
©2000 Fairchild Semiconductor Corporation  
74VCX163245 Rev. 1.7  
www.fairchildsemi.com  
11  
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The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an  
exhaustive list of all such trademarks.  
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Rev. I26  
©2000 Fairchild Semiconductor Corporation  
74VCX163245 Rev. 1.7  
www.fairchildsemi.com  
12  
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