74VHC08MTCX [ONSEMI]

四路 2 输入 AND 门极;
74VHC08MTCX
型号: 74VHC08MTCX
厂家: ONSEMI    ONSEMI
描述:

四路 2 输入 AND 门极

栅 光电二极管 逻辑集成电路 触发器
文件: 总8页 (文件大小:283K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
74VHC08  
Quad 2-Input AND Gate  
General Description  
The VHC08 is an advanced high speed CMOS 2 Input AND Gate  
fabricated with silicon gate CMOS technology. It achieves the  
high−speed operation similar to equivalent Bipolar Schottky TTL  
while maintaining the CMOS low power dissipation.  
www.onsemi.com  
The internal circuit is composed of 4 stages including buffer output,  
which provide high noise immunity and stable output. An input  
protection circuit insures that 0 V to 7 V can be applied to the input  
pins without regard to the supply voltage. This device can be used to  
interface 5 V to 3 V systems and two supply systems such as battery  
backup. This circuit prevents device destruction due to mismatched  
supply and input voltages.  
MARKING  
DIAGRAMS  
Order Number: 74VHC08M  
Features  
High Speed: t = 4.3 ns (Typ.) at T = 25°C  
PD  
A
SOIC14  
CASE 751EF  
High Noise Immunity: V  
= V = 28% V (Min.)  
NIH  
NIL  
CC  
A
WL  
Y
= Assembly Location  
= Wafer Lot  
= Year  
Power Down Protection is Provided on All Inputs  
Low Power Dissipation: I = 2 mA (Max.) @ T = 25°C  
CC  
A
WW  
= Work Week  
Low Noise: V  
= 0.8 V (Max.)  
Pin and Function Compatible with 74HC08  
OLP  
Order Number: 74VHC08MTCX  
14  
14  
AXYKK  
V08  
1
1
TSSOP−14 WB  
CASE 948G  
A
= Assembly Location  
XY  
KK  
= 2−digit 2 Weekly Date Code  
= 2−digit Lot Run Code  
Order Number: 74VHC08SJX  
14  
SOP14  
CASE 565BE  
AXYKK  
VHC08  
1
A
= Assembly Location  
XY  
KK  
= 2−digit 2 Weekly Date Code  
= 2−digit Lot Run Code  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 2 of this data sheet.  
© Semiconductor Components Industries, LLC, 2017  
1
Publication Order Number:  
June, 2019 − Rev. 3  
74VHC08/D  
74VHC08  
IEEE/IEC  
Figure 1. Connection Diagram  
PIN DESCRIPTION  
Figure 2. Logic Symbol  
TRUTH TABLE  
Pin Names  
Description  
A , B  
Inputs  
A
L
B
L
O
L
n
n
O
Outputs  
n
L
H
L
L
H
H
L
H
H
ORDERING INFORMATION  
Part Number  
Package Number  
M14A  
Package  
Packing Method  
74VHC08M  
SOIC14 (Pb−Free)  
SOP14 (Pb−Free)  
55 / Tube  
74VHC08SJ  
M14D  
2000 / Tape & Reel  
2500 / Tape & Reel  
74VHC08MTC  
MTC14  
TSSOP−14 WB (Pb−Free)  
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging  
Specifications Brochure, BRD8011/D  
www.onsemi.com  
2
74VHC08  
ABSOLUTE MAXIMUM RATINGS  
Symbol  
Parameter  
Rating  
–0.5 V to +7.0 V  
–0.5 V to +7.0 V  
–0.5 V to VCC + 0.5 V  
–20 mA  
Supply Voltage  
V
CC  
DC Input Voltage  
V
IN  
DC Output Voltage  
Input Diode Current  
Output Diode Current  
DC Output Current  
DC VCC / GND Current  
Storage Temperature  
V
OUT  
I
IK  
20 mA  
I
OK  
25 mA  
I
OUT  
50 mA  
I
CC  
–65°C to +150°C  
260°C  
T
STG  
T
L
Lead Temperature (Soldering, 10 seconds)  
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality  
should not be assumed, damage may occur and reliability may be affected.  
RECOMMENDED OPERATING CONDITIONS (Note 1)  
Symbol  
Parameter  
Rating  
Supply Voltage  
2.0 V to +5.5 V  
0 V to +5.5 V  
V
CC  
Input Voltage  
V
IN  
Output Voltage  
0 V to V  
V
CC  
OUT  
OPR  
Operating Temperature  
–40°C to +85°C  
T
t , t  
Input Rise and Fall Time,  
r
f
0 ns/V 100 ns/V  
0 ns/V 20 ns/V  
V
V
= 3.3 V 0.3 V  
= 5.0 V 0.5 V  
CC  
CC  
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond  
the Recommended Operating Ranges limits may affect device reliability.  
1. Unused inputs must be held HIGH or LOW. They may not float.  
www.onsemi.com  
3
74VHC08  
DC ELECTRICAL CHARACTERISTICS  
T
A
= 255C  
Typ  
T
= –405C to +855C  
A
Min  
Max  
Min  
1.50  
Max  
Symbol  
Parameter  
V
CC  
(V)  
Conditions  
Units  
V
2.0  
1.50  
V
IH  
HIGH Level Input  
Voltage  
3.0–5.5  
2.0  
0.7 x VCC  
0.7 x VCC  
V
0.50  
0.50  
V
V
IL  
LOW Level Input  
Voltage  
3.0–5.5  
2.0  
0.3 x VCC  
0.3 x VCC  
V
= V  
or VIL  
IOH = –50 mA  
V
OH  
1.9  
2.9  
2.0  
3.0  
4.5  
1.9  
2.9  
IN  
IH  
HIGH Level Output  
Voltage  
3.0  
4.5  
4.4  
4.4  
IOH = –4 mA  
IOH = –8 mA  
IOL = 50 mA  
3.0  
2.58  
3.94  
2.48  
3.80  
4.5  
V
= V  
or VIL  
V
OL  
2.0  
0.0  
0.0  
0.0  
0.1  
0.1  
0.1  
0.1  
V
IN  
IH  
LOW Level Output  
Voltage  
3.0  
4.5  
0.1  
0.1  
IOL = 4 mA  
IOL = 8 mA  
3.0  
0.36  
0.36  
0.1  
0.44  
0.44  
1.0  
4.5  
VIN = 5.5 V or GND  
VIN = VCC or GND  
I
0–5.5  
mA  
mA  
IN  
Input Leakage Current  
I
5.5  
2.0  
20.0  
CC  
Quiescent Supply  
Current  
NOISE CHARACTERISTICS  
T
A
= 255C  
Symbol  
Parameter  
V
(V)  
Conditions  
Units  
CC  
Typ  
0.3  
Limits  
(2)  
V
CL = 50 pF  
CL = 50 pF  
CL = 50 pF  
Quiet Output Maximum Dynamic VOL  
Quiet Output Minimum Dynamic VOL  
5.0  
0.8  
–0.8  
3.5  
V
V
V
OLP  
(2)  
V
5.0  
5.0  
–0.3  
OLV  
(2)  
V
IHD  
Minimum HIGH Level Dynamic Input  
Voltage  
(2)  
V
CL = 50 pF  
5.0  
1.5  
V
ILD  
Maximum LOW Level Dynamic Input  
Voltage  
2. Parameter guaranteed by design.  
www.onsemi.com  
4
 
74VHC08  
AC ELECTRICAL CHARACTERISTICS  
T
A
= 255C  
T
= –405C to +855C  
A
Min  
Typ  
Max  
8.8  
12.3  
5.9  
7.9  
10  
Min  
Max  
10.5  
14.0  
7.0  
Symbol  
, t  
Parameter  
V
(V)  
Conditions  
Units  
CC  
CL = 15 pF  
CL = 50 pF  
CL = 15 pF  
CL = 50 pF  
VCC = Open  
(Note 3)  
Propagation Delay  
3.3 0.3  
6.2  
8.7  
4.3  
5.8  
4
1.0  
1.0  
1.0  
1.0  
ns  
t
PHL PLH  
5.0 0.5  
ns  
9.0  
Input Capacitance  
10  
pF  
pF  
C
IN  
18  
C
PD  
Power Dissipation  
Capacitance  
3. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.  
Average operating current can be obtained by the equation: ICC (opr.) = CPD VCC fIN + ICC / 4 (per gate).  
www.onsemi.com  
5
 
MECHANICAL CASE OUTLINE  
PACKAGE DIMENSIONS  
SOIC14  
CASE 751EF  
ISSUE O  
DATE 30 SEP 2016  
Electronic versions are uncontrolled except when accessed directly from the Document Repository.  
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.  
DOCUMENT NUMBER:  
DESCRIPTION:  
98AON13739G  
SOIC14  
PAGE 1 OF 1  
ON Semiconductor and  
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.  
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding  
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically  
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the  
rights of others.  
© Semiconductor Components Industries, LLC, 2019  
www.onsemi.com  
MECHANICAL CASE OUTLINE  
PACKAGE DIMENSIONS  
TSSOP14 WB  
CASE 948G  
ISSUE C  
14  
DATE 17 FEB 2016  
1
SCALE 2:1  
NOTES:  
14X K REF  
1. DIMENSIONING AND TOLERANCING PER  
ANSI Y14.5M, 1982.  
M
S
S
V
0.10 (0.004)  
T U  
2. CONTROLLING DIMENSION: MILLIMETER.  
3. DIMENSION A DOES NOT INCLUDE MOLD  
FLASH, PROTRUSIONS OR GATE BURRS.  
MOLD FLASH OR GATE BURRS SHALL NOT  
EXCEED 0.15 (0.006) PER SIDE.  
4. DIMENSION B DOES NOT INCLUDE  
INTERLEAD FLASH OR PROTRUSION.  
INTERLEAD FLASH OR PROTRUSION SHALL  
NOT EXCEED 0.25 (0.010) PER SIDE.  
5. DIMENSION K DOES NOT INCLUDE DAMBAR  
PROTRUSION. ALLOWABLE DAMBAR  
PROTRUSION SHALL BE 0.08 (0.003) TOTAL  
IN EXCESS OF THE K DIMENSION AT  
MAXIMUM MATERIAL CONDITION.  
S
0.15 (0.006) T U  
N
0.25 (0.010)  
14  
8
2X L/2  
M
B
L
N
U−  
PIN 1  
IDENT.  
F
7
1
6. TERMINAL NUMBERS ARE SHOWN FOR  
REFERENCE ONLY.  
DETAIL E  
7. DIMENSION A AND B ARE TO BE  
DETERMINED AT DATUM PLANE W.  
S
K
0.15 (0.006) T U  
A
V−  
MILLIMETERS  
DIM MIN MAX  
INCHES  
MIN MAX  
K1  
A
B
C
D
F
G
H
J
4.90  
4.30  
−−−  
0.05  
0.50  
5.10 0.193 0.200  
4.50 0.169 0.177  
J J1  
1.20  
−−− 0.047  
0.15 0.002 0.006  
0.75 0.020 0.030  
SECTION NN  
0.65 BSC  
0.026 BSC  
0.60 0.020 0.024  
0.20 0.004 0.008  
0.16 0.004 0.006  
0.30 0.007 0.012  
0.25 0.007 0.010  
0.50  
0.09  
0.09  
0.19  
J1  
K
W−  
C
K1 0.19  
L
M
6.40 BSC  
0.252 BSC  
0.10 (0.004)  
0
8
0
8
_
_
_
_
SEATING  
PLANE  
T−  
H
G
DETAIL E  
D
GENERIC  
MARKING DIAGRAM*  
14  
SOLDERING FOOTPRINT  
XXXX  
XXXX  
ALYWG  
G
7.06  
1
1
A
L
= Assembly Location  
= Wafer Lot  
Y
W
G
= Year  
= Work Week  
= PbFree Package  
0.65  
PITCH  
(Note: Microdot may be in either location)  
*This information is generic. Please refer to  
device data sheet for actual part marking.  
PbFree indicator, “G” or microdot “G”, may  
or may not be present. Some products may  
not follow the Generic Marking.  
01.34X6  
14X  
1.26  
DIMENSIONS: MILLIMETERS  
Electronic versions are uncontrolled except when accessed directly from the Document Repository.  
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.  
DOCUMENT NUMBER:  
DESCRIPTION:  
98ASH70246A  
TSSOP14 WB  
PAGE 1 OF 1  
onsemi and  
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves  
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular  
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation  
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.  
© Semiconductor Components Industries, LLC, 2019  
www.onsemi.com  
onsemi,  
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates  
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.  
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/PatentMarking.pdf. onsemi reserves the right to make changes at any time to any  
products or information herein, without notice. The information herein is provided “asis” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the  
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use  
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products  
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