74VHC161284MTDX [ONSEMI]
IEEE 161284收发器;
| 型号： | 74VHC161284MTDX |
| 厂家： | 
ONSEMI |
| 描述： | IEEE 161284收发器 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总13页 (文件大小：324K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Is Now Part of
To learn more about ON Semiconductor, please visit our website at
www.onsemi.com
Please note: As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers
will need to change in order to meet ON Semiconductor’s system requirements. Since the ON Semiconductor
product management systems do not have the ability to manage part nomenclature that utilizes an underscore
(_), the underscore (_) in the Fairchild part numbers will be changed to a dash (-). This document may contain
device numbers with an underscore (_). Please check the ON Semiconductor website to verify the updated
device numbers. The most current and up-to-date ordering information can be found at www.onsemi.com. Please
email any questions regarding the system integration to Fairchild_questions@onsemi.com.
ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number
of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right
to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON
Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON
Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA
Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended
or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out
of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor
is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
February 1998
Revised June 2005
74VHC161284
IEEE 1284 Transceiver
General Description
Features
■ Supports IEEE 1284 Level 1 and Level 2 signaling
standards for bidirectional parallel communications
between personal computers and printing peripherals
The VHC161284 contains eight bidirectional data buffers
and eleven control/status buffers to implement
a full
IEEE 1284 compliant interface. The device supports the
IEEE 1284 standard and is intended to be used in
Extended Capabilities Port mode (ECP). The pinout allows
for easy connection from the Peripheral (A-side) to the
Host (cable side).
■ Replaces the function of two (2) 74ACT1284 devices
■ All inputs have hysteresis to provide noise margin
■ B and Y output resistance optimized to drive external
cable
Outputs on the cable side can be configured to be either
open drain or high drive ( 14 mA). The pull-up and pull-
down series termination resistance of these outputs on the
cable side is optimized to drive an external cable. In addi-
tion, all inputs (except HLH) and outputs on the cable side
contain internal pull-up resistors connected to the VCC sup-
■ B and Y outputs in high impedance mode during power
down
■ Inputs and outputs on cable side have internal pull-up
resistors
■ Flow-through pin configuration allows easy interface
ply to provide proper termination and pull-ups for open
drain mode.
between the Peripheral and Host
Outputs on the Peripheral side are standard LOW-drive
CMOS outputs. The DIR input controls data flow on the A1–
A8/B1–B8 transceiver pins.
Ordering Code:
Ordering Number Package Number
Package Description
74VHC161284MEA
74VHC161284MTD
MS48A
MTD48
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
© 2005 Fairchild Semiconductor Corporation
DS500098
www.fairchildsemi.com
Pin Descriptions
Truth Table
Pin Names
Description
Inputs
Outputs
HD
HIGH Drive Enable Input (Active HIGH)
Direction Control Input
Inputs or Outputs
DIR
HD
DIR
L
L
B1–B8 Data to A1–A8, and
A9–A13 Data to Y9–Y13 (Note 1)
C14–C17 Data to A14–A17
PLH Open Drain Mode
A1–A8
B1–B8
A9–A13
Y9–Y13
A14–A17
Inputs or Outputs
Inputs
Outputs
L
H
L
B1–B 8 Data to A1–A8, and
A9–A13 Data to Y9–Y13
Outputs
C
14–C17
Inputs
C14–C17 Data to A14–A17
A1–A8 Data to B1–B8 (Note 2)
A9–A13 Data to Y9–Y13 (Note 1)
PLHIN
PLH
Peripheral Logic HIGH Input
Peripheral Logic HIGH Output
Host Logic HIGH Input
Host Logic HIGH Output
H
HLHIN
HLH
C14–C17 Data to A14–A17
PLH Open Drain Mode
A1–A8 Data to B1–B8
A9–A13 Data to Y9–Y13
C14–C17 Data to A14–A17
H
H
Note 1: Y –Y Open Drain Outputs
9
13
Note 2: B –B Open Drain Outputs
1
8
Logic Diagram
www.fairchildsemi.com
2
Absolute Maximum Ratings(Note 3)
Recommended Operating
Conditions
Supply Voltage
VCC
0.5V to 7.0V
Supply Voltage
Input Voltage (VI) (Note 4)
A1–A 13, PLHIN, DIR, HD
B1–B8, C14–C17, HLHIN
B1–B8, C14–C17, HLHIN
VCC
4.5V to 5.5V
0V to VCC
0.5V to VCC 0.5V
0.5V to 5.5V (DC)
2.0V to 7.0V *
DC Input Voltage (VI)
Open Drain Voltage (VO)
Operating Temperature (TA)
0V to 5.5V
40 C to 85 C
*40 ns Transient
Output Voltage (VO)
A1–A8, A14–A17, HLH
B1–B 8, Y9–Y13, PLH
B1–B 8, Y9–Y13, PLH
0.5V to VCC 0.5V
0.5V to 5.5V (DC)
2.0V to 7.0V*
*40 ns Transient
DC Output Current (IO)
A1–A8, HLH
25 mA
50 mA
84 mA
50 mA
B1–B8, Y9–Y13
PLH (Output LOW)
PLH (Output HIGH)
Input Diode Current (IIK) (Note 4)
DIR, HD, A9–A13
,
PLH, HLH, C14–C17
Output Diode Current (IOK
A1–A8, A14–A17, HLH
B1–B8, Y9–Y13, PLH
DC Continuous VCC or
Ground Current
20 mA
)
50 mA
50 mA
Note 3: Absolute Maximum continuos ratings are those values beyond
which damage to the device may occur. Exposure to these indicated may
adversely affect device reliability. Functional operation under absolute max-
imum rated conditions is not implied.
200 mA
Note 4: Either voltage limit or current limit is sufficient to protect inputs.
Storage Temperature
ESD (HBM) Last Passing
Voltage
65 C to 150 C
2000V
DC Electrical Characteristics
V
T
40 C to 85 C
CC
A
Symbol
Parameter
Units
Conditions
(V)
3.0
Guaranteed Limits
V
V
Input Clamp Diode Voltage
1.2
V
I
18 mA
IK
I
Minimum HIGH Level Input Voltage
Maximum LOW Level Input Voltage
Minimum Input Hysteresis
A , PLH , DIR, HD
4.5 5.5
4.5 5.5
4.5 5.5
4.5 5.5
4.5 5.5
4.5 5.5
4.5 5.5
4.5 5.5
4.5 5.5
4.5 5.5
5.0
0.7 V
CC
IH
n
IN
B
2.0
2.3
2.6
n
V
C
n
HLH
IN
V
A , PLH , DIR, HD
0.3 V
CC
IL
n
n
IN
B
0.8
0.8
1.6
0.4
0.4
0.8
0.3
4.4
3.8
3.73
4.45
V
V
C
n
HLH
IN
VT
A , PLH , DIR, HD
V
V
V
V
–V
n
n
IN
T
T
T
B
–V
T
C
–V
–V
n
T
T
T
HLH
5.0
IN
T
V
Minimum HIGH Level Output Voltage
A , HLH
4.5
I
I
I
I
50 A
OH
n
OH
OH
OH
OH
4.5
8 mA
V
B , Y
n
4.5
14 mA
n
PLH
4.5
500 A
3
www.fairchildsemi.com
DC Electrical Characteristics (Continued)
V
T
40 C to 85 C
CC
A
Symbol
Parameter
Units
Conditions
50
(V)
4.5
4.5
4.5
4.5
5.0
5.0
5.0
5.0
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
0.0
0.0
0.0
5.5
Guaranteed Limits
V
Maximum LOW Level Output Voltage
A , HLH
0.1
0.44
0.77
0.7
I
I
I
I
A
OL
n
OL
OL
OL
OL
8 mA
V
B , Y
n
14 mA
84 mA
n
PLH
RD
RP
Maximum Output Impedance
Minimum Output Impedance
Maximum Pull-Up Resistance
Minimum Pull-Up Resistance
Maximum Input Current in HIGH State
B –B , Y –Y
55
(Note 5)(Note 6)
(Note 5)(Note 6)
1
8
9
13
13
B –B , Y –Y
35
1
8
9
B –B , Y –Y , C –C
1650
1150
1.0
1
8
9
13
14
17
B –B , Y –Y , C –C
1
8
9
13
14
17
I
I
I
I
A –A , PLH , HD, DIR, HLH
V
V
V
V
V
V
V
5.5V
5.5V
0.0V
0.0V
5.5V
5.5V
0.0V
IH
9
13
IN
IN
I
A
C
–C
100
1.0
14
17
I
Maximum Input Current in LOW State
A –A , PLH , HD, DIR, HLH
A
IL
9
13
IN
IN
I
C
–C
5.0
mA
14
17
I
Maximum Output Disable Current
(HIGH)
A —A
20
OZH
OZL
1
8
O
O
O
A
B –B
100
20
1
8
Maximum Output Disable Current
(LOW)
A —A
A
mA
A
1
8
B –B
5.0
1
8
I
I
I
I
Power Down Output Leakage
Power Down Input Leakage
B –B , Y –Y , PLH
100
100
250
70
V
V
5.5V
5.5V
OFF
OFF
OFF
CC
1
8
9
13
O
C
–C , HLH
IN
A
14
17
I
I
Power Down Leakage to V
Maximum Supply Current
A
(Note 7)
CC
CC
mA
V
V
or GND
I
CC
Note 5: Output impedance is measured with the output active LOW and active HIGH (HD HIGH).
Note 6: This parameter is guaranteed but not tested, characterized only.
Note 7: Power-down leakage to V
is tested by simultaneously forcing all pins on the cable-side (B –B , Y –Y , PLH, C –C and HLH to 5.5V and
1 8 9 13 14 17 IN
CC
measuring the resulting I
.
CC
www.fairchildsemi.com
4
AC Electrical Characteristics
T
40 C to 85 C
4.5V 5.5V
A
Figure
Number
Symbol
Parameter
V
Units
CC
Min
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
Max
30.0
30.0
30.0
30.0
30.0
30.0
30.0
30.0
6.0
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
A –A to B –B
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 1
Figure 2
Figure 3
Figure 3
Figure 1
Figure 2
Figure 3
Figure 3
(Note 9)
Figure 1
Figure 2
Figure 3
Figure 3
PHL
1
8
1
8
8
8
8
A –A to B –B
PLH
PHL
PLH
PHL
PLH
PHL
PLH
SKEW
PHL
PLH
PHL
PLH
PHZ
PLZ
PZH
PZL
PHZ
PLZ
pEN
1
8
1
B –B to A –A
1
8
1
B –B to A –A
1
8
1
A –A to Y –Y
9
13
9
13
13
A –A to Y –Y
9
13
9
C
–C to A –A
17 14
14
14
17
C
–C to A –A
17 14
17
LH-LH or HL-HL
PLH to PLH
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
30.0
30.0
30.0
30.0
18.0
18.0
25.0
25.0
25.0
25.0
IN
PLH to PLH
IN
HLH to HLH
IN
HLH to HLH
IN
Output Disable Time
DIR to A –A
ns
ns
ns
ns
Figure 7
Figure 8
Figure 9
Figure 2
Figure 2
1
8
Output Enable Time
DIR to A –A
1
8
Output Disable Time
DIR to B –B
1
8
Output Enable Time
HD to B –B , Y –Y
13
2.0
2.0
28.0
1
8
9
t
Output Disable Time
HD to B –B , Y –Y
13
pDis
28.0
20.0
ns
ns
1
8
9
t
t
t
t
–t
Output Enable-Output Disable
Output Slew Rate
pEn pDis
SLEW
PLH
B –B , Y –Y
0.05
0.05
0.40
0.40
120
120
Figure 5
Figure 4
Figure 6
(Note 10)
1
8
9
13
V/ns
ns
PHL
t , t
t
and t
RISE FALL
r
f
B –B , Y –Y (Note 8)
1
8
9
13
Note 8: Open Drain
Note 9: t is measured for common edge output transitions and compares the measured propagation delay for a given path type.
SKEW
(i) A –A to B –B , A –Y to Y –Y
13
1
8
1
8
9
13
9
(ii) B –B to A –A
8
1
8
1
(iii) C –C to A –A
17
14
17
14
Note 10: This parameter is guaranteed but not tested, characterized only.
Capacitance (Note 11)
Symbol
Parameter
Input Capacitance
I/O Pin Capacitance
Typ
5
Units
pF
Conditions
0.0V (HD, DIR, A —A , C —C , PLH and HLH )
IN
C
C
V
V
IN
CC
CC
9
13
14
17
IN
12
pF
3.3V
I/O
Note 11: Capacitance is measured at frequency 1 MHz.
5
www.fairchildsemi.com
AC Loading and Waveforms
Pulse Generator for all pulses: Rate 1.0 MHz; ZO 50 ; tf 2.5 ns, tr 2.5 ns.
FIGURE 1. Part A to B and A to Y Propagation Delay Load and Waveforms
FIGURE 2. Port A to B and a to Y Output Waveforms
FIGURE 3. Port B to A, C to A and HLHin to HLH Propagation Delay Waveforms
www.fairchildsemi.com
6
AC Loading and Waveforms (Continued)
FIGURE 4. Port A to B and A to Y HL Slew Test Load and Waveforms
FIGURE 5. Part A to b and A to Y LH Slew Test Load and Waveforms
t
t
Output Rise Time, Open Drain
Output Fall Time, Open Drain
r
f
FIGURE 6. tRISE and tFALL Test Load and Waveforms for Open Drain Outputs
A1–A8 to B1–B8, A9–A13 to Y9–Y13
7
www.fairchildsemi.com
AC Loading and Waveforms (Continued)
FIGURE 7. tPHZ and tPLZ Test Load and Waveforms, DIR to A1–A8
FIGURE 8. tPZH and tPZL Test Load and Waveforms, DIR to A1–A8
www.fairchildsemi.com
8
AC Loading and Waveforms (Continued)
FIGURE 9. tPHZ and tPLZ Test Load and Waveforms, DIR to B1–B8
9
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
Package Number MS48A
www.fairchildsemi.com
10
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
11
www.fairchildsemi.com
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
© Semiconductor Components Industries, LLC
www.onsemi.com
相关型号：
74VHC161284MTDX_NL
Line Transceiver, 13 Func, 14 Driver, 13 Rcvr, CMOS, PDSO48, 6.10 MM, MO-153, TSSOP-48
FAIRCHILD
74VHC161MX_NL
Binary Counter, AHC/VHC/H/U/V Series, Synchronous, Positive Edge Triggered, 4-Bit, Up Direction, CMOS, PDSO16, 0.150 INCH, MS-012, SOIC-16
FAIRCHILD
©2020 ICPDF网 联系我们和版权申明