87F008SU_技术文档

Ordering number : ENA1892581

LC87F0808A

CMOS IC

8K-byte FROM and 256-byte RAM integrated

http://onsemi.com

8-bit 1-chip Microcontroller

Overview

The LC87F0808A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of

50.0ns, integrates on a single chip a number of hardware features such as 8K-byte flash ROM (On-board-

programmable), 256-byte RAM, an On-chip-debugger, sophisticated 16-bit timers/counters (may be divided into 8-bit

timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), two 8-bit timers with

a prescaler, a base timer serving as a time-of-day clock, a high-speed clock counter, a synchronous SIO interface,

an asynchronous/synchronous SIO interface, a UART interface (full duplex), motor control PWM , a 10/8-bit 10-

channel AD converter, a system clock frequency divider, an internal reset and a 21-source 10-vector interrupt feature.

This microcomputer is suitable for small motor control equipment.

Features

Flash ROM

• Capable of On-board-programming with wide range (3.3 to 5.5V) of voltage source.

• Block-erasable in 128 byte units

Writable in 2-byte units

•

• 8192 × 8 bits

RAM

• 256 × 9 bits

Minimum Bus Cycle

• 50.0ns (20MHz at V =3.3V to 5.5V)

DD

Note: The bus cycle time here refers to the ROM read speed.

* This product is licensed from Silicon Storage Technology, Inc. (USA).

Semiconductor Components Industries, LLC, 2013

91510HKIM 20100823-S00001 No.A1828-1/25

May, 2013

Ver.1.00

LC87F0808A

Ports

• Normal withstand voltage I/O ports

Ports I/O direction can be designated in 1-bit units

Ports I/O direction can be designated in 4-bit units

• Dedicated oscillator ports/input ports

• Reset pin

20 (P1n, P20, P21, P30 to P35, P70 to P73)

8 (P0n)

2 (CF1/XT1, CF2/XT2)

1 (

RES

)

On-chip Debugger

•

1 (OWP0)

• Power pins

4 (V 1, V 2, V 1, V 2)

SS SS DD DD

Timers

• Timer 0: 16-bit timer/counter with a capture register.

Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) × 2 channels

Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register)

+ 8-bit counter (with an 8-bit capture register)

Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register)

Mode 3: 16-bit counter (with a 16-bit capture register)

• Timer 1: 16-bit timer/counter that supports PWM/toggle outputs

Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/

counter with an 8-bit prescaler (with toggle outputs)

Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels

Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs)

(toggle outputs also possible from the lower-order 8 bits)

Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs)

(The lower-order 8 bits can be used as PWM)

• Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs)

• Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs)

• Base timer

1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler

output.

2) Interrupts are programmable in 5 different time schemes

3) The base timer is unavailable when the CF oscillator circuit is selected

SIO

• SIO0: 8-bit Synchronous serial interface

1) LSB first/MSB first mode selectable

2)

transfer clock cycle=4/3tCYC)

Built-in 8-bit baudrate generator (maximum

• SIO1: 8-bit asynchronous/synchronous serial interface

Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)

Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)

Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)

Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)

UART

• Full Duplex

• 7/8/9 bit data bits selectable

• 1 Stop bit (2 bits in continuous data transmission)

• Built-in baudrate generator

AD Converter: 10 bits/8 bits × 10 channels (internal: 2 channels)

• 10/8 bits AD converter resolution selectable

Auto start function (It links an interrupt factor of MCPWM)

•

No.A1828-2/25

LC87F0808A

Remote Control Receiver Circuit (sharing pins with P73, INT3, and T0IN)

• Noise rejection function (noise filter time constant selectable from 1 tCYC/32 tCYC/128 tCYC)

Clock Output Function

• Can generate clock outputs with a frequency of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 of the source clock selected as

the system clock.

• Can generate the source clock for the subclock

Analog Comparator / Amplifier × 2 channels

• Analog comparator / amplifier selectable (each channel)

• Analog comparator Interrupt

MCPWM: Motor Control 12-bit PWM × 6 channels

• Dead time is programmable.

• Forced stop is possible by the output of the analog comparator and the INT terminals.

• Edge-aligned / center-aligned selectable

Watchdog Timer

• Can generate the internal reset signal on a timer overflow monitored by the WDT-dedicated low-speed

RC oscillation clock (30kHz).

• Allows selection of continue, stop, or hold mode operation of the counter on entry into the HALT/HOLD mode.

Interrupts

• 21 sources, 10 vector addresses

1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of

the level equal to or lower than the current interrupt are not accepted.

2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level

takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector

address takes precedence.

No.

1

Vector Address

00003H

Level

X or L

H or L

Interrupt Source

INT0

2

0000BH

00013H

INT1

3

INT2/T0L/INT4

INT3/Base timer

T0H

4

0001BH

00023H

5

6

0002BH

00033H

T1L/T1H

7

SIO0/UART1 receive

8

0003BH

00043H

SIO1/UART1 transmit/MCPWM

ADC/T6/T7

9

10

0004BH

Port 0/CMP1/CMP2

• Priority levels X > H > L

• Of interrupts of the same level, the one with the smallest vector address takes precedence.

Subroutine Stack Levels: 128levels (The stack is allocated in RAM.)

High-speed Multiplication/Division Instructions

• 16 bits × 8 bits

• 24 bits × 16 bits

• 16 bits ÷ 8 bits

• 24 bits ÷ 16 bits

(5 tCYC execution time)

(12 tCYC execution time)

(8 tCYC execution time)

(12 tCYC execution time)

No.A1828-3/25

LC87F0808A

Oscillation Circuits

• Internal oscillation circuits

Medium-speed RC oscillation circuit: For system clock (1MHz)

High-speed RC oscillation circuit:

Low-speed RC oscillation circuit:

• External oscillation circuits

For system clock (20MHz)

For watch dog timer (30kHz)

Hi-speed CF oscillation circuit:

For system clock, with internal Rf

Low speed crystal oscillation circuit:

For low-speed system clock, with internal Rf

1) The CF and crystal oscillation circuits share the same pins. The active circuit is selected under program control.

2) The CF and the crystal oscillation circuits stop operating in the system reset state and start oscillating when the

oscillation is enabled with an instruction.

System Clock Divider Function

• Can run on low current.

• The minimum instruction cycle selectable from 150ns, 300ns, 600ns, 1.2μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs and

38.4μs (at a main clock rate of 20MHz).

Internal Reset Function

• Power-on reset (POR) function

1) POR reset is generated only at power-on time.

2) The POR release level can be selected from 8 levels (1.67V, 1.97V, 2.07V, 2.37V, 2.57V, 2.87V, 3.86V and

4.35V) through option configuration.

• Low-voltage detection reset (LVD) function

1) LVD and POR functions are combined to generate resets when power is turned on and when power voltage falls

below a certain level.

2) The use/disuse of the LVD function and the low voltage threshold level (7 levels: 1.91V, 2.01V, 2.31V, 2.51V,

2.81V, 3.79V, 4.28V).

Standby Function

• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.

1) Oscillation is not halted automatically.

2) There are three ways of resetting the HALT mode.

(1) Setting the reset pin to the low level

(2) System resetting by watchdog timer or low-voltage detection

(3) Occurrence of an interrupt

• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.

1) The CF, RC and crystal oscillators automatically stop operation.

2) There are four ways of resetting the HOLD mode.

(1) Setting the reset pin to the lower level.

(2) System resetting by watchdog timer or low-voltage detection

(3) Having an interrupt source established at either INT0, INT1, INT2 or INT4

* INT0 and INT1 HOLD mode reset is available only when level detection is set.

(4) Having an interrupt source established at port 0.

• X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer.

1) The CF and RC oscillator automatically stop operation.

2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.

3) There are five ways of resetting the X'tal HOLD mode.

(1) Setting the reset pin to the low level.

(2) System resetting by watchdog timer or low-voltage detection.

(3) Having an interrupt source established at either INT0, INT1, INT2 or INT4

* INT0 and INT1 HOLD mode reset is available only when level detection is set.

(4) Having an interrupt source established at port 0.

(5) Having an interrupt source established in the base timer circuit.

Note: Available only when X’tal oscillation is selected.

No.A1828-4/25

LC87F0808A

On-chip Debugger

• Supports software debugging with the IC mounted on the target board.

Data Security Function (flash versions only)

• Protects the program data stored in flash memory from unauthorized read or copy.

Note: This data security function does not necessarily provide absolute data security.

Package Form

• QFP36 (7×7): Lead-/Halogen-free type

Development Tools

• On-chip debugger: TCB87 type C + LC87F0808A

Programming Boards

Package

Programming boards

W87F24Q

QFP36(7×7)

Flash ROM Programmer

Maker

Model

Supported Version

Rev 03.28 or later

Device

Single

AF9709/AF9709B/AF9709C

(Including Ando Electric Co., Ltd. models)

AF9723/AF9723B(Main body)

(Including Ando Electric Co., Ltd. models)

AF9833(Unit)

87f008SU

(3B247)

Programmer

Flash Support Group, Inc.

(FSG)

-

Gang

Programmer

(Including Ando Electric Co., Ltd. models)

SKK/SKK Type B

Single/Gang

Programmer

Gang

Application Version

1.06 or later

(SanyoFWS)

Chip Data Version

2.26 or later

SKK-4G

Programmer

(SanyoFWS)

Our company

LC87F0808

Application Version

1.06 or later

In-circuit/Gang

Programmer

SKK-DBG Type C

(SanyoFWS)

Chip Data Version

2.31 or later

For information about AF-Series:

Flash Support Group, Inc.

TEL: +81-53-459-1050

E-mail: sales@j-fsg.co.jp

No.A1828-5/25

LC87F0808A

Package Dimensions

unit : mm (typ)

3162C

9.0

7.0

27

19

28

18

10

36

1

9

0.15

0.65

0.3

(0.9)

SANYO : QFP36(7X7)

Pin Assignment

P04/AN4

28

29

30

31

32

33

34

35

36

18

17

16

15

14

13

12

11

10

P14/SI1/SB1/CMP1O

P13/SO1/CMP1IA

P12/SCK0/CMP1IB

P11/SI0/SB0

P10/SO0

P35/PULSG2

P34/PULSG2

P33/PULSG1

P32/PULSG1

P05/AN5/CKO

P06/AN6/T6O

P07/AN7/T7O

P20/INT4

LC87F0808A

P21/INT4/BUZ

P70/INT0/T0LCP

P71/INT1/T0HCP

P72/INT2/T0LCP/T0IN

Top view

QFP36 (7×7) “Lead-/Halogen-free Type”

No.A1828-6/25

LC87F0808A

QFP36

1

NAME

P73/INT3/T0HCP/T0IN

RES

QFP36

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

NAME

P15/SCK1/CMP2IB(+)

P16/T1PWML/UTX/CMP2IA(-)

P17/T1PWMH/URX/CMP2O

2

OWP0

3

V

1

V

2

4

SS

DD

CF1/XT1

CF2/XT2

5

V

SS

6

P00/AN0

P01/AN1

V

1

7

DD

P30/PULSG0

PULSG0

8

P02/AN2

P31/

P32/PULSG1

PULSG1

9

P03/AN3

10

11

12

13

14

15

16

17

18

P04/AN4

P33/

P34/PULSG2

PULSG2

P05/AN5/CKO

P06/AN6/T6O

P07/AN7/T7O

P20/INT4

P35/

P10/SO0

P11/SI0/SB0

P21/INT4/BUZ

P70/INT0/T0LCP

P71/INT1/T0HCP

P72/INT2/T0LCP/T0IN

P12/SCK0/CMP1IB(+)

P13/SO1/CMP1IA(-)

P14/SI1/SB1/CMP1O

No.A1828-7/25

LC87F0808A

System Block Diagram

Interrupt control

IR

PLA

Flash ROM

Standby control

CF/

X'tal

RC

PC

MRC

ACC

RES

B register

WDT

Reset circuit

(LVD/POR)

C register

SIO0

SIO1

Bus interface

ALU

Port 0

Port 1

PSW

RAR

Timer 0

Timer 1

Port 2/INT4

Port 3

RAM

Timer 6

Stack pointer

Timer 7

Base timer

MCPWM

UART1

Port 7

ADC

On-chip debugger

INT0-2

INT3 (Noise filter)

No.A1828-8/25

LC87F0808A

Pin Description

Pin Name

I/O

Description

Option

No

V

1,V

2

-

- Power supply pins

+ Power supply pins

SS SS

1, V

2

-

No

DD

Port 0

I/O

• 8-bit I/O port

• I/O specifiable in 4-bit units

P00 to P07

• Pull-up resistors can be turned on and off in 4-bit units.

• HOLD reset input

• Port 0 interrupt input

Yes

• Pin functions

P05: System clock output

P06: Timer 6 toggle output

P07: Timer 7 toggle output

P00 (AN0) to P07 (AN7): AD converter input

• 8-bit I/O port

Port 1

I/O

• I/O specifiable in 1-bit units

• Pull-up resistors can be turned on and off in 1-bit units.

• Pin functions

P10 to P17

P10: SIO0 data output

P11: SIO0 data input/bus I/O

P12: SIO0 clock I/O

P14: SIO1 data input / bus I/O

P15: SIO1 clock I/O

P16: Timer 1 PWML output / UART transmit

P17: Timer 1 PWMH output / UART receive

P13: SIO1 data output

Yes

analog comparator / amplifier I/O pins

P12 to P17:

P12: CMP1(+) input / AMP1(+) input

P13: CMP1(-) input / AMP1(-) input

P14: CMP1 output / AMP1 output

P15: CMP2(+) input / AMP2(+) input

P16: CMP2(-) input / AMP2(-) input

P17: CMP2 output / AMP2 output

Port 2

I/O

• 2-bit I/O port

• I/O specifiable in 1-bit units

P20 to P21

• Pull-up resistors can be turned on and off in 1-bit units.

• Pin functions

P21: Beeper output

P20 to P21: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/

timer 0H capture input

Yes

Interrupt acknowledge types

Rising &

Rising

enable

Falling

enable

H level

disable

L level

Falling

enable

INT4

disable

Port 3

I/O

• 6-bit I/O port

• I/O specifiable in 1-bit units

P30 to P35

• Pull-up resistors can be turned on and off in 1-bit units.

• Pin functions

P30 to p35 : motor control PWM output pins

P30: PULSG0 output

Yes

PULSG0

P31:

P32: PULSG1 output

PULSG1

output

P33:

P34: PULSG2 output

PULSG2

output

P35:

output

Continued on next page.

No.A1828-9/25

LC87F0808A

Continued from preceding page.

Pin Name

Port 7

I/O

Description

Option

• 4-bit I/O port

• I/O specifiable in 1-bit units

P70 to P73

• Pull-up resistors can be turned on and off in 1-bit units.

• Pin functions

P70: INT0 input/HOLD reset input/timer 0L capture input

P71: INT1 input/HOLD reset input/timer 0H capture input

P72: INT2 input/HOLD reset input/timer 0 event input / timer 0L capture input

P73: INT3 input (with noise filter)/ timer 0 event input/timer 0H capture input

Interrupt acknowledge types

No

Rising &

Rising

Falling

H level

L level

Falling

disable

enable

INT0

INT1

INT2

INT3

enable

disable

enable

disable

OWP0

RES

I/O

I

On-chip debugger (exclusive pin)

External reset input/internal reset output

No

CF1/XT1

• Ceramic resonator or 32.768kHz crystal oscillator input pin

• Pin function

No

General-purpose input port

CF2/XT2

I/O

• Ceramic resonator or 32.768kHz crystal oscillator output pin

• Pin function

General-purpose input port

Port Output Types

The table below lists the types of port outputs and the presence/absence of a pull-up resistor.

Data can be read into any input port even if it is in the output mode.

Option selected in

Port Name

Option type

Output type

Pull-up resistor

units of

1 bit

P00 to P07

1

2

CMOS

Programmable (Note 1)

No

Nch-open drain

CMOS

P10 to P17

P20 to P21

P30 to P35

P70 to P73

1 bit

-

1

Programmable

2

Nch-open drain

CMOS

1

2

Nch-open drain

CMOS

1

2

Nch-open drain

CMOS

No

Note 1: The control of the presence or absence of the programmable pull-up resistors for port 0 and the switching

between low-and high-impedance pull-up connection is exercised in nibble (4-bit) units (P00 to 03 or

P04 to 07).

No.A1828-10/25

LC87F0808A

User Option Table

Option name

Option to be applied on

Flash-rom version

Option selected in units of

1 bit

Option selection

Port output type

P00 to P07

P10 to P17

P20 to P21

P30 to P35

-



CMOS

Nch-open drain

CMOS

1 bit

Nch-open drain

CMOS

1 bit

Nch-open drain

CMOS

1 bit

Nch-open drain

00000h

Program start

address

-

01E00h

-

00000h to 01BFFh

01C00h to 01EFFh

Enable: Use

Protect area

(Note 1)

Low-voltage

detection reset

function

Detect function

Disable: Not Used

7-level

Detect level



-

Power-on reset

function

Power-On reset level

8-level

(Note 1) This option selects the area to be write protected at the time of the On-board writing.

Recommended Unused Pin Connections

Recommended unused pin connections

Port Name

Board

Software

P00 to P07

P10 to P17

P20 to P21

P30 to P35

P70 to P73

CF1/XT1

Open

Output low

Open

Output low

Open

Output low

Open

Output low

Pulled low with a 100kΩ resistor or less

General-purpose input port

CF2/XT2

On-chip Debugger Pin Connection Requirements

OWP0 of the On-chip-debugger terminal must add pull-down resistor of 100kΩ.

The connection with TCB87 Type C are OWP0/V /V

DD SS

Note: Be sure to electrically short-circuit between the V 1 and V 2 pins and between the V 1 and V 2 pins.

SS

DD

No.A1828-11/25

LC87F0808A

Absolute Maximum Ratings at Ta = 25°C, V 1 = V 2 = 0V

SS

Specification

typ max

Parameter

Symbol

Pin/Remarks

Conditions

V

[V]

min

-0.3

unit

V

DD

Maximum supply

voltage

V

max

V 1

DD

+6.5

+0.3

Input voltage

V

CF1

CF2

-0.3

V

I

DD

Input/output

voltage

IO

Ports 0, 1, 2, 3

Port 7

+0.3

DD

Peak output

current

IOPH(1)

Ports 0, 1, 2, 3

CMOS output select

Per 1 applicable pin

-10

-5

IOPH(2)

IOMH(1)

Port7

Mean output

current

Ports 0, 1, 2, 3

CMOS output select

Per 1 applicable pin

-7.5

(Note 1-1)

IOMH(2)

ΣIOAH(1)

ΣIOAH(2)

IOPL(1)

Port7

-3

-25

Total output

current

Ports 0, 2, 7

Ports 1, 3

Total of all applicable pins

Per 1 applicable pin

Peak output

current

P02 to P07

Ports 1, 2, 3

P00, P01

20

mA

IOPL(2)

IOPL(3)

IOML(1)

Per 1 applicable pin

30

10

Port 7

Mean output

current

P02 to P07

Ports 1, 2, 3

P00, P01

15

(Note 1-1)

IOML(2)

IOML(3)

ΣIOAL(1)

ΣIOAL(2)

Pd max(1)

Per 1 applicable pin

20

7.5

45

Port 7

Per 1 applicable pin

Total output

current

Ports 0, 2, 7

Ports 1, 3

QFP36(7×7)

Total of all applicable pins

45

Power

Ta=-40 to +85°C

Package only

115

244

+85

Dissipation

Pd max(2)

Ta=-40 to +85°C

Package with thermal

resistance board

(Note 1-2)

mW

Operating ambient

Temperature

Topr

Tstg

-40

-55

°C

Storage ambient

temperature

+125

Note 1-1: The mean output current is a mean value measured over 100ms.

Note 1-2: SEMI standards thermal resistance board (size: 76.1×114.3×1.6tmm, glass epoxy) is used.

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating

Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

No.A1828-12/25

LC87F0808A

Allowable Operating Conditions at Ta = -40°C to +85°C, V 1 = V 2 = 0V

SS

Specification

Parameter

Symbol

Pin/Remarks

Conditions

V

[V]

min

3.3

typ max

unit

DD

Operating

V

1, V

2

0.142μs ≤ tCYC ≤ 200μs

DD

5.5

supply voltage

Memory

VHD

1, V

2

RAM and register contents sustained

in HOLD mode.

sustaining

2.0

supply voltage

High level

V

(1)

Ports 1, 2, 3, 7

Ports 0

3.3 to 5.5 0.3V +0.7

DD

V

IH

DD

input voltage

(2)

(3)

3.3 to 5.5 0.3V +0.7

DD

V

CF1, CF2,

RES

3.3 to 5.5

4.0 to 5.5

3.3 to 4.0

4.0 to 5.5

3.3 to 4.0

3.3 to 5.5

0.75V

DD

Low level

(1)

(2)

(3)

Ports 1, 2, 3, 7

V

0.1V +0.4

DD

IL

SS

input voltage

0.2V

DD

V

Ports 0

0.15V +0.4

DD

0.2V

DD

V

CF1, CF2,

RES

0.25V

DD

Instruction

cycle time

(Note 2-1)

External

tCYC

3.3 to 5.5

0.142

200

20

μs

FEXCF

CF1

• CF2 pin open

system clock

frequency

• System clock frequency division

ratio=1/1

3.3 to 5.5

0.1

• External system clock duty=50 5%

20MHz ceramic oscillation

See Fig. 1.

Oscillation

frequency

range

FmCF(1)

FmCF(2)

FmCF(3)

FmMRC

CF1, CF2

3.3 to 5.5

20

10MHz ceramic oscillation

See Fig. 1.

10

4

MHz

(Note 2-2)

4MHz ceramic oscillation

See Fig. 1.

Internal High-speed RC oscillation.

1/2 frequency division ration.

3.3 to 5.5

19.0

20.0

21.0

(RCCTD=0)

(Note 2-3)

FmRC

FmSRC

FsX’tal

Internal medium-speed RC oscillation

Internal low-speed RC oscillation

3.3 to 5.5

0.5

15

1.0

30

2.0

60

kHz

XT1, XT2

32.768kHz crystal oscillation

See Fig. 1.

3.3 to 5.5

32.768

Note 2-1: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at

a division ratio of 1/2.

Note 2-2: See Tables 1 and 2 for the oscillation constants.

Note 2-3: When switching the system clock, allow an oscillation stabilization time of 100μs or longer after the

high-speed RC oscillator circuit transmits from the "oscillation stopped" to "oscillation enabled" state.

No.A1828-13/25

LC87F0808A

Electrical Characteristics at Ta = -40°C to +85°C, V 1 = V 2 = 0V

SS

Specification

typ max

Parameter

Symbol

Pin/Remarks

Conditions

V

[V]

min

unit

DD

High level input

current

I

(1)

Ports 0, 1, 2, 3

Port 7

Output disabled

Pull-up resistor off

=V

IH

V

3.3 to 5.5

1

RES

IN DD

(Including output Tr's off leakage

current)

I

(2)

IH

CF1, CF2

V

=V

15

IN DD

μA

Low level input

current

(1)

Ports 0, 1, 2, 3

Port 7

Output disabled

IL

Pull-up resistor off

V

=V

-1

RES

IN SS

(Including output Tr's off leakage

current)

I

(2)

CF1, CF2

V

I

=V

3.3 to 5.5

4.5 to 5.5

3.3 to 5.5

4.5 to 5.5

3.3 to 5.5

4.5 to 5.5

3.3 to 5.5

4.5 to 5.5

3.3 to 5.5

-15

-1

IL

IN SS

High level output

voltage

V

(1)

Ports 0, 1, 2, 7

=-1mA

V

OH

DD

(2)

(3)

(4)

I

=-0.35mA

V

-0.4

-1

OH

DD

V

Port 3

=-6mA

OH

DD

=-1.4mA

-0.4

OH

DD

Low level output

voltage

(1)

(2)

(3)

(4)

(5)

Ports 0, 1, 2, 3

=10mA

=1.4mA

=25mA

=4mA

1.5

0.4

1.5

0.4

V

OL

Port 7

P00, P01

Pull-up resistance

Rpu(1)

Ports 0, 1, 2, 3

Port 7

V

=0.9V

OH

DD

When Port 0 selected

low-impedance pull-up.

4.5 to 5.5

15

35

80

kΩ

Rpu(2)

Port 0

V

=0.9V

OH

DD

When Port 0 selected

3.3 to 5.5

100

210

400

high-impedance pull-up.

When Port 2 selected INT4.

Hysteresis voltage

Pin capacitance

VHYS

CP

Ports 1, 2, 3, 7

RES

0.1V

V

DD

10

All pins

For pins other than that under test:

V

=V

IN SS

3.3 to 5.5

pF

f=1MHz

Ta=25°C

No.A1828-14/25

LC87F0808A

Serial I/O Characteristics at Ta = -40°C to +85°C, V 1 = V 2 = 0V

SS

SIO0 Serial I/O Characteristics (Note 4-1-1)

Specification

Pin/

Parameter

Symbol

Conditions

• See Fig. 5.

Remarks

V

[V]

min

typ

max

unit

DD

Frequency

tSCK(1)

SCK0(P12)

2

1

Low level

tSCKL(1)

tSCKH(1)

3.3 to 5.5

pulse width

High level

pulse width

Frequency

tCYC

1

tSCK(2)

SCK0(P12)

• CMOS output selected

• See Fig. 5.

4/3

Low level

pulse width

tSCKL(2)

1/2

3.3 to 5.5

tSCK

High level

tSCKH(2)

tsDI(1)

pulse width

Data setup time

SB0(P11),

SI0(P11)

• Must be specified with

respect to rising edge of

SIOCLK.

0.05

Data hold time

thDI(1)

tdD0(1)

• See Fig. 5.

Output delay

time

SO0(P10),

SB0(P11)

• Continuous data

(1/3)tCYC

+0.08

transmission/reception mode

(Note 4-1-2)

μs

tdD0(2)

tdD0(3)

• Synchronous 8-bit mode

(Note 4-1-2)

1tCYC

+0.08

3.3 to 5.5

(Note 4-1-2)

(1/3)tCYC

+0.08

Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.

Note 4-1-2: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of

output state change in open drain output mode. See Fig. 5.

SIO1 Serial I/O Characteristics (Note 4-2-1)

Specification

Pin/

Parameter

Frequency

Symbol

tSCK(3)

Conditions

Remarks

V

[V]

min

typ

max

unit

DD

SCK1(P15)

See Fig. 5.

2

1

2

Low level

tSCKL(3)

tSCKH(3)

tSCK(4)

tSCKL(4)

tSCKH(4)

tsDI(2)

3.3 to 5.5

pulse width

High level

pulse width

Frequency

tCYC

SCK1(P15)

• CMOS output selected

• See Fig. 5.

Low level

pulse width

High level

1/2

tSCK

pulse width

Data setup time

SB1(P14),

SI1(P14)

• Must be specified with respect

to rising edge of SIOCLK.

• See Fig. 5.

0.05

Data hold time

thDI(2)

tdD0(4)

μs

Output delay time

SO1(P13),

SB1(P14)

• Must be specified with respect

to falling edge of SIOCLK.

• Must be specified as the time

to the beginning of output state

change in open drain output

mode.

(1/3)tCYC

+0.08

3.3 to 5.5

• See Fig. 5.

Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.

No.A1828-15/25

LC87F0808A

Pulse Input Conditions at Ta = -40°C to +85°C, V 1 = V 2 = 0V

SS SS

Specification

typ max

Parameter

Symbol

Pin/Remarks

Conditions

V

[V]

min

unit

tCYC

μs

DD

High/low level

pulse width

tPIH(1)

tPIL(1)

INT0(P70),

• Interrupt source flag can be set.

• Event inputs for timer 0 or 1 are

enabled.

INT1(P71),

3.3 to 5.5

1

2

INT2(P72),

INT4(P20 to P21)

INT3(P73) when noise

filter time constant is

1/1

tPIH(2)

tPIL(2)

• Interrupt source flag can be set.

• Event inputs for timer 0 are

enabled.

3.3 to 5.5

tPIH(3)

tPIL(3)

INT3(P73) when noise

filter time constant is

1/32

• Interrupt source flag can be set.

• Event inputs for timer 0 are

nabled.

64

tPIH(4)

tPIL(4)

INT3(P73) when noise

filter time constant is

1/128

• Interrupt source flag can be set.

• Event inputs for timer 0 are

enabled.

3.3 to 5.5

256

200

RES

tPIL(5)

• Resetting is enabled.

AD Converter Characteristics at V 1 = V 2 = 0V

SS SS

10bits AD Converter Mode/Ta = -40°C to +85°C

Specification

typ max

10

Parameter

Symbol

Pin/Remarks

Conditions

V

[V]

min

unit

bit

DD

Resolution

N

AN0(P00) to

AN7(P07)

3.3 to 5.5

Absolute

ET

(Note 6-1)

3.3 to 5.5

16

LSB

μs

AN8(AMP1O)

AN9(AMP2O)

accuracy

Conversion time

TCAD

VAIN

• See Conversion time calculation

3.3 to 5.5

8.5

59.5

formulas. (Note 6-2)

Analog input

voltage range

Analog port

input current

V

SS

DD

IAINH

IAINL

VAIN=V

DD

3.3 to 5.5

1

μA

VAIN=V

SS

-1

8bits AD Converter Mode/Ta = -40°C to +85°C

Specification

typ max

Parameter

Symbol

Pin/Remarks

Conditions

V

[V]

min

unit

bit

DD

Resolution

N

AN0(P00) to

AN7(P07)

3.3 to 5.5

8

Absolute

ET

(Note 6-1)

1.5

20

LSB

μs

AN8(AMP1O)

AN9(AMP2O)

accuracy

Conversion time

TCAD

VAIN

• See Conversion time calculation

3.3 to 5.5

2.9

formulas. (Note 6-2)

Analog input

voltage range

Analog port

input current

V

SS

DD

IAINH

IAINL

VAIN=V

DD

3.3 to 5.5

1

μA

VAIN=V

SS

-1

Conversion time calculation formulas:

10bits AD Converter Mode: TCAD (Conversion time) = ((42/(AD division ratio))+2)×(1/3)×tCYC

8bits AD Converter Mode: TCAD (Conversion time) = ((28/(AD division ratio))+2)× (1/3)×tCYC

No.A1828-16/25

LC87F0808A

AD division ratio

(ADDIV)

AD conversion time

(TCAD)

External

oscillation

(FmCF)

Operating supply

voltage range

System division ratio

(SYSDIV)

Cycle time

(tCYC)

(V

)

10bit AD

8bit AD

10bit AD

8bit AD

DD

3.3V to 5.5V

1/1

150ns

300ns

750ns

1/4

1/2

8.5μs

17μs

2.9μs

CF-20MHz

CF-10MHz

CF-4MHz

5.8μs

42.5μs

14.5μs

Note 6-1: The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must

be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog

input channel.

Note 6-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the

time the conversion results register(s) are loaded with a complete digital conversion value corresponding to

the analog input value.

The conversion time is 2 times the normal-time conversion time when:

• The first AD conversion is performed in the 10-bit AD conversion mode after a system reset.

• The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 10-bit

conversion mode.

Power-on Reset (POR) Characteristics at Ta = -40°C to +85°C, V 1=V 2=0V

SS

Specification

typ max

1.67 1.79

Parameter

Symbol

Pin/Remarks

Conditions

Option selected

voltage

min

unit

POR release

voltage

PORRL

• Select from option.

1.67V

1.97V

2.07V

2.37V

2.57V

2.87V

3.86V

4.35V

1.55

(Note 7-1)

1.85

1.95

2.25

2.45

2.75

3.73

4.21

1.97

2.07

2.37

2.57

2.87

3.86

4.35

2.09

2.19

2.49

2.69

2.99

3.99

4.49

V

Detection

POUKS

PORIS

• See Fig. 7.

voltage

(Note 7-2)

0.7

0.95

unknown state

Power supply

rise time

• Power supply rise

100

ms

time from 0V to 1.6V.

Note7-1: The POR release level can be selected out of 8 levels only when the LVD reset function is disabled.

Note7-2: POR is in an unknown state before transistors start operation.

No.A1828-17/25

LC87F0808A

Low Voltage Detection Reset (LVD) Characteristics at Ta = -40

°C to +85

°

C, V 1=V 2=0V

SS SS

Specification

typ

1.91

Parameter

Symbol

Pin/Remarks

Conditions

Option selected

voltage

min

max

2.01

unit

LVD reset voltage

(Note 8-2)

LVDET

• Select from option.

(Note 8-1)

1.91V

2.01V

2.31V

2.51V

2.81V

3.79V

4.28V

1.91V

2.01V

2.31V

2.51V

2.81V

3.79V

4.28V

1.81

1.91

2.21

2.41

2.71

3.69

4.18

2.01

2.31

2.51

2.81

3.79

4.28

55

2.11

2.41

2.61

2.91

3.89

4.38

(Note 8-3)

• See Fig. 8.

V

LVD hysteresys

width

LVHYS

55

mV

60

65

Detection voltage

unknown state

LVUKS

TLVDW

• See Fig. 8.

(Note 8-4)

0.7

0.95

V

Low voltage

• LVDET-0.5V

• See Fig. 9.

detection

0.2

ms

minimum width

(Reply sensitivity)

Note8-1: The LVD reset level can be selected out of 7 levels only when the LVD reset function is enabled.

Note8-2: LVD reset voltage specification values do not include hysteresis voltage.

Note8-3: LVD reset voltage may exceed its specification values when port output state changes and/or when a large

current flows through port.

Note8-4: LVD is in an unknown state before transistors start operation.

Comparator, Operational Amplifiers Characteristics at Ta=-40 to +85°C, V 1=V 2=0V

SS SS

Specification

Function

Parameter

Symbol

Pin/Remarks

Conditions

V

[V]

min

typ

max

unit

V

DD

CMP1, 2

Input common-

mode voltage

(Note9-1)

VCMIN

CMP1IA, CMP1IB

CMP2IA, CMP2IB

3.3 to

5.5

V

-

DD

V

SS

1.5V

Offset voltage

VOFF(1)

tCRT

CMP1IA, CMP1IB

CMP2IA, CMP2IB

CMP1O

Input common-mode

voltage range

3.3 to

5.5

20

mV

ns

CMP

• Input common-mode

voltage range

response

speed

CMP2O

3.3 to

5.5

200

• Input amplitude=100mV

• Over drive=50mV

AMP1, 2

AMP input

voltage

VAMIN

CMP1IA, CPM2IA

3.3 to

5.5

V

-

DD

V

SS

1.5V

(Note9-1)

Input offset

voltage

VOPOFF

SR

CMP1IA, CMP1IB

CMP2IA, CMP2IB

CMP1O

Input common-mode

voltage range

50pF

3.3 to

5.5

20

mV

Slew rate

5.0

3

V/μs

CMP2O

Output

current

Source

IoSource

CMP1IA,CMP1IB(+)=1V

CMP2IA,CMP2IB(-)=0V

5.0

2.5

0.3

3.5

mA

CMP1O,CMP2O=V -1.5V

DD

Sink

IoSink

CMP1IA,CMP1IB(+)=0V

CMP2IA,CMP2IB(-)=1V

5.0

0.35

CMP1O,CMP2O=V +0.5V

DD

Note9-1: When V =5V, input voltage is effective from 0 to 3.5V.

DD

No.A1828-18/25

LC87F0808A

Consumption Current Characteristics at Ta = -40°C to +85°C, V 1 = V 2 = 0V

SS

Specification

Pin/

Parameter

Symbol

Conditions

Remarks

V

[V]

min

typ max

unit

DD

Normal mode

consumption

current

IDDOP(1)

V

1,

2

• FmCF=20MHz ceramic oscillation mode

• System clock set to 20MHz side

• All internal RC oscillation stopped.

• 1/1 frequency division ratio

• FmCF=4MHz ceramic oscillation mode

• System clock set to 4MHz side

• All internal RC oscillation stopped.

• 1/1 frequency division ratio

• FsX’tal=32.768kHz crystal oscillation mode

• Internal medium speed RC oscillation

stopped.

DD

3.3 to 5.5

10

3

12.5

4.1

(Note 10-1)

(Note 10-2)

IDDOP(2)

IDDOP(3)

mA

3.3 to 5.5

9.2

11

• System clock set to internal high speed

RC oscillation (20MHz).

• 1/1 frequency division ratio

• FsX’tal=32.768kHz crystal oscillation mode

• Internal high speed RC oscillation stopped.

• System clock set to internal medium speed

RC oscillation.

IDDOP(4)

3.3 to 5.5

0.5

32

0.7

74

• 1/2 frequency division ratio

• FsX’tal=32.768kHz crystal oscillation mode

• System clock set to 32.768kHz crystal

oscillation.

IDDOP(5)

μA

• All internal RC oscillation stopped.

• 1/1 frequency division ratio

• HALT mode

HALT mode

consumption

current

IDDHALT(1)

IDDHALT(2)

IDDHALT(3)

V

1,

2

DD

• FmCF=20MHz ceramic oscillation mode

• System clock set to 20MHz side

• All internal RC oscillation stopped.

• 1/1 frequency division ratio

• HALT mode

4.7

1.5

5.8

2.3

(Note 10-1)

(Note 10-2)

• FmCF=4MHz ceramic oscillation mode

• System clock set to 4MHz side

• All internal RC oscillation stopped.

• 1/1 frequency division ratio

• HALT mode

• FsX’tal=32.768kHz crystal oscillation

mode

mA

• Internal medium speed RC oscillation

stopped.

3.3 to 5.5

4

5

• System clock set to internal high speed

RC oscillation (20MHz).

• 1/1 frequency division ratio

• HALT mode

IDDHALT(4)

IDDHALT(5)

• FsX’tal=32.768kHz crystal oscillation mode

• Internal high speed RC oscillation stopped.

• System clock set to internal medium speed

RC oscillation.

3.3 to 5.5

0.3

0.45

• 1/2 frequency division ratio

• HALT mode

• FsX’tal=32.768kHz crystal oscillation mode

• System clock set to 32.768kHz crystal

oscillation.

3.3 to 5.5

16

60

μA

• All internal RC oscillation stopped.

• 1/1 frequency division ratio

Note10-1: Values of the consumption current do not include current that flows into the output transistors and internal

pull-up resistors.

Note10-2: The consumption current values do not include operational current of LVD function if not specified.

Continued on next page.

No.A1828-19/25

LC87F0808A

Continued from preceding page.

Specification

typ max

Pin/

Parameter

Symbol

Conditions

Remarks

V

[V]

min

unit

DD

HOLD mode

consumption

current

IDDHOLD(1)

V

1,

2

HOLD mode

DD

V

• CF1=V

or open

3.3 to 5.5

0.03

3

32

35

DD

(External clock mode)

(Note 10-1)

(Note 10-2)

(Note 10-3)

μA

IDDHOLD(2)

HOLD mode

• CF1=V

DD

(External clock mode)

or open

• LVD option selected

Note10-1: Values of the consumption current do not include current that flows into the output transistors and internal

pull-up resistors.

Note10-2: The consumption current values do not include operational current of LVD function if not specified.

Note10-3: The amplifier / comparator circuit operates in the HOLD mode.

F-ROM Programming Characteristics at Ta = -40°C to +85°C, V 1 = V 2 = 0V

SS SS

Specification

Parameter

Symbol

Pin/Remarks

Conditions

V

[V]

min

typ max

unit

mA

DD

Onboard

IDDFW(1)

V

1, V

2

• Only current of the flash block.

DD DD

programming

current

3.3 to 5.5

5

10

Programming

time

tFW(1)

tFW(2)

• Erasing time

20

40

30

60

ms

• Programming time

μs

UART (Full Duplex) Operating Conditions at Ta = -40°C to +85°C, V 1 = V 2 = 0V

SS

Specification

Parameter

Symbol

Pin/Remarks

Conditions

V

[V]

min

16/3

typ

max

8192/3

unit

DD

Transfer rate

UBR

UTX(P16)

URX(P17)

3.3 to 5.5

tCYC

Data length

Stop bits

Parity bits

: 7/8/9 bits (LSB first)

: 1 bit (2-bit in continuous data transmission)

: None

Example of Continuous 8-bit Data Transmission Mode Processing (First Transmit Data=55H)

Start bit

Stop bit

End of

transmission

Start of

transmission

Transmit data (LSB first)

UBR

Example of Continuous 8-bit Data Reception Mode Processing (First Receive Data=55H)

Start bit

Stop bit

End of

reception

Start of

Receive data (LSB first)

reception

UBR

No.A1828-20/25

LC87F0808A

Characteristics of a Sample Main System Clock Oscillation Circuit

Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a Our

designated oscillation characteristics evaluation board and external components with circuit constant values with

which the oscillator vendor confirmed normal and stable oscillation.

Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator

MURATA

Oscillation

Circuit Constant

Operating

Voltage Range

[V]

Stabilization Time

Nominal

Type

Oscillator Name

Remarks

Frequency

C1

C2

Rf

Rd

typ

max

[ms]

[pF]

[Ω]

[ms]

SMD

LEAD

SMD

CSTCE20M0G51-R0

CSTLS20M0G52-B0

CSTCE10M0G52-R0

CSTLS10M0G53-B0

CSTCR4M00G53-R0

CSTLS4M00G53-B0

(5)

Open

470

330

470

680

1.5k

3.3 to 5.5

0.02

0.06

0.02

0.04

0.03

20MHz

10MHz

4MHz

(10)

(15)

(10)

(15)

Internal

C1,C2

LEAD

SMD

LEAD

The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after V

goes above the operating voltage lower limit (see Figure 3).

DD

Characteristics of a Sample Subsystem Clock Oscillator Circuit

Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a Our

designated oscillation characteristics evaluation board and external components with circuit constant values with which

the oscillator vendor confirmed normal and stable oscillation.

Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator

EPSON TOYOCOM

Oscillation

Circuit Constant

Operating

Voltage Range

[V]

Stabilization Time

Nominal

Oscillator

Name

Type

Remarks

Frequency

C1

C2

Rf

Rd

typ

[s]

max

[s]

[pF]

[Ω]

Applicable

CL value =

7.0pF

32.768kHz

SMD

MC-306

8

Open

330k

3.3 to 5.5

1.0

4.0

The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the

instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the

oscillation to get stabilized after the HOLD mode is reset (see Figure 3).

Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible

because they are vulnerable to the influences of the circuit pattern.

CF2/XT2

CF1/XT1

Rf

Rd

0.5V

DD

C1

C2

CF/X’tal

Figure 1 CF and XT Oscillator Circuit

Figure 2 AC Timing Measurement Point

No.A1828-21/25

LC87F0808A

V

DD

Operating V

lower limit

0V

DD

Power supply

Reset time

RES

Internal medium speed

RC oscillation

tmsCF/tmsX’tal

CF1, CF2

Operating

Unpredictable

Reset

Instruction execution

mode

Reset Time and Oscillation Stabilization Time

HOLD reset

signal

HOLD reset signal

absent

HOLD reset signal valid

Internal medium speed

RC oscillation or

low speed RC oscillation

tmsCF/tmsX’tal

CF1, CF2

(Note)

State

HOLD

HALT

HOLD Reset Signal and Oscillation Stabilization Time

Note: External oscillation circuit is selected.

Figure 3 Oscillation Stabilization Times

No.A1828-22/25

LC87F0808A

V

DD

Note:

External circuits for reset may vary

R

RES

depending on the usage of POR and LVD.

Please refer to the user’s manual for more

information.

RES

C

RES

Figure 4 Reset Circuit

SIOCLK:

DATAIN:

DATAOUT:

DI0

DI1

DI2

DI3

DI4

DI5

DI6

DI7

DO0

DO1

DO2

DO3

DO4

DO5

DO6

DO7

tSCK

tSCKL

tSCKH

thDI

SIOCLK:

DATAIN:

tsDI

tdDO

DATAOUT:

Figure 5 Serial I/O Output Waveforms

tPIL

tPIH

Figure 6 Pulse Input Timing Signal Waveform

No.A1828-23/25

LC87F0808A

POR release voltage

(PORRL)

(a)

(b)

V

DD

Reset period

100μs or longer

Unknown-state

(POUKS)

RES

Figure 7 Waveform observed when only POR is used (LVD not used)

(RESET pin: Pull-up resistor R only)

RES

• The POR function generates a reset only when power is turned on starting at the V level.

SS

• No stable reset will be generated if power is turned on again when the power level does not go down to the V level

SS

as shown in (a). If such a case is anticipated, use the LVD function together with the POR function or implement an

external reset circuit.

• A reset is generated only when the power level goes down to the V level as shown in (b) and power is turned on

SS

again after this condition continues for 100μs or longer.

LVD hysteresis width

LVD release voltage

(LVHYS)

(LVDET+LVHYS)

V

DD

LVD reset voltage

(LVDET)

Reset period

Unknown-state

(LVUKS)

RES

Figure 8 Waveform observed when both POR and LVD functions are used

(RESET pin: Pull-up resistor R only)

RES

• Resets are generated both when power is turned on and when the power level lowers.

• A hysteresis width (LVHYS) is provided to prevent the repetitions of reset release and entry cycles near the detection

level.

No.A1828-24/25

LC87F0808A

V

DD

LVD release voltage

LVD reset voltage

LVDET-0.5V

TLVDW

V

SS

Figure 9 Low voltage detection minimum width

(Example of momentary power loss/Voltage variation waveform)

ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number

of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at

www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no

warranty, representation or guarantee regarding the suitabilityof its products for any particular purpose, nor does SCILLC assume any liability arising out of the

application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental

damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual

performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical

experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use

as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in

which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for

any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors

harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or

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part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PS No.A1828-25/25


型号：	87F008SU
厂家：	ONSEMI
描述：	8-bit 1-chip Microcontroller 8位单芯片微控制器微控制器
文件：	总25页 (文件大小：176K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

87F008SU [ONSEMI]

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