ADP3414JRZ-REEL7 [ONSEMI]
Dual Bootstrapped MOSFET Driver;
| 型号： | ADP3414JRZ-REEL7 |
| 厂家： | 
ONSEMI |
| 描述： | Dual Bootstrapped MOSFET Driver 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总10页 (文件大小：428K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Dual Bootstrapped
MOSFET Driver
ADP3414
FEATURES
FUNCTIONAL BLOCK DIAGRAM
All-In-One Synchronous Buck Driver
Bootstrapped High Side Drive
One PWM Signal Generates Both Drives
Anticross-Conduction Protection Circuitry
Pulse-by-Pulse Disable Control
VCC
BST
IN
DRVH
SW
APPLICATIONS
Mobile Computing CPU Core Power Converters
Multiphase Desktop CPU Supplies
OVERLAP
PROTECTION
CIRCUIT
Single-Supply Synchronous Buck Converters
Standard-to-Synchronous Converter Adaptations
DRVL
ADP3414
GENERAL DESCRIPTION
PGND
The ADP3414 is a dual MOSFET driver optimized for driving
two N-channel MOSFETs which are the two switches in a
nonisolated synchronous buck power converter. Each of the
drivers is capable of driving a 3000 pF load with a 20 ns propa-
gation delay and a 30 ns transition time. One of the drivers can
be bootstrapped and is designed to handle the high voltage
slew rate associated with “floating” high side gate drivers.
The ADP3414 includes overlapping drive protection (ODP)
to prevent shoot-through current in the external MOSFETs.
The ADP3414 is specified over the commercial temperature
range of 0°C to 70°C and is available in an 8-lead SOIC package.
7V
12V
D1
VCC
ADP3414
BST
C
BST
DRVH
SW
IN
Q1
DELAY
+1V
DRVL
PGND
Q2
1V
Figure 1. General Application Circuit
©2010 SCILLC. All rights reserved.
May 2010 - Rev. 3
Publication Order Number:
ADP3414/D
1
(T = 0؇C to 70؇C, VCC = 7 V, BST = 4 V to 26 V, unless otherwise noted.)
A
ADP3414–SPECIFICATIONS
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
SUPPLY
Supply Voltage Range
Quiescent Current
VCC
ICCQ
4.15
7.5
2
V
mA
1
PWM INPUT
Input Voltage High2
Input Voltage Low2
2.3
V
V
0.8
HIGH SIDE DRIVER
Output Resistance, Sourcing Current
V
V
V
V
V
V
V
V
BST – VSW = 5 V
BST – VSW = 7 V
3.0
2.0
1.25
1.0
36
5.0
3.5
2.5
2.5
47
Ω
Ω
Output Resistance, Sinking Current
Transition Times3 (See Figure 2)
Propagation Delay3, 4 (See Figure 2)
BST – VSW = 5 V
BST – VSW = 7 V
Ω
Ω
trDRVH
tfDRVH
BST – VSW = 7 V, CLOAD = 3 nF
BST – VSW = 7 V, CLOAD = 3 nF
BST – VSW = 7 V
ns
ns
ns
ns
20
65
30
86
tpdhDRVH
tpdlDRVH
BST – VSW = 7 V
21
32
LOW SIDE DRIVER
Output Resistance, Sourcing Current
VCC = 5 V
VCC = 7 V
3.0
2.0
1.5
1.0
27
5.0
3.5
3.0
2.5
35
Ω
Ω
Output Resistance, Sinking Current
Transition Times3 (See Figure 2)
Propagation Delay3, 4 (See Figure 2)
VCC = 5 V
VCC = 7 V
Ω
Ω
trDRVL
tfDRVL
VCC = 7 V, CLOAD = 3 nF
VCC = 7 V, CLOAD = 3 nF
VCC = 7 V
ns
ns
ns
ns
19
30
26
35
tpdhDRVL
tpdlDRVL
VCC = 7 V
15
25
NOTES
1All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.
2Logic inputs meet typical CMOS I/O conditions for source/sink current (~1 µA).
3AC specifications are guaranteed by characterization but not production tested.
4For propagation delays, “tpdh” refers to the specified signal going high; “tpdl” refers to it going low.
Specifications subject to change without notice.
Rev. 3 | Page 2 of 9 | www.onsemi.com
ADP3414
ORDERING GUIDE
Temperature Package
ABSOLUTE MAXIMUM RATINGS*
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +8 V
BST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +30 V
BST to SW . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +8 V
SW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5.0 V to +25 V
IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V
Operating Ambient Temperature Range . . . . . . . 0°C to 70°C
Operating Junction Temperature Range . . . . . . 0°C to 125°C
θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155°C/W
θJC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
Package
Option
Model
Range
Description
ADP3414JR 0°C to 70°C
8-Lead Standard
SOIC-8
Small Outline (SOIC)
PIN CONFIGURATION
BST
IN
DRVH
SW
1
2
3
4
8
7
6
5
*This is a stress rating only; operation beyond these limits can cause the device to
be permanently damaged. Unless otherwise specified, all voltages are referenced
to PGND.
ADP3414
TOP VIEW
(Not To Scale)
PGND
DRVL
NC
VCC
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS
Pin
Mnemonic
Function
1
BST
Floating Bootstrap Supply for the Upper MOSFET. A capacitor connected between BST and SW Pins
holds this bootstrapped voltage for the high side MOSFET as it is switched. The capacitor should be
chosen between 100 nF and 1 F.
2
3
4
5
6
7
IN
TTL-level input signal that has primary control of the drive outputs.
No Connection
NC
VCC
DRVL
PGND
SW
Input Supply. This pin should be bypassed to PGND with ~1 µF ceramic capacitor.
Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.
Power Ground. Should be closely connected to the source of the lower MOSFET.
This pin is connected to the buck-switching node, close to the upper MOSFET’s source. It is the floating
return for the upper MOSFET drive signal. It is also used to monitor the switched voltage to prevent turn-
on of the lower MOSFET until the voltage is below ~1 V. Thus, according to operating conditions, the
high low transition delay is determined at this pin.
8
DRVH
Buck Drive. Output drive for the upper (buck) MOSFET.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADP3414 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
Rev. 3 | Page 3 of 9 | www.onsemi.com
ADP3414
IN
tfDRVL
tpdlDRVL
tpdlDRVH
trDRVL
DRVL
tfDRVH
tpdhDRVH trDRVH
DRVH-SW
V
V
TH
TH
tpdhDRVL
SW
1V
Figure 2. Nonoverlap Timing Diagram (Timing Is Referenced to the 90% and 10% Points Unless Otherwise Noted)
Rev. 3 | Page 4 of 9 | www.onsemi.com
Typical Performance Characteristics–
ADP3414
50
C
= 3nF
T
T
LOAD
T
= 25؇C
A
T
= 25؇C
VCC = 5V
A
45
DRVH @ VCC = 5V
DRVH
5V/DIV
DRVH
5V/DIV
VCC = 5V
40
35
30
25
DRVH @ VCC = 7V
R3
R3
DRVL @ VCC = 5V
DRVL
2V/DIV
IN
DRVL
5V/DIV
R2
R1
IN
2V/DIV
R2
R1
2V/DIV
DRVL @ VCC = 7V
40ns/DIV
40ns/DIV
20
0
25
JUNCTION TEMPERATURE – ؇C
50
75
100
125
TPC 1. DRVH Fall and DRVL Rise
Times
TPC 2. DRVL Fall and DRVH Rise
Times
TPC 3. DRVH and DRVL Rise Times
vs. Temperature
35
55
50
37
DRVL @ VCC = 7V
30
32
DRVH @ VCC = 5V
45
DRVL @ VCC = 7V
DRVL @ VCC = 5V
25
27
40
DRVH @ VCC = 7V
35
20
22
DRVH @ VCC = 7V
15
30
DRVL @ VCC = 5V
25
17
DRVH @ VCC = 5V
10
DRVH @ VCC = 5V
20
15
10
DRVL @ VCC = 7V
DRVH @ VCC = 7V
12
5
0
DRVL @ VCC = 5V
7
0
125
25
50
75
100
1.0
2.0
3.0
4.0
5.0
2.0
3.0
4.0
5.0
1.0 1.5
2.5
3.5
4.5
LOAD CAPACITANCE – nF
LOAD CAPACITANCE – nF
JUNCTION TEMPERATURE – ؇C
TPC 6. DRVH and DRVL Fall Times
vs. Load Capacitance
TPC 5. DRVH and DRVL Rise Times
vs. Load Capacitance
TPC 4. DRVH and DRVL Fall Times
vs. Temperature
8.5
8.0
35
T
= 25؇C
A
C
= 3nF
30
25
20
15
10
5
LOAD
VCC = 7V
7.5
VCC = 7V
C
= 3nF
7.0
6.5
6.0
5.5
5.0
LOAD
f
= 250kHz
IN
VCC = 5V
VCC = 5V
0
100
200
0
25
50
75
125
0
400 600 800 1000 1200 1400
IN FREQUENCY – kHz
JUNCTION TEMPERATURE – ؇C
TPC 7. Supply Current vs.
Frequency
TPC 8. Supply Current vs.
Temperature
Rev. 3 | Page 5 of 9 | www.onsemi.com
ADP3414
THEORY OF OPERATION
To prevent the overlap of the gate drives during Q2’s turn OFF
and Q1’s turn ON, the overlap circuit provides a internal delay
that is set to 50 ns. When the PWM input signal goes high, Q2
will begin to turn OFF (after a propagation delay), but before
Q1 can turn ON, the overlap protection circuit waits for the
voltage at DRVL to drop to around 10% of VCC. Once the
voltage at DRVL has reached the 10% point, the overlap protec-
tion circuit will wait for a 20 ns typical propagation delay. Once
the delay period has expired, Q1 will begin turn ON.
The ADP3414 is a dual MOSFET driver optimized for driving
two N-channel MOSFETs in a synchronous buck converter
topology. A single PWM input signal is all that is required to
properly drive the high side and the low side FETs. Each driver
is capable of driving a 3 nF load.
A more detailed description of the ADP3414 and its features
follows. Refer to the Functional Block Diagram.
Low Side Driver
The low side driver is designed to drive low RDS(ON) N-channel
MOSFETs. The maximum output resistance for the driver is
3.5 Ω for sourcing and 2.5 Ω for sinking gate current. The low
output resistance allows the driver to have 20 ns rise and fall
times into a 3 nF load. The bias to the low side driver is inter-
nally connected to the VCC supply and PGND.
APPLICATION INFORMATION
Supply Capacitor Selection
For the supply input (VCC) of the ADP3414, a local bypass
capacitor is recommended to reduce the noise and to supply some
of the peak currents drawn. Use a 1 µF, low ESR capacitor.
Multilayer ceramic chip (MLCC) capacitors provide the best
combination of low ESR and small size and can be obtained from
the following vendors:
When the driver is enabled, the driver’s output is 180 degrees
out of phase with the PWM input. When the ADP3414 is dis-
abled, the low side gate is held low.
Murata GRM235Y5V106Z16 www.murata.com
Taiyo-
High-Side Driver
The high side driver is designed to drive a floating low RDS(ON)
N-channel MOSFET. The maximum output resistance for the
driver is 3.5 Ω for sourcing and 2.5 Ω for sinking gate cur-
rent. The low output resistance allows the driver to have 30 ns
rise and fall times into a 3 nF load. The bias voltage for the
high side driver is developed by an external bootstrap supply
circuit, which is connected between the BST and SW Pins.
Yuden
EMK325F106ZF
www.t-yuden.com
Tokin
C23Y5V1C106ZP
www.tokin.com
Keep the ceramic capacitor as close as possible to the ADP3414.
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor (CBST) and a
Schottky diode, as shown in Figure 1. Selection of these compo-
nents can be done after the high side MOSFET has been chosen.
The bootstrap circuit comprises a diode, D1, and bootstrap
capacitor, CBST. When the ADP3414 is starting up, the SW Pin
is at ground, so the bootstrap capacitor will charge up to VCC
through D1. When the PWM input goes high, the high side
driver will begin to turn the high side MOSFET, Q1, ON by
pulling charge out of CBST. As Q1 turns ON, the SW Pin will
rise up to VIN, forcing the BST Pin to VIN + VC(BST), which is
enough gate to source voltage to hold Q1 ON. To complete the
cycle, Q1 is switched OFF by pulling the gate down to the volt-
age at the SW Pin. When the low side MOSFET, Q2, turns
ON, the SW Pin is pulled to ground. This allows the bootstrap
capacitor to charge up to VCC again.
The bootstrap capacitor must have a voltage rating that is able
to handle the maximum battery voltage plus 5 V. A minimum 50
V rating is recommended. The capacitance is determined
using the following equation:
QGATE
CBST
=
∆VBST
where, QGATE is the total gate charge of the high side MOSFET,
and ∆VBST is the voltage droop allowed on the high side MOSFET
drive. For example, the IRF7811 has a total gate charge of about
20 nC. For an allowed droop of 200 mV, the required boot-
strap capacitance is 100 nF. A good quality ceramic capacitor
should be used.
The high-side driver’s output is in phase with the PWM input.
When the driver is disabled, the high side gate is held low.
Overlap Protection Circuit
The overlap protection circuit (OPC) prevents both of the main
power switches, Q1 and Q2, from being ON at the same time.
This is done to prevent shoot-through currents from flowing
through both power switches and the associated losses that can
occur during their ON-OFF transitions. The overlap protection
circuit accomplishes this by adaptively controlling the delay from
Q1’s turn OFF to Q2’s turn ON and by internally setting the
delay from Q2’s turn OFF to Q1’s turn ON.
A Schottky diode is recommended for the bootstrap diode due
to its low forward drop, which maximizes the drive available for
the high side MOSFET. The bootstrap diode must have a mini-
mum 40 V rating to withstand the maximum battery voltage
plus 5 V. The average forward current can be estimated by:
IF(AVG) ≈ QGATE × fMAX
where fMAX is the maximum switching frequency of the control-
ler. The peak surge current rating should be checked in-circuit,
since this is dependent on the source impedance of the 5 V
To prevent the overlap of the gate drives during Q1’s turn OFF
and Q2’s turn ON, the overlap circuit monitors the voltage at the
SW Pin. When the PWM input signal goes low, Q1 will begin to
turn OFF (after a propagation delay), but before Q2 can turn ON,
the overlap protection circuit waits for the voltage at the SW Pin
to fall from VIN to 1 V. Once the voltage on the SW Pin has fallen
to 1 V, Q2 will begin turn ON. By waiting for the voltage on the
SW Pin to reach 1 V, the overlap protection circuit ensures that
Q1 is OFF before Q2 turns on, regardless of variations in tem-
perature, supply voltage, gate charge, and drive current.
supply and the ESR of CBST
.
Rev. 3 | Page 6 of 9 | www.onsemi.com
ADP3414
Printed Circuit Board Layout Considerations
Use the following general guidelines when designing printed
circuit boards:
Typical Application Circuits
The circuit in Figure 3 shows how two drivers can be com-
bined with the ADP3160 to form a total power conversion
solution for VCC(CORE) generation in a high current Intel CPU
computer. Figure 4 gives a similar application circuit for a
45 A AMD processor.
1. Trace out the high current paths and use short, wide traces
to make these connections.
2. Connect the PGND pin of the ADP3414 as close as possible
to the source of the lower MOSFET.
3. The VCC bypass capacitor should be located as close as
possible to VCC and PGND Pins.
270F
؋
4 OS–CON 16V
R7
20⍀
V
IN
12V
C12 C13 C14 C15
C23
10F
R4
4m⍀
C24
10F
V
RTN
IN
C26
4.7F
D1
MBR052LTI
C9
1F
R6
10⍀
R5
2.4k⍀
C21
15nF
U2
ADP3414
Q5
2N3904
C4
4.7F
Q1
FDB7030L
1
Z1
ZMM5236BCT
8
7
6
5
BST
DRVH
L1
600nH
2
3
4
IN
SW
PGND
DRVL
NC
VCC
U1
ADP3160
Q2
FDB8030L
C5
1F
C22
1nF
VID4
VID3
VID2
VCC
REF
CS–
1
2
3
4
5
6
7
8
16
15
14
13
12
FROM
CPU
1200F
؋
8 OS–CON 2.5V
11m⍀ ESR (EACH)
V
R
CC (CORE)
1.1V – 1.85V
53.4A
A
34.0k⍀
VID1 PWM1
VID0
PWM2
C
+
+
+
+
+
+
+
+
OC
1.4nF
C10
1F
D2
MBR052LTI
COMP CS+ 11
V
R
Z
1.1k⍀
CC (CORE)
PWRGND
GND
FB
CT
10
9
C11 C16 C17 C18 C19 C20 C27 C28
RTN
U3
ADP3414
R
B
11.5k⍀
C1
150pF
Q3
FDB7030L
1
8
7
6
5
BST
DRVH
SW
L2
600nH
2
3
4
IN
R1
1k⍀
C2
100pF
NC
VCC
PGND
DRVL
Q4
FDB8030L
C6
1F
NC = NO CONNECT
Figure 3. 53.4 A Intel CPU Supply Circuit
Rev. 3 | Page 7 of 9 | www.onsemi.com
ADP3414
1000F
؋
6 RUBYCON ZA SERIES
V
IN
5V
C12 C13 C14 C15 C24 C25
R7
20⍀
V
RTN
IN
R4
5m⍀
12V V
CC
C29
10F
C30
10F
C26
4.7F
D1
MBR052LTI
12V
RTN
R6
10⍀
V
CC
R5
2.4k⍀
C21
15nF
U2
C9
ADP3414 1F
Q5
2N3904
C4
4.7F
Q1
FDB7030L
1
2
3
4
Z1
ZMM5236BCT
8
7
6
5
BST
IN
DRVH
SW
L1
600nH
NC
PGND
DRVL
U1
ADP3160
Q2
FDB7045L
VCC
C5
1F
C22
1nF
VID4
VCC
16
15
1
2
3
4
5
6
7
8
FROM
CPU
VID3
VID2
REF
CS– 14
1000F
؋
8 V
R
CC (CORE)
1.1V – 1.85V
45A
A
6.98k⍀
RUBYCON ZA SERIES
24m⍀ ESR (EACH)
VID1 PWM1 13
VID0
PWM2 12
C
+
+
+
+
+
+
+
+
OC
4.7nF
C10
1F
D2
MBR052LTI
COMP CS+ 11
FB PWRGD 10
V
R
Z
750⍀
CC (CORE)
C11 C16 C17 C18 C19 C20 C27 C28
RTN
U3
ADP3414
GND
CT
9
R
B
14.0k⍀
C1
150pF
Q3
FDB7030L
1
8
7
6
5
BST
DRVH
SW
L2
600nH
2
3
4
IN
R1
1k⍀
C2
100pF
NC
VCC
PGND
DRVL
Q4
FDB7045L
C6
1F
NC = NO CONNECT
Figure 4. 45 A Athlon Duron CPU Supply Circuit
Rev. 3 | Page 8 of 9 | www.onsemi.com
ADP3414
OUTLINE DIMENSIONS
8-Lead Standard Small Outline Package [SOIC]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2440)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
PIN 1
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
؋
45؇ 1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8؇
0؇ 1.27 (0.0500)
0.51 (0.0201)
0.33 (0.0130)
0.25 (0.0098)
0.19 (0.0075)
SEATING
PLANE
0.41 (0.0160)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-012AA
ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no
warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any
and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights
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