Electronic Components Datasheet Search
English 中文版
Manufacturer Upload
Part Name:
 
Description:
MPM3002  IDT54540DTQB  MPS-A55  MPQ2369  MPS-A42  MPQ6002N  LDTS14  IDT74541DTQB  MPQ6501  MPS-A06  
ADT7481ARMZ-1R7 Dual Channel Temperature Sensor and Overtemperature Alarm
Prototype PCB
Part No.:   ADT7481ARMZ-1R7
Download: Download   Right selection Save Target As
View Datasheet (Html)   No need to install PDF reader software
Description:   Dual Channel Temperature Sensor and Overtemperature Alarm
File Size :   253 K    
Page : 20 Pages
Logo:   
Maker   ONSEMI [ ON SEMICONDUCTOR ]http://www.onsemi.com
Buy Now :   
  ADT7481ARMZ-1R7 Datasheet PDF page 9 ADT7481ARMZ-1R7 Datasheet PDF page 10 ADT7481ARMZ-1R7 Datasheet PDF page 11 ADT7481ARMZ-1R7 Datasheet PDF page 12 ADT7481ARMZ-1R7 Datasheet PDF page 14 ADT7481ARMZ-1R7 Datasheet PDF page 15 ADT7481ARMZ-1R7 Datasheet PDF page 16 ADT7481ARMZ-1R7 Datasheet PDF page 17  
100%
ADT7481
Table 11. List of Registers
Read
Address
(Hex)
21
22
23
24
30
31
32
33
34
35
36
37
39
3D
3E
Write
Address
(Hex)
21
22
N/A
24
N/A
31
32
N/A
34
35
36
37
39
N/A
N/A
Mnemonic
THERM Hysteresis
Consecutive ALERT
Status Register 2
Configuration 2 Register
Remote 2 Temperature Value High Byte
Remote 2 Temp High Limit High Byte
Remote 2 Temp Low Limit High Byte
Remote 2 Temperature Value Low Byte
Remote 2 Temperature Offset High Byte
Remote 2 Temperature Offset Low Byte
Remote 2 Temp High Limit Low Byte
Remote 2 Temp Low Limit Low Byte
Remote 2 THERM Limit
Device ID
Manufacturer ID
Power−On Default
0000 1010 (0x0A) (10°C)
0000 0001 (0x01)
0000 0000 (0x00)
0000 0000 (0x00)
0000 0000 (0x00)
0101 0101 (0x55) (85°C)
0000 0000 (0x00) (0°C)
0000 0000 (0x00)
0000 0000 (0x00)
0000 0000 (0x00)
0000 0000 (0x00) (0°C)
0000 0000 (0x00) (0°C)
0101 0101 (0x55) (85°C)
1000 0001 (0x81)
0100 0001 (0x41)
N/A
Comment
Lock
Yes
Yes
No
Yes
No
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
1. Writing to Address 0F causes the ADT7481 to perform a single measurement. It is not a data register as such, and it does not matter
what data is written to it.
Serial Bus Interface
Control of the ADT7481 is achieved via the serial bus.
The ADT7481 is connected to this bus as a slave device
under the control of a master device.
The ADT7481 has an SMBus timeout feature. When this
is enabled, the SMBus will typically timeout after 25 ms of
no activity. However, this feature is not enabled by default.
Set Bit 7 (SCL timeout bit) of the consecutive alert register
(Address 0x22) to enable the SCL timeout. Set Bit 6 (SDA
timeout bit) of the consecutive alert register (Address 0x22)
to enable the SDA timeout.
The ADT7481 supports packet error checking (PEC) and
its use is optional. It is triggered by supplying the extra clock
for the PEC byte. The PEC byte is calculated using CRC−8.
The frame check sequence (FCS) conforms to CRC−8 by the
polynomial:
C(x)
+
x
8
)
x
2
)
x
1
)
1
(eq. 1)
Consult the SMBus 1.1 specification for more
information (www.smbus.org).
Addressing the Device
In general, every SMBus device has a 7−bit device
address, except for some devices that have extended, 10−bit
addresses. When the master device sends a device address
over the bus, the slave device with that address responds.
The ADT7481 is available with one device address, 0x4C
(1001 100b). An ADT7481−1 is also available. The only
difference between the ADT7481 and the ADT7481−1 is the
SMBus address. The ADT7481−1 has a fixed SMBus
address of 0x4B (1001 011b). The addresses mentioned in
this datasheet are 7−bit addresses. The R/W bit needs to be
added to arrive at an 8−bit address. Other than the different
SMBus addresses, the ADT7481 and the ADT7481−1 are
functionally identical.
The serial bus protocol operates as follows:
The master initiates data transfer by establishing a start
condition, defined as a high−to−low transition on the serial
data line (SDATA) while the serial clock line (SCLK)
remains high. This indicates that an address/data stream
follows. All slave peripherals connected to the serial bus
respond to the start condition and shift in the next eight bits,
consisting of a 7−bit address (MSB first) plus a R/W bit,
which determines the direction of the data transfer, that is,
whether data will be written to, or read from, the slave
device. The peripheral with the address corresponding to the
transmitted address responds by pulling the data line low
during the low period before the ninth clock pulse, known as
the acknowledge bit. All other devices on the bus remain idle
while the selected device waits for data to be read from or
written to it. If the R/W bit is 0, the master writes to the slave
device. If the R/W bit is 1, the master reads from the slave
device.
Data is sent over the serial bus in a sequence of nine clock
pulses, eight bits of data followed by an acknowledge bit
from the slave device. Transitions on the data line must
occur during the low period of the clock signal and remain
stable during the high period, since a low−to−high transition
when the clock is high may be interpreted as a stop signal.
The number of data bytes that can be transmitted over the
serial bus in a single read or write operation is limited only
by what the master and slave devices can handle.
When all data bytes have been read or written, stop
conditions are established. In write mode, the master will
pull the data line high during the tenth clock pulse to assert
http://onsemi.com
13
Home - IC Supply - Link
Copyright© 2001 - 2014 ICPDF All Rights Reserved ICPDF.COM

粤公网安备 44030402000629号


粤ICP备13051289号-7