AP0100CS2L00SPGAH-GEVB

‡

AP0100CS HDR: Image Signal Processor (ISP)

Features

AP0100CS High-Dynamic Range (HDR) Image

Signal Processor (ISP)

AP0100CS Datasheet, Rev. 6

For the latest product datasheet, please visit www.onsemi.com

Table 1:

Key Performance Parameters

Value

Features

• Up to 1.2Mp (1280x960) ON Semiconductor sensor

support

• 45 fps at 1.2Mp, 60 fps at 720p

• Optimized for operation with HDR sensors.

• Color and gamma correction

• Auto exposure, auto white balance, 50/60 Hz auto

flicker detection and avoidance

• Adaptive Local Tone Mapping (ALTM)

• Programmable Spatial Transform Engine (STE).

• Pre-rendered Graphical Overlay

• Two-wire serial programming interface (CCIS)

• Interface to low-cost Flash or EEPROM through SPI

bus (to configure and load patches, etc.)

• High-level host command interface

• Standalone operation supported

• Up to 5 GPIO

Parameter

Primary camera

interfaces

Parallel and HiSPi

RAW12 Linear/RAW12, RAW14 (HiSPi

format only) Companded

Primary camera input

Output interface

Output format

Analog composite, up to 16-bit

parallel digital output

YUV422 8-bit,10-bit, and 10-, 12-bit

tone-mapped Bayer

Maximum resolution 1280x960 (1.2 Mp)

NTSC output

PAL output

720H x 487V

720H x 576V

6-30 MHz

VDDIO_S

VDDIO_H

VDD_REG

VDD

Input clock range

1.8 or 2.8 V nominal

2.5 or 3.3 V nominal

1.8 V nominal

• Fail-safe IO

• Multi-Camera synchronization support

• Integrated video encoder for NTSC/PAL with overlay

capability and 10-bit I-DAC

1.2 V nominal

Supply voltage

VDD_PLL

1.2 V nominal

VDD_DAC

1.2V nominal

VDDIO_OTPM 2.5 or 3.3 V nominal

Applications

• IP cam and CCTV - HD

• Enables CCTV -HD w/ MP sensor

VDDA_DAC

VDD_PHY

3.3 V nominal

2.8 V nominal

Operating temp.

–30°C to +70°C

185 mW

Power consumption

Notes: 1.

AP0100CS/D Rev. 6, 1/16 EN

1

©Semiconductor Components Industries, LLC 2016,

AP0100CS HDR: Image Signal Processor (ISP)

Ordering Information

Table 2:

Available Part Numbers

Part Number

Product Description

Orderable Product Attribute Description

AP0100CS2L00SUGA0-DR1

AP0100CS2L00SPGAD3-GEVK

AP0100CS2L00SPGAH-GEVB

1Mp Co-Processor, 100-ball VFBGA

AP0100CS Demo Kit

Drypack

AP0100CS Head Board

See the ON Semiconductor Device Nomenclature document (TND310/D) for a full

description of the naming convention used for image sensors. For reference documenta-

tion, including information on evaluation kits, please visit our web site at

www.onsemi.com.

AP0100CS/D Rev. 6, 1/16 EN

2

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

Table of Contents

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Functional Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

System Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

On-Chip Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Multi-Camera Synchronization Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Image Flow Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Test Patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Camera Control and Auto Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Flicker Avoidance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Flicker Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Output Formatting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Bayer Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Spatial Transform Engine (STE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Overlay Capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Serial Memory Partition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Overlay Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Slave Two-Wire Serial Interface (CCIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Host Command Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Start-up Host Command Lock-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Multitasking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Host Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Summary of Host Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Usage Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Two-Wire Serial Register Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Package Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

AP0100CS/D Rev. 6, Pub. 1/16 EN

3

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

General Description

Functional Overview

The ON Semiconductor AP0100CS is a high-performance, ultra-low power in-line,

digital image processor optimized for use with HDR (High Dynamic Range) sensors. The

AP0100CS provides full auto-functions support (AWB and AE) and ALTM (Adaptive Local

Tone Mapping) to enhance HDR images and advanced noise reduction which enables

excellent low-light performance.

Figure 1 shows the typical configuration of the AP0100CS in a camera system. On the

host side, a two-wire serial interface is used to control the operation of the AP0100CS,

and image data is transferred using the analog or parallel interface between the

AP0100CS and the host. The AP0100CS interface to the sensor also uses a parallel inter-

face.

Figure 1:

AP0100CS Connectivity

1.2Mp HDR Sensor

12-bit parallel

or

Two-lane HiSPi

NTSC/PAL display

Analog

Two-wire serial I/F (CCIM)

Two-wire serial IF (CCIS)

Host

System Interfaces

Figure 2: “Typical Parallel Configuration,” on page 5 and Figure 3: “Typical HiSPi Config-

uration,” on page 6 show typical AP0100CS device connections.

All power supply rails must be decoupled from ground using capacitors as close as

possible to the package.

The AP0100CS signals to the sensor and host interfaces can be at different supply voltage

levels to optimize power consumption and maximize flexibility. Table 1 on page 9

provides the signal descriptions for the AP0100CS.

AP0100CS/D Rev. 6, Pub. 1/16 EN

4

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

System Interfaces

Figure 2:

Typical Parallel Configuration

1. 2V (Regulator OP)

Power up Core, PLL.

and DAC digital

DAC

analog

power

1. 8V

(Regulator

Sensor IO

power

Host IO

power

OTPM

power

IP)

VDDIO _S

VDDIO _H

SCLK

SDATA

SADDR

M_SCLK

M_S DATA

EXTCLK

EXTCLK_OUT

XTAL

RESET_BAR_OUT

SPI_CS_BAR

FV_IN

LV_IN

PIXCLK _IN

SPI_CLK

SPI_SDO

SPI_SDI

[11:0]

DIN

FV_OUT

LV_OUT

TRIGGER_OUT

PIXCLK_OUT

DOUT[15:0]

DAC_POS

DAC_NEG

DAC_REF

FRAME_SYNC

GPIO_1

GPIO_2

GPIO_3

GPIO_4

GPIO_5

5

TRST_BAR

G ND_REG

G ND

4

6

4

VDD_REG

VDDIO_S

LDO_OP

VDDIO_OTPM VDDIO_H

VDDIO_DAC

Notes: 1. This typical configuration shows only one scenario out of multiple possible variations for this

device.

2. ON Semiconductor recommends a 1.5kresistor value for the two-wire serial interface RPULL-UP;

however, greater values may be used for slower transmission speed.

3. RESET_BAR has an internal pull-up resistor and can be left floating if not used.

4. The decoupling capacitors for the regulator input and output should have a value of 1.0uF. The

capacitors should be ceramic and need to have X5R or X7R dielectric.

5. TRST_BAR connects to GND for normal operation.

6. ON Semiconductor recommends that 0.1F and 1F decoupling capacitors for each power supply

are mounted as close as possible to the pin. Actual values and numbers may vary depending on lay-

out and design consideration

AP0100CS/D Rev. 6, Pub. 1/16 EN

5

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

System Interfaces

Figure 3:

Typical HiSPi Configuration

1. 2V (Regulator OP)

Power up Core, PLL.

and DAC digital

DAC

analog voltage

power

HiSPi

1. 8V

(Regulator

Sensor IO

power

Host IO

power

OTPM

power

IP)

V

DDIO _S

V

DDIO _H

S

DATA

CLK

M_SCLK

S

ADDR

M_S DATA

EXTCLK

EXTCLK_OUT

XTAL

RESET_BAR_OUT

Sensor IO

power

SPI_CS_BAR

FV_IN

LV_IN

PIXCLK _IN

SPI_CLK

SPI_SDO

SPI_SDI

[11:0]

DIN

FV_OUT

LV_OUT

TRIGGER_OUT

PIXCLK_OUT

D

OUT[15:0]

CLK_N CLK_P

DATA0_N DATA0_P

DATA1_N DATA1_P

DAC_POS

DAC_NEG

DAC_REF

FRAME_SYNC

GPIO_1

GPIO_2

GPIO_3

GPIO_4

GPIO_5

TRST_BAR⁵

G ND_REG

G ND

4

6

4

VDD_REG

V

DDIO_S

LDO_OP

V

DDIO_OTPM

VDDIO_H

VDDIO_DAC

VDDIO_PHY

HiSPi and Parallel Connection

When using the HiSPi interface, the user should connect the parallel interface to

VDDIO_S.

When using the parallel interface, the HiSPi interface and power supply (VDD_PHY) can

be left floating.

AP0100CS/D Rev. 6, Pub. 1/16 EN

6

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

System Interfaces

Crystal Usage

As an alternative to using an external oscillator, a crystal may be connected between

EXTCLK and XTAL. Two small loading capacitors and a feedback resistor should be

added, as shown in Figure 4.

Figure 4:

Using a Crystal Instead of an External Oscillator

AP0100CS

C1

EXTCLK

Rf=1MΩ

XTAL

C2

Rf represents the feedback resistor, an Rf value of 1M is sufficient for AP0100CS. C1 and

C2 are decided according to the crystal or resonator CL specification. In the steady state

of oscillation, CL is defined as (C1 x C2)/(C1+C2). In fact, the I/O ports, the bond pad,

package pin and PCB traces all contribute the parasitic capacitance to C1 and C2. There-

fore, CL can be rewritten to be (C1* x C2*)/(C1*+C2*), where C1*=(C1+Cin, stray) and

C2*=(C2+Cout, stray). The stray capacitance for the IO ports, bond pad and package pin

are known which means the formulas can be rewritten as C1*=(C1+1.5pF+Cin, PCB) and

C2*=(C2+1.3pF+Cout, PCB).

Table 3:

Pin Descriptions

Name

Type

Description

EXTCLK

Input

Master input clock. This can either be a square-wave generated from an

oscillator (in which case the XTAL input must be left unconnected) or direct

connection to a crystal.

XTAL

Output

If EXTCLK is connected to one pin of a crystal, the other pin of the crystal is

connected to XTAL pin; otherwise this signal must be left unconnected.

RESET_BAR

SCLK

Input/PU

Input

I/O

Master reset signal, active LOW. This signal has an internal pull up.

Two-wire serial interface clock (host interface).

SDATA

Two-wire serial interface data (host interface).

SADDR

Input

Selects device address for the two-wire slave serial interface. When connected

to GND the device ID is 0x90. When wired to VDDIO_H, a device ID of 0xBA is

selected.

FRAME_SYNC

Input

This signal is used to synchronize to external sources or multiple cameras

together. This signal should be connected to GND if not used.

STANDBY

EXT_REG

Input

Standby mode control, active HIGH.

Select external regulator if tied high

AP0100CS/D Rev. 6, Pub. 1/16 EN

7

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

System Interfaces

Table 3:

Pin Descriptions (Continued)

Name

Type

Input

Description

ENDLO

SPI_SCLK

SPI_SDI

Regulator enable (VDD_REG domain)

Output

Input/PU

Clock output for interfacing to an external SPI flash or EEPROM memory.

Data in from SPI flash or EEPROM memory. When no SPI device is fitted, this

signal is used to determine whether the AP0100CS should auto-configure: 0:

Do not auto-configure; Two-wire interface will be used to configure the

device (host-config mode) 1: Auto-configure. This signal has an internal pull-

up resistor.

SPI_SDO

Output

I/O

Data out to SPI flash or EEPROM memory.

Chip select out to SPI flash or EEPROM memory.

Clock to external sensor.

SPI_CS_BAR

EXT_CLK_OUT

RESET_BAR_OUT

M_SCLK

Reset signal to external signal.

Two-wire serial interface clock (Master).

Sensor frame valid input.

M_SDATA

FV_IN

Input

LV_IN

Input

Sensor line valid input.

PIXCLK_IN

DIN[11:0]

CLK_N

Input

Sensor pixel clock input.

Input

Sensor pixel data input DIN[11:0]

Input

Differential HiSPi clock (sub-LVDS, negative).

Differential HiSPi clock (sub-LVDS, positive).

Differential HiSPi data, lane 0 (sub-LVDS, negative).

Differential HiSPi data, lane 0 (sub-LVDS, positive).

Differential HiSPi data, lane 1 (sub-LVDS, negative).

Differential HiSPi data, lane 1 (sub-LVDS, positive).

Trigger signal for external sensor.

CLK_P

Input

DATA0_N

DATA0_P

DATA1_N

DATA1_P

TRIGGER_OUT

FV_OUT

Input

Output

Host frame valid output (synchronous to PIXCLK_OUT)

Host line valid output (synchronous to PIXCLK_OUT)

Host pixel clock output.

LV_OUT

PIXCLK_OUT

DOUT[15:0]

DAC_POS

Host pixel data output (synchronous to PIXCLK_OUT) DOUT[15:0].

Positive video DAC output in differential mode. Video DAC output in single-

ended mode. This interface is enabled by default using NTSC/PAL signaling.

For applications where composite video output is not required, the video DAC

can be placed in a power-down state under software control.

DAC_NEG

DAC_REF

GPIO [5:1]

TRST_BAR

VDDIO_S

Output

I/O

Negative video DAC output in differential mode.

External reference resistor for Video DAC.

General purpose digital I/O.

Must be tied to GND in normal operation.

Sensor I/O power supply.

Host I/O power supply.

Input

Supply

VDDIO_H

VDD_PLL

PLL supply.

VDD

Core supply.

VDDIO_OTPM

VDD_DAC

VDDA_DAC

VDD_PHY

OTPM power supply.

Video DAC digital power

Video DAC analog power

PHY IO voltage for HiSPi

AP0100CS/D Rev. 6, Pub. 1/16 EN

8

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

System Interfaces

Table 3:

Pin Descriptions (Continued)

Name

Type

Description

GND

Supply

Output

Ground

VDD_REG

LDO_OP

FB_SENSE

Input to on-chip 1.8V to 1.2V regulator.

Output from on chip 1.8V to 1.2V regulator.

On-chip regulator sense signal.

AP0100CS/D Rev. 6, Pub. 1/16 EN

9

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

On-Chip Regulator

The AP0100CS has an on-chip regulator, the output from the regulator is 1.2 V and

should only be used to power up the AP0100CS. It is possible to bypass the regulator and

provide power to the relevant pins that need 1.2 V. Figure 5 shows how to configure the

AP0100CS to bypass the internal regulator.

Figure 5:

External Regulator

DAC

PHY

analog

External supplied

1.2V

power

Sensor IO

power

Host IO

power

OTPM

Host IO

power

Host IO

power

VDDIO _S

VDDIO _H

SCLK

M_SCLK

SDATA

SADDR

M_S DATA

STANDBY

EXTCLK

EXTCLK_OUT

XTAL

RESET_BAR_OUT

SPI_CS_BAR

FV_IN

LV_IN

PIXCLK _IN

SPI_CLK

SPI_SDO

SPI_SDI

[11:0]

DIN

FV_OUT

LV_OUT

TRIGGER_OUT

PIXCLK_OUT

DOUT[15:0]

CLK_N CLK_P

DATA0_N DATA0_P

DATA1_N DATA1_P

DAC_POS

DAC_NEG

DAC_REF

FRAME_SYNC

GPIO_1

GPIO_2

GPIO_3

GPIO_4

GPIO_5

TRST_BAR

G ND

The following table summarizes the key signals when using/bypassing the regulator.

Key Signals When Using the Regulator

Table 5:

Signal Name

VDD_REG

ENLDO

Internal Regulator

1.8 V

External Regulator

Connect to VDDIO_H

GND

Connect to 1.8 V (VDD_REG)

1.2 V (output)

GND

FB_SENSE

LDO_OP

Float

EXT_REG

Connect to VDDIO_H

AP0100CS/D Rev. 6, Pub. 1/16 EN

11

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

On-Chip Regulator

Power-Up Sequence

Powering up the ISP requires voltages to be applied in a particular order, as seen in

Figure 6. The timing requirements are shown in Table 6. The ISP includes a power-on

reset feature that initiates a reset upon power up of the ISP.

Figure 6:

Power-Up and Power-Down Sequence

dv/dt

V

DDIO_H

dv/dt

t7

t1

V

DDIO_S, VDDIO_OTPM, VDDA_DAC,

DD_PHY (when using HiSPi)

dv/dt

t6

t2

V

DD_REG

t3

t5

EXTCLK

S

CLK

t4

S

DATA

Table 6:

Power-Up and Power-Down Signal Timing

Symbol Parameter

Min

Typ

Max

Unit

t1

Delay from VDDIO_H to VDDIO_S, VDDIO_OTPM, VDDA_DAC, VDD_PHY

0

–

50

ms

(When using HiSPi)

t2

t3

t4

t5

t6

t7

Delay from VDDIO_H to VDD_REG

0

t2 + 1

100

t6

–

50

–

ms

EXTCLK activation

First serial command¹

EXTCLK cutoff

–

EXTCLK cycles

–

ms

Delay from VDD_REG to VDDIO_H

0

50

Delay from VDDIO_S, VDDIO_OTPM, VDDA_DAC, VDD_PHY (When using

HiSPi) to VDDIO_H

0

dv/dt Power supply ramp time (slew rate)

–

0.1

V/s

Note:

1. When using XTAL the settling time should be taken into account.

Reset

The AP0100CS has three types of reset available:

•

A hard reset is issued by toggling the RESET_BAR signal

A soft reset is issued by writing commands through the two-wire serial interface

An internal power-on reset

Table 7 on page 13 shows the output states when the part is in various states.

AP0100CS/D Rev. 6, Pub. 1/16 EN

12

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

On-Chip Regulator

Hard Reset

Figure 7:

The AP0100CS enters the reset state when the external RESET_BAR signal is asserted

LOW, as shown in Figure 7. All the output signals will be in High-Z state.

Hard Reset Operation

t₁

t₄

t₃

t₂

EXTCLK

RESET_BAR

SDATA

Data Active

All Outputs

Mode

Enter streaming mode

Reset

Internal Initialization Time

Table 8:

Hard Reset

Symbol

Definition

RESET_BAR pulse width

Min

Typ

–

Max

Unit

t₁

t₂

t₃

50

–

EXTCLK

cycles

Active EXTCLK required after RESET_BAR asserted

10

–

Active EXTCLK required before RESET_BAR de-

asserted

–

t₄

First two-wire serial interface communication after

RESET is HIGH

100

–

Soft Reset

A soft reset sequence to the AP0100 CS can be activated by writing to a register through

the two-wire serial interface.

Hard Standby Mode

The AP0100CS can enter hard standby mode by using external STANDBY signal, as

shown in Figure 8.

Entering Standby Mode

1. Assert STANDBY signal HIGH.

AP0100CS/D Rev. 6, Pub. 1/16 EN

15

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

On-Chip Regulator

Exiting Standby Mode

1. De-assert STANDBY signal LOW.

Figure 8:

Hard Standby Operation

t₁

t₂

t₃

EXTCLK

STANDBY

Mode

STANDBY

Asserted

STANDBY

Mode

EXTCLK Disabled

EXTCLK Enabled

Table 9:

Hard Standby Signal Timing

Symbol Parameter

Min

Typ

–

Max

2 Frames

–

Unit

Lines

^t1

^t2

Standby entry complete

Active EXTCLK required after going into STANDBY

–

10

–

EXTCLKs

mode

^t3

Active EXTCLK required before STANDBY

de-asserted

10

–

EXTCLKs

AP0100CS/D Rev. 6, Pub. 1/16 EN

16

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

Multi-Camera Synchronization Support

The AP0100CS supports multi-camera synchronization through the FRAME_SYNC pin.

The behavior will be different depending if the user is using interlaced or progressive

mode.

When using the interlaced modes, on the rising edge of FRAME_SYNC this will cause the

output to stop the current frame (A) and during B the image output will be indetermi-

nate. On the falling edge of FRAME_SYNC this will cause the re-synchronization to

begin, this will continue for a period (C), during C black fields will be output. The re-

synchronized interlaced signal will be available at D. During C if the user toggles the

FRAME_SYNC input the AP0100CS will ignore it, the user cannot re-synchronize again

until at D.

Figure 9:

Frame Sync Behavior with Interlaced Mode

FRAME_SYNC

CVBS output

(NTSC/PAL)

B

A

C

D

When using progressive mode, the host (or controlling entity) ‘broadcasts’ a sync-pulse

to all cameras within the system that triggers capture. The AP0100AT will propagate the

signal to the TRIGGER_OUT pin, and subsequently to the attached sensor's TRIGGER

pin.

The AP0100CS supports two different trigger modes when using progressive output. The

first mode supported is ‘single-shot’; this is when the trigger pulse will cause one frame

to be output from the image sensor and AP0100CS (see Figure 10).

Figure 10: Single-Shot Mode

FRAME_SYNC

TRIGGER_OUT

FV_OUT

Note:

This diagram is not to scale.

The second mode supported is called 'continuous', this is when a trigger pulse will cause

the part to continuously output frames, see Figure 11. This mode would be especially

useful for applications which have multiple sensors and need to have their video

streams synchronized (for example, surround view or panoramic view applications).

AP0100CS/D Rev. 6, Pub. 1/16 EN

17

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

Multi-Camera Synchronization Support

Figure 11: Continuous Mode

FRAME_SYNC

TRIGGER_OUT

FV_OUT

Note:

This diagram is not to scale.

When two or more cameras have a signal applied to the FRAME_SYNC input at the same

time, the respective FV_OUT signals would be synchronized within 5 PIXCLK_OUT

cycles. This assumes that all cameras have the same configuration settings and that the

exposure time is the same.

AP0100CS/D Rev. 6, Pub. 1/16 EN

18

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

Image Flow Processor

Image and color processing in the AP0100CS is implemented as an image flow processor

(IFP) coded in hardware logic. During normal operation, the embedded microcontroller

will automatically adjust the operating parameters. For normal operation of the

AP0100CS, streams of raw image data from the attached image sensor are fed into the

color pipeline. The user also has the option to select a number of test patterns to be

input instead of sensor data. The IFP is broken down into different sections, as outlined

in Figure 12.

Figure 12: AP0100CS IFP

R A W 12- or 20-bit B ayer

12-bit A LTM B ayer

AE, FD and ALTM

stats

linear or

com panded data

Black level

subtractio,n

D igital gain

contro,l

P rogressive

(Y C bC r or

B ayer)

D efect correctio,n

N oise reduction

YU V

filters

R X

C olor

Interpolation

C olor

C orrection

Aperture

C orrection

Scaler

C rop

Gam m a

C olor Kill

ALTM

R GB 2YU V

decom panding

PGA

AW B stats

Progressive

T est pattern

generator

C C IR656

(Y C bC r)

PAL /N TSC

Encode D AC

N TS C/P A L

(Y C bC r)

STE

Interlacer

Overlay

R A W B ayer

A LTM B ayer

R GB

PAL /N TSC

Test patterns

Y C bC r

AP0100CS/D Rev. 6, Pub. 1/16 EN

19

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

Test Patterns

The AP0100CS has a number of test patterns that are available when using the progres-

sive, NTSC and PAL modes. The test patterns can be selected by programming variables.

To enter test pattern mode, set R0xC88F to 0x02 and issue a Change-Config request; to

exit this mode, set R0xC88F to 0x00, and issue a Change-Config request.

NTSC and PAL test patterns can only be selected when the device is configured for inter-

laced operation.

Progressive Test Patterns

Figure 13: Progressive Test Patterns

Example

Test Pattern

FLAT FIELD

REG= 0xC88C, 0x02

REG= 0xC88F, 0x01

REG= 0xC890, 0x000FFFFF

REG= 0xC894, 0x000FFFFF

REG= 0xC898, 0x000FFFFF

Load = Change-Config

// CAM_MODE_SELECT

// CAM_MODE_TEST_PATTERN_SELECT

// CAM_MODE_TEST_PATTERN_RED

// CAM_MODE_TEST_PATTERN_GREEN

// CAM_MODE_TEST_PATTERN_BLUE

Changing the values in R0xC890-R0x898 will change the color of the

test pattern (will require a Refresh operation).

100% Color Bar

REG= 0xC88C, 0x02

REG= 0xC88F, 0x02

Load = Change-Config

// CAM_MODE_SELECT

// CAM_MODE_TEST_PATTERN_SELECT

Pseudo-Random

REG= 0xC88C, 0x02

REG= 0xC88F, 0x05

Load = Change-Config

// CAM_MODE_SELECT

// CAM_MODE_TEST_PATTERN_SELECT

Fade-to-Gray

REG= 0xC88C, 0x02

REG= 0xC88F, 0x08

Load = Change-Config

// CAM_MODE_SELECT

// CAM_MODE_TEST_PATTERN_SELECT

Linear Ramp

REG= 0xC88C, 0x02

REG= 0xC88F, 0x09

Load = Change-Config

// CAM_MODE_SELECT

// CAM_MODE_TEST_PATTERN_SELECT

AP0100CS/D Rev. 6, Pub. 1/16 EN

20

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

Test Patterns

NTSC Test Patterns

Figure 14: NTSC Test Patterns

Example

Test Pattern

EIA Full Field 7 Color Bars

REG= 0xC88C, 0x02

REG= 0xC88F, 0x14

// CAM_MODE_SELECT

// CAM_MODE_TEST_PATTTERN_SELECT

Load = Change-Config

EIA Full Field 8 Color Bars

REG= 0xC88C, 0x02

REG= 0xC88F, 0x15

// CAM_MODE_SELECT

// CAM_MODE_TEST_PATTERN_SELECT

Load = Change-Config

SMPTE EG 1-1990

REG= 0xC88C, 0x02

REG= 0xC88F, 0x16

Load = Change-Config

// CAM_MODE_SELECT

// CAM_MODE_TEST_PATTERN_SELECT

EIA Full Field 8 Color Bars 100 IRE

REG= 0xC88C, 0x02

REG= 0xC88F, 0x17

Load = Change-Config

// CAM_MODE_SELECT

// CAM_MODE_TEST_PATTERN_SELECT

AP0100CS/D Rev. 6, Pub. 1/16 EN

21

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

Test Patterns

PAL Test Patterns

Figure 15: PAL Test Patterns

Example

Test Pattern

EBU Full Field 7 Color Bars

REG= 0xC88C, 0x02

// CAM_MODE_SELECT

REG= 0xC88F, 0x1E

// CAM_MODE_TEST_PATTERN_SELECT

Load = Change-Config

EBU Full Field 8 Color Bars

REG= 0xC88C, 0x02

// CAM_MODE_SELECT

REG= 0xC88F, 0x1F

// CAM_MODE_TEST_PATTERN_SELECT

Load = Change-Config

Each NTSC/PAL test pattern consists of seven or eight color bars (white, yellow, cyan,

green, magenta, red, blue and optionally black). The Y, Cb and Cr values for each bar are

detailed in Table 10.

For the NTSC SMPTE test pattern it is also required to generate -I, +Q, -4 black and +4

black.

Table 10:

NTSC/PAL Test Pattern Values

Nominal

Range

White White

Magent

a

-4

+4

100%

75% Yellow Cyan Green

Red

Blue

Black

-I

-Q

black black

Y

16 to 235

16 to 240

235

128

180

128

162

44

131

156

44

112

72

84

65

35

16

156

97

16

7

25

Cb

Cr

184

198

100

212

114

128

171

148

128

142

58

AP0100CS/D Rev. 6, Pub. 1/16 EN

22

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

Test Patterns

Figure 16: Test Pattern

Defect Correction

Image stream processing commences with the defect correction function immediately

after data decompanding.

To obtain defect free images, the pixels marked defective during sensor readout and the

pixels determined defective by the defect correction algorithms are replaced with values

derived from the non-defective neighboring pixels. This image processing technique is

called defect correction.

AdaCD (Adaptive Color Difference)

Automotive applications require good performance in extremely low light, even at high

temperature conditions. In these stringent conditions the image sensor is prone to

higher noise levels, and so efficient noise reduction techniques are required to circum-

vent this sensor limitation and deliver a high quality image to the user.

The AdaCD Noise Reduction Filter is able to adapt its noise filtering process to local

image structure and noise level, removing most objectionable color noise while

preserving edge details.

Black Level Subtraction and Digital Gain

After noise reduction, the pixel data goes through black level subtraction and multiplica-

tion of all pixel values by a programmable digital gain. Independent color channel digital

gain can be adjusted with registers. Black level subtraction (to compensate for sensor

data pedestal) is a single value applied to all color channels. If the black level subtraction

produces a negative result for a particular pixel, the value of this pixel is set to 0.

AP0100CS/D Rev. 6, Pub. 1/16 EN

23

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

Test Patterns

Positional Gain Adjustments (PGA)

Lenses tend to produce images whose brightness is significantly attenuated near the

edges. There are also other factors causing fixed pattern signal gradients in images

captured by image sensors. The cumulative result of all these factors is known as image

shading. The AP0100CS has an embedded shading correction module that can be

programmed to counter the shading effects on each individual R, Gb, Gr, and B color

signal.

The Correction Function

The correction functions can then be applied to each pixel value to equalize the

response across the image as follows:

P_correctedrow, col = P_sensorrow, col  f(row, col)

(EQ 1)

where P are the pixel values and f is the color dependent correction functions for each

color channel.

AP0100CS/D Rev. 6, Pub. 1/16 EN

24

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

Test Patterns

Adaptive Local Tone Mapping (ALTM)

Real world scenes often have very high dynamic range (HDR) that far exceeds the elec-

trical dynamic range of the imager. Dynamic range is defined as the luminance ratio

between the brightest and the darkest object in a scene. In recent years many technolo-

gies have been developed to capture the full dynamic range of real world scenes. For

example, the multiple exposure method is widely adopted for capturing high dynamic

range images, which combines a series of low dynamic range images of the same scene

taken under different exposure times into a single HDR image.

Even though the new digital imaging technology enables the capture of the full dynamic

range, low dynamic range display devices are the limiting factor. Today’s typical LCD

monitor has contrast ratio around 1,000:1; however, it is not typical for an HDR image

(the contrast ratio for an HDR image is around 250,000:1). Therefore, in order to repro-

duce HDR images on a low dynamic range display device, the captured high dynamic

range must be compressed to the available range of the display device. This is commonly

called tone mapping.

Tone mapping methods can be classified into global tone mapping and local tone

mapping. Global tone mapping methods apply the same mapping function to all pixels.

While global tone mapping methods provide computationally simple and easy to use

solutions, they often cause loss of contrast and detail. A local tone mapping is thus

necessary in addition to global tone mapping for the reproduction of visually more

appealing images that also reveal scene details that are important for automotive safety

and surveillance applications. Local tone mapping methods use a spatially variable

mapping function determined by the neighborhood of a pixel, which allows it to

increase the local contrast and the visibility of some details of the image. Local methods

usually yield more pleasing results because they exploit the fact that human vision is

more sensitive to local contrast.

ON Semiconductor’s ALTM solution significantly improves the performance over global

tone mapping. ALTM is directly applied to the Bayer domain to compress the dynamic

range from 20-bit to 12-bit. This allows the regular color pipeline to be used for HDR

image rendering.

Color Interpolation

In the raw data stream fed by the external sensor to the IFP, each pixel is represented by a

20- or 12-bit integer number, which can be considered proportional to the pixel's

response to a one-color light stimulus, red, green, or blue, depending on the pixel's posi-

tion under the color filter array. Initial data processing steps, up to and including ALTM,

preserve the one-color-per-pixel nature of the data stream, but after ALTM it must be

converted to a three-colors-per-pixel stream appropriate for standard color processing.

The conversion is done by an edge-sensitive color interpolation module. The module

pads the incomplete color information available for each pixel with information

extracted from an appropriate set of neighboring pixels. The algorithm used to select

this set and extract the information seeks the best compromise between preserving

edges and filtering out high frequency noise in flat field areas. The edge threshold can be

set through register settings.

AP0100CS/D Rev. 6, Pub. 1/16 EN

25

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

Test Patterns

Color Correction and Aperture Correction

To achieve good color fidelity of the IFP output, interpolated RGB values of all pixels are

subjected to color correction. The IFP multiplies each vector of three pixel colors by a 3 x

3 color correction matrix. The three components of the resulting color vector are all

sums of three 10-bit numbers. The color correction matrix can be either programmed by

the user or automatically selected by the auto white balance (AWB) algorithm imple-

mented in the IFP. Color correction should ideally produce output colors that are

corrected for the spectral sensitivity and color crosstalk characteristics of the image

sensor. The optimal values of the color correction matrix elements depend on those

sensor characteristics and on the spectrum of light incident on the sensor. The color

correction variables can be adjusted through register settings.

Traditionally this would have been derived from two sets of CCM, one for Warm light like

Tungsten and the other for Daylight (the part would interpolate between the two

matrices). This is not an optimal solution for cameras used in a Cool White Fluorescent

(CWF) environment. A better solution is to provide three CCMs, which would include a

matrix for CWF (interpolation now between three matrices). The AP0100CS offers this

feature which will give the user improved color fidelity when under CWF type lighting.

To increase image sharpness, a programmable 2D aperture correction (sharpening filter)

is applied to color-corrected image data. The gain and threshold for 2D correction can

be defined through register settings.

Gamma Correction

The gamma correction curve is implemented as a piecewise linear function with 33 knee

points, taking 12-bit arguments and mapping them to 10-bit output. The abscissas of the

knee points are fixed at 0, 8, 16, 24, 32, 40, 48, 56, 64, 80, 96, 112, 128, 160, 192, 224, 256,

320, 384, 448, 512, 640, 768, 896, 1024, 1280, 1536, 1792, 2048, 2560, 3072, 3584, and 4096.

The 10-bit ordinates are programmable through variables.

The AP0100CS has the ability to calculate the 33-point knee points based on the tuning

of cam_ll_gamma and cam_ll_contrast_gradient_bright. The other method is for the

host to program the 33 knee point curve themselves.

Also included in this block is a Fade-to Black curve which sets all knee points to zero and

causes the image to go black in extreme low light conditions.

Color Kill

To remove high-or low-light color artifacts, a color kill circuit is included. It affects only

pixels whose luminance exceeds a certain preprogrammed threshold. The U and V

values of those pixels are attenuated proportionally to the difference between their lumi-

nance and the threshold.

YUV Color Filter

As an optional processing step, noise suppression by one-dimensional low-pass filtering

of Y and/or UV signals is possible. A 3- or 5-tap filter can be selected for each signal.

AP0100CS/D Rev. 6, Pub. 1/16 EN

26

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

Camera Control and Auto Functions

Auto Exposure

The auto exposure algorithm optimizes scene exposure to minimize clipping and satu-

ration in critical areas of the image. This is achieved by controlling exposure time and

analog gains of the external sensor as well as digital gains applied to the image.

Auto exposure is implemented by a firmware algorithm that is running on the

embedded microcontroller that analyzes image statistics collected by the exposure

measurement engine, makes a decision, and programs the sensor and color pipeline to

achieve the desired exposure. The measurement engine subdivides the image into 25

windows organized as a 5 x 5 grid.

Figure 17: 5 x 5 Grid

AE Track Driver

Other algorithm features include the rejection of fast fluctuations in illumination (time

averaging), control of speed of response, and control of the sensitivity to small changes.

While the default settings are adequate in most situations, the user can program target

brightness, measurement window, and other parameters described above.

The driver changes AE parameters (integration time, gains, and so on) to drive scene

brightness to the programmable target.

To avoid unwanted reaction of AE on small fluctuations of scene brightness or momen-

tary scene changes, the AE track driver uses a temporal filter for luma and a threshold

around the AE luma target. The driver changes AE parameters only if the filtered luma is

larger than the AE target step and pushes the luma beyond the threshold.

AP0100CS/D Rev. 6, Pub. 1/16 EN

27

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

Camera Control and Auto Functions

Auto White Balance

The AP0100CS has a built-in AWB algorithm designed to compensate for the effects of

changing spectra of the scene illumination on the quality of the color rendition. The

algorithm consists of two major parts: a measurement engine performing statistical

analysis of the image and a driver performing the selection of the optimal color correc-

tion matrix and IFP digital gain. While default settings of these algorithms are adequate

in most situations, the user can reprogram base color correction matrices, place limits

on color channel gains, and control the speed of both matrix and gain adjustments. The

AP0100 CSAWB displays the current AWB position in color temperature, the range of

which will be defined when programming the CCM matrixes.

The region of interest can be controlled through the combination of an inclusion

window and an exclusion window.

Exposure and White Balance Control

The Sensor Manager firmware component is responsible for controlling the application

of 'exposure' and 'white balance' within the system. This effectively means that all

control of integration times and gains (whether for exposure or white balance) is dele-

gated to the Sensor Manager. The Auto Exposure (AE) and Auto White Balance (AWB)

algorithms use services provided by the Sensor Manager to apply exposure and/or white

balance changes.

Dual Band IRCF

For some applications a day/night filter would be switched in/out, this option is an

additional cost to the camera system. The AP0100CS supports the use of dual band IRCF,

which removes the need for the switching day/night filter. Tuning support is provided

for this usage case. Refer to the AP0100CS developer guide for details.

Exposure and White Balance Modes

The AP0100CS supports auto and manual exposure and white balance modes. In addi-

tion, it will operate within synchronized multi-camera systems. In this use case, one

camera within the system will be the 'master', and the others 'slaves'. The master is used

to calculate the appropriate exposure and white balance. This is then applied to all

slaves concurrently under host control.

Auto Mode

In Auto Exposure mode the AE algorithm is responsible for calculating the appropriate

exposure to keep the desired scene brightness, and for applying the exposure to the

underlying hardware. In Auto White Balance mode the AWB algorithm is responsible for

calculating the color temperature of the scene and applying the appropriate red and

blue gains to compensate.

Triggered Auto Mode

The Triggered Auto Exposure and Triggered Auto White Balance modes are intended for

the multi-camera use cases, where a host is controlling the exposure and white balance

of a number of cameras. The idea is that one camera is in triggered-auto mode (the

master), and the others in host-controlled mode (slaves). The master camera must

calculate the exposure and gains, the host then copies this to the slaves, and all changes

are then applied at the same time.

AP0100CS/D Rev. 6, Pub. 1/16 EN

28

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

Flicker Avoidance

Manual Mode

Manual mode is intended to allow simple manual exposure and white balance control

by the host. The host needs to set the CAM_AET_EXPOSURE_TIME_MS, CAM_AET_EX-

POSURE_GAIN and CAM_AWB_COLOR_TEMPERATURE controls, the camera will

calculate the appropriate integration times and gains.

Host Controlled

The Host Controlled mode is intended to give the host full control over exposure and

gains

Flicker Avoidance

Flicker occurs when the integration time is not an integer multiple of the period of the

light intensity. The AP0100CS can be programmed to avoid flicker for 50 or 60 Hertz. For

integration times below the light intensity period (10ms for 50Hz environment), flicker

cannot be avoided. The AP0100CS supports an indoor AE mode, that will ensure flicker-

free operation.

Flicker Detection

The AP0100CS supports flicker detection, the algorithm is designed only to detect a

50Hz or 60Hz flicker source.

Output Formatting

The pixel output data in AP0100CS will be transmitted as an 8/10 bit word over one or

two clocks.

Uncompressed YCbCr Data Ordering

The AP0100CS supports swapping YCbCr mode, as illustrated in Table 11.

Table 11:

YCbCr Output Data Ordering

Mode

Data Sequence

Default (no swap)

Cbi

Cri

Yi

Cri

Yi+1

Cri

Swapped CrCb

Swapped YC

Yi

Cbi

Cri

Yi+1

Swapped CrCb, YC

Yi

Cbi

The data ordering for the YCbCr output modes for AP0100CS are shown in Table 12:

Table 12:

Mode

YCbCr Output Modes (cam_port_parallel_msb_align=0x1)

Byte

Pixel i

Cbi

Pixel i+1

Cri

Notes

Odd (DOUT [15:8])

Even (DOUT [15:8])

Data range of 0-255 (Y=16-235 and C=16-240)

YCbCr_422_8_8

Yi

Yi+1

Data range of 0-1023 (Y=64-940 and C=64-

960)

Odd (DOUT [15:6])

Cbi

Cri

YCbCr_422_10_10

YCbCr_422_16

Even (DOUT [15:6])

Single (DOUT [15:0])

Yi

Yi+1

Cbi_Yi

Cri_Yi+1

Data range of 0-255 (Y=16-235 and C=16-240)

AP0100CS/D Rev. 6, Pub. 1/16 EN

29

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

Output Formatting

Note:

Odd means first cycle; even means second cycle.

Table 13:

YCbCr Output Modes (cam_port_parallel_msb_align=0x0)

Mode

Byte

Pixel i

Cbi

Pixel i+1

Cri

""Notes"

Odd (DOUT[7 :0])

Even (DOUT [7:0]

Odd (DOUT [9:0])

Even (DOUT [9:0])

Single (DOUT [15:0])

Data range of 0-255 (Y=16-235 and C=16-240)

YCbCr_422_8_8

Yi

Yi+1

Cbi

Cri

Data range of 0-1023 (Y=64-940 and C=64-960)"

Data range of 0-255 (Y=16-235 and C=16-240)

YCbCr_422_10_10

YCbCr_422_16

Yi

Yi+1

Cbi_Yi

Cri_Yi+1

Figure 18: 8- bit YCbCr Output (YCbCr_422_8_8)

P ixel C lock

Fram e V alid

Porch – 0-255 cycles

Line V alid

Data[15:8]

00

C r

Y

C b Y C r

Y

C b Y C r

Y

C b Y C r

Y C b Y C r

Data[7:0]

H Blank

Im age

H Blank

Im age

H Blank

P ixel C lock

Fram e V alid

Line V alid

Porch – 0-255 cycles

Data[15:8]

Data[7:0]

00

C r

Y

Cb

Y

C r

Y

Cb

Y

Cr

Y

Cb

Y

Cr

Y

Cb Y Cr

H Blank

Im age

H Blank

Im age

H Blank

Active Video

P ixel C lock

Fram e V alid

Line V alid

Porch – 0-255 cycles

Data[15:8]

Data[7:0]

00

Y

Cb Y Cr

Im age

Vblank

P ixel C lock

Fram e V alid

Line V alid

Porch – 0-255 cycles

00

C r

Data[15:8]

Data[7:0]

Y

Cb

Y

Cr

Im age

Vblank

Vertical Blanking

Notes: 1. Cb Y Cr Y by default.

2. cam_port_parallel_msb_align=0x0

AP0100CS/D Rev. 6, Pub. 1/16 EN

30

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

Output Formatting

Figure 19: 10-bit YCbCr Output (YCbCr_422_10_10)

P ixel C lock

Fram e V alid

Porch – 0-255 cycles

Line V alid

Data[5:0]

00

C r

Y

Cb

Y

Cr

Y

C b Y C r

Y

Cb

Y

Cr

Y Cb Y C r

Data[15:6]

H Blank

Im age

H Blank

Im age

H Blank

P ixel C lock

Fram e V alid

Line V alid

Porch – 0-255 cycles

00

Data[5:0]

Data[15:6]

C r

Y

Cb

Y

Cr

Y

Cb

Y

C r

Y

Cb

Y

Cr

Y

Cb Y C r

H Blank

Im age

H Blank

Im age

H Blank

Active Video

P ixel C lock

Fram e V alid

Line V alid

Porch – 0-255 cycles

00

Data[5:0]

Y

Cb Y C r

Data[15:6]

Im age

Vblank

P ixel C lock

Fram e V alid

Line V alid

Porch – 0-255 cycles

00

C r

Data[5:0]

Data[15:6]

Y

Cb

Y

Cr

Im age

Vblank

Vertical Blanking

Notes: 1. Cb Y Cr Y by default.

2. cam_port_parallel_msb_align=0x1

AP0100CS/D Rev. 6, Pub. 1/16 EN

31

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

Output Formatting

Figure 20: 16-bit YCbCr Output (YCbCr_422_16)

Pixel Clock

Frame Valid

Line Valid

Porch – 0-255 cycles

Y

Y Y Y Y

Data[7:0]

C r

Cb Cr Cb C r

Cb Cr Cb Cr

Cb Cr Cb C r

Data[15:8]

H Blank

Im age

H Blank

Im age

H Blank

Pixel Clock

Frame Valid

Line Valid

Porch – 0-255 cycles

Y

Y Y Y Y

Data[7:0]

C r

Cb Cr Cb Cr

Cb Cr Cb C r

Data[15:8]

H Blank

Im age

H Blank

Im age

H Blank

Active Video

Pixel Clock

Frame Valid

Line Valid

Porch – 0-255 cycles

Y

Y Y Y

Data[7:0]

C b C r C b C r

Data[15:8]

Im age

Vblank

Pixel Clock

Frame Valid

Line Valid

Porch – 0-255 cycles

Y

Y Y Y Y

Data[7:0]

C r

C b C r C b C r

Data[15:0]

Im age

Vblank

Vertical Blanking

AP0100CS/D Rev. 6, Pub. 1/16 EN

32

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

Output Formatting

Figure 21: Typical CCIR656 Output

Pixel Clock

Frame Valid

Line Valid

00

Data[15:8]

80 10 80 10 80 10 80 10 FF 00 00 80 Cb

Blanking SAV

Y

Cr

Y

Cb

Y

Cr

Y

FF 00 00 9D 80 10 80 10

EAV

80 10 80 10 FF 00 00 80 Cb

SAV

Y

Cr

Y

Cb

Y

Cr

Y

FF 00 00 9D 80 10 80 10

EAV Blanking

Data[7:0]

Image

Blanking

HBlank

Image

HBlank

Pixel Clock

Frame Valid

Line Valid

Data[15:8]

Data[7:0]

00

80 10 80 10 80 10 80 10 FF 00 00 80 Cb

Blanking SAV

Y

Cr

Y

Cb

Y

Cr

Y

FF 00 00 B6 80 10 80 10

EAV Blank

80 10 80 10 FF 00 00 AB 80 10 80 10

SAV Blank

80 10 80 10 FF 00 00 B6 80 10 80 10

EAV blank Blanking

Image

Blanking

HBlank

VBlank

HBlank

Field 1

Pixel Clock

Frame Valid

Line Valid

Data[15:8]

Data[7:0]

00

80 10 80 10 80 10 80 10 FF 00 00 C7 Cb

Blanking SAV

Y

Cr

Y

Cb

Y

Cr

Y

FF 00 00 DA 80 10 80 10

EAV

80 10 80 10 FF 00 00 C7 Cb

SAV

Y

Cr

Y

Cb

Y

Cr

Y

FF 00 00 DA 80 10 80 10

EAV Blanking

Image

Blanking

HBlank

Image

HBlank

Pixel Clock

Frame Valid

Line Valid

Data[15:8]

Data[7:0]

00

80 10 80 10 80 10 80 10 FF 00 00 C7 Cb

Blanking SAV

Y

Cr

Y

Cb

Y

Cr

Y

FF 00 00 F1 80 10 80 10

EAV Blank

80 10 80 10 FF 00 00 EC 80 10 80 10

SAV Blank

80 10 80 10 FF 00 00 F1 80 10 80 10

EAV blank Blanking

Image

Blanking

HBlank

VBlank

HBlank

Field 2

AP0100CS/D Rev. 6, Pub. 1/16 EN

33

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

Output Formatting

Figure 22: Typical CVBS Output (NTSC/PAL)

Line Valid to First Field Latency ~= STE Latency + 1 Field

Frame Valid In

Line Valid In

1

2

3

4

5

6

7

8

9

Video

Pre-Equalisation

Pulses

Post-Equalising

Pulses

Serration Pulses

Field 1 / 3

Frame Valid In

Line Valid In

Video

1

2

3

4

5

6

7

8

9

Pre-Equalisation

Pulses

Post-Equalising

Pulses

Serration Pulses

Field 2 / 4

AP0100CS/D Rev. 6, Pub. 1/16 EN

34

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

Bayer Modes

Bayer output modes are only available in progressive output mode before STE. The data

ordering for the ALTM Bayer output modes for AP0100CS are shown in Table 14.

Table 14:

Mode

ALTM Bayer Output Modes

D1 D1 D1 D1

Byte

5

4

3

2

D11 D10

D9

D9 D98 D7

D11 D10 D9 D8 D7

D8

D7

D6

D5

D4

D3

D2

D1

D0

ALTM_Bayer_10 Single

ALTM_Bayer_12 Single

0

D6

D5

D4

D3

D2

D1

D0

Table 14 and Table 15 show LSB aligned data; it is possible using register setting to obtain

MSB aligned data.

The data ordering for the Bayer output modes for AP0100CS are shown in Table 15.

Table 15:

Mode

Bayer Output Modes

Byte D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Notes

Bayer_1 Singl

0

D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

RAW Bayer

data

2

e

Note:

Bayer_12 can be selected by setting cam_mode_select = 0x1 and requesting a Change-Config

operation.

Sensor Embedded Data

The AP0100CS is capable of passing sensor embedded data in Bayer output mode only.

The AP0100CS Statistics are available through the serial interface. Refer to the developer

guide for details.

AP0100CS/D Rev. 6, Pub. 1/16 EN

35

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

Spatial Transform Engine (STE)

A spatial transform is defined as a transform in which some pixels are in different posi-

tions within the input and output pictures. Examples include zoom, lens distortion

correction, turn, and rotate. STE is a fully programmable engine which can perform

spatial transforms and eliminates the need for an expensive DSP for image correction.

Lens Distortion Correction

Automotive backup cameras typically feature a wide FOV lens so that a single camera

mounted above the center of the rear bumper can present the driver with a view of all

potential obstacles immediately behind the full width of the vehicle. Lenses with a wide

field of view typically exhibit at least a noticeable amount of barrel distortion.

Barrel distortion is caused by a reduction in object magnification the further away from

the optical axis.

For the image to appear natural to the driver, the AP0100CS corrects this barrel distor-

tion and reprocesses the image so that the resulting distortion is much smaller. This is

called distortion correction. Distortion correction is the ability to digitally correct the

lens barrel distortion and to provide a natural view of objects. In addition, with barrel

distortion one can adjust the perspective view to enhance the visibility by virtually

elevating the point of viewing objects.

Pan, Tilt, Zoom and Rotate

Using the STE it is possible to implement image transformations like Pan, Tilt, Zoom and

Rotate.

Figure 23: Uncorrected Image

AP0100CS/D Rev. 6, Pub. 1/16 EN

36

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

Spatial Transform Engine (STE)

Figure 24: Zoomed

Figure 25: Zoom and Look Left

AP0100CS/D Rev. 6, Pub. 1/16 EN

37

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

Overlay Capability

Figure 26: Zoom and Look Right

Overlay Capability

Figure 27 highlights the graphical overlay data flow of the AP0100CS. The images are

separated to fit into 4KB blocks of memory after compression.

•

Up to seven overlays may be blended simultaneously

Overlay size up to 720 x 576 pixels rendered

Selectable readout: rotating order is user programmable

Dynamic movement through predefined overlay images

Palette of 32 colors out of 16 million with 16 colors per bitmap

Each color has a YCbCr (8-8-8 bit) and 8 bits for the Alpha value (Transparency).

Each layer has a built in fader which when enabled scales the Alpha value for each

pixel.

•

Blend factors may be changed dynamically to achieve smooth transitions

The overlay engine is controlled through host commands that allow a bitmap to be

written piecemeal to a memory buffer through the two-wire serial interface, and

through a DMA chanel direct from SPI Flash memory. Multiple encoding passes may be

required to fit an image into a 4KB block of memory; alternatively, the image can be

divided into two or more blocks to make the image fit. Every graphic image may be posi-

tioned in an x/y direction and overlap with other graphic images.

The host may load an image at any time. Under control of DMA assist, data are trans-

ferred to the off-screen buffer in compressed form. This assures that no display data are

corrupted during the replenishment of the seven active overlay buffers.

AP0100CS/D Rev. 6, Pub. 1/16 EN

38

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

Overlay Capability

Figure 27: Overlay Data Flow

Overlay buffers: 4KB each

NVM

Decompress

Blend and Overlay

Bitmaps - compressed

Off-screen

buffer

Note:

These images are not actually rendered, but show conceptual objects and object blending.

AP0100CS/D Rev. 6, Pub. 1/16 EN

39

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

Serial Memory Partition

The contents of the Flash/EEPROM memory partition logically into three blocks (see

Figure 28):

•

Memory for overlay data and descriptors

Memory for register settings, which may be loaded at boot-up

Firmware extensions or software patches; in addition to the on-chip firmware, exten-

sions reside in this block of memory

These blocks are not necessarily contiguous.

Figure 28: Memory Partitioning

Flash

Fixed-size

Fixed Size

Fixed-size

Overlays – RLE

Overlays-RLE

Partitioning

Flash

Overlays – RLE

Overlays-RLE

Partitioning

12-byte Header

12Byte Header

Overlay

Data

Overlay Data

RLE Encoded

Data

2KB

4Kb

2kByte

Lens Shading

Lens Correction

Correction

Parameter

Alternate

Alternate Reg.

RegistSeerttSinegtting

S/W Patch

Software Patch

AP0100CS/D Rev. 6, Pub. 1/16 EN

40

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

Overlay Adjustment

To ensure a correct position of the overlay to compensate for assembly deviation, the

overlay can be adjusted with assistance from the calibration statistics engine:

• The calibration statistics engine supports a windowed 8-bin luma histogram, either

row-wise (vertical) or column-wise (horizontal).

• The example calibration statistics function of the firmware can be used to perform an

automatic successive approximation search of a cross-hair target within the scene.

• On the first frame, the firmware performs a coarse horizontal search, followed by a

coarse vertical search in the second frame.

• In subsequent frames, the firmware reduces the region-of-interest of the search to the

histogram bins containing the greatest accumulator values, thereby refining the search.

• The resultant X, Y location of the cross-hair target can be used to assign a calibration

value of offset selected overlay graphic image positions within the output image.

• The calibration statistics also supports a manual mode, which allows the host to access

the raw accumulator values directly.

Composite Video Output

The external pin GPIO[3] can be used to configure the device for default NTSC or PAL

operation. This and other video configuration settings are available as register settings

accessible through the serial interface.

Single-Ended and Differential Composite Output

The composite output can be operated in a single-ended or differential mode by simply

changing the external resistor configuration. For single-ended termination, see

Figure 29 on page 41. The differential schematic is shown in Figure 30 on page 42.

Figure 29: Single-Ended Termination

The DAC is differential, but it may be used to produce single-ended signals provided that

the unused (DAC_NEG) output is terminated into a resistance to ground approximately

equal to the load on the DAC_POS output. Without this termination, the internal bias

AP0100CS/D Rev. 6, Pub. 1/16 EN

41

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

Overlay Adjustment

circuits will not be kept in their proper operating regions and the dynamic performance

of the DAC will be degraded. Termination straight into ground causes all of the power

dissipation to occur on the chip, which is undesirable. If a one component saving was

absolutely critical, termination straight to ground is a possibility.

Figure 30: Differential Connection

If the user is not using the analog output then Figure 31 shows how the signals should be

connected.

Figure 31: No DAC

AP0100CS/D Rev. 6, Pub. 1/16 EN

42

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

Slave Two-Wire Serial Interface (CCIS)

The two-wire slave serial interface bus enables read/write access to control and status

registers within the AP0100CS.

The interface protocol uses a master/slave model in which a master controls one or

more slave devices.

Protocol

Data transfers on the two-wire serial interface bus are performed by a sequence of

low-level protocol elements, as follows:

•

a start or restart condition

a slave address/data direction byte

a 16-bit register address

an acknowledge or a no-acknowledge bit

data bytes

a stop condition

The bus is idle when both SCLK and SDATA are HIGH. Control of the bus is initiated with a

start condition, and the bus is released with a stop condition. Only the master can

generate the start and stop conditions.

The SADDR pin is used to select between two different addresses in case of conflict with

another device. If SADDR is LOW, the slave address is 0x90; if SADDR is HIGH, the slave

address is 0xBA. See Table 16 below. The user can change the slave address by changing a

register value.

Table 16:

Two-Wire Interface ID Address Switching

SADDR

Two-Wire Interface Address ID

0

1

0x90

0xBA

Start Condition

Data Transfer

A start condition is defined as a HIGH-to-LOW transition on SDATA while SCLK is HIGH.

At the end of a transfer, the master can generate a start condition without previously

generating a stop condition; this is known as a “repeated start” or “restart” condition.

Data is transferred serially, 8 bits at a time, with the MSB transmitted first. Each byte of

data is followed by an acknowledge bit or a no-acknowledge bit. This data transfer

mechanism is used for the slave address/data direction byte and for message bytes. One

data bit is transferred during each SCLK clock period. SDATA can change when SCLK is low

and must be stable while SCLK is HIGH.

AP0100CS/D Rev. 6, Pub. 1/16 EN

43

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

Protocol

Slave Address/Data Direction Byte

Bits [7:1] of this byte represent the device slave address and bit [0] indicates the data

transfer direction. A “0” in bit [0] indicates a write, and a “1” indicates a read. The default

slave addresses used by the AP0100CS are 0x90 (write address) and 0x91 (read address).

Alternate slave addresses of 0xBA (write address) and 0xBB (read address) can be

selected by asserting the SADDR input signal.

Message Byte

Message bytes are used for sending register addresses and register write data to the slave

device and for retrieving register read data. The protocol used is outside the scope of the

two-wire serial interface specification.

Acknowledge Bit

Each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the

SCLK clock period following the data transfer. The transmitter (which is the master when

writing, or the slave when reading) releases SDATA. The receiver indicates an acknowl-

edge bit by driving SDATA LOW. As for data transfers, SDATA can change when SCLK is

LOW and must be stable while SCLK is HIGH.

No-Acknowledge Bit

The no-acknowledge bit is generated when the receiver does not drive SDATA low during

the SCLK clock period following a data transfer. A no-acknowledge bit is used to termi-

nate a read sequence.

Stop Condition

A stop condition is defined as a LOW-to-HIGH transition on SDATA while SCLK is HIGH.

Typical Operation

A typical READ or WRITE sequence begins by the master generating a start condition on

the bus. After the start condition, the master sends the 8-bit slave address/data direction

byte. The last bit indicates whether the request is for a READ or a WRITE, where a “0”

indicates a WRITE and a “1” indicates a READ. If the address matches the address of the

slave device, the slave device acknowledges receipt of the address by generating an

acknowledge bit on the bus.

If the request was a WRITE, the master then transfers the 16-bit register address to which

a WRITE will take place. This transfer takes place as two 8-bit sequences and the slave

sends an acknowledge bit after each sequence to indicate that the byte has been

received. The master will then transfer the 16-bit data, as two 8-bit sequences and the

slave sends an acknowledge bit after each sequence to indicate that the byte has been

received. The master stops writing by generating a (re)start or stop condition. If the

request was a READ, the master sends the 8-bit write slave address/data direction byte

and 16-bit register address, just as in the write request. The master then generates a

(re)start condition and the 8-bit read slave address/data direction byte, and clocks out

the register data, 8 bits at a time. The master generates an acknowledge bit after each 8-

bit transfer. The data transfer is stopped when the master sends a no-acknowledge bit.

AP0100CS/D Rev. 6, Pub. 1/16 EN

44

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

Protocol

Single READ from Random Location

Figure 32 shows the typical READ cycle of the host to the AP0100CS. The first two bytes

sent by the host are an internal 16-bit register address. The following 2-byte READ cycle

sends the contents of the registers to host.

Figure 32: Single READ from Random Location

M+1

P

Previous Reg Address, N

Reg Address, M

Read Data

[7:0]

S

Slave Address 0 A Reg Address[15:8]

A

Reg Address[7:0] A Sr Slave Address

1

A

[15:8]

S = start condition

P = stop condition

Sr = restart condition

A = acknowledge

slave to master

master to slave

A = no-acknowledge

Single READ from Current Location

Figure 33 shows the single READ cycle without writing the address. The internal address

will use the previous address value written to the register.

Figure 33: Single Read from Current Location

Previous Reg Address, N

Reg Address, N+1

Slave Address

N+2

Read Data

[7:0]

Read Data

[15:8]

Read Data

[15:8]

Read Data

[7:0]

A

S

Slave Address

1

A

P

S

1 A

A

A P

Sequential READ, Start from Random Location

This sequence (Figure 34) starts in the same way as the single READ from random loca-

tion (Figure 32 on page 45). Instead of generating a no-acknowledge bit after the first

byte of data has been transferred, the master generates an acknowledge bit and

continues to perform byte READs until “L” bytes have been read.

Figure 34: Sequential READ, Start from Random Location

Previous Reg Address, N

Reg Address, M

M+1

A

Read Data

A

S

Slave Address

M+1

0

Reg Address[15:8]

A

Reg Address[7:0]

Sr

A

Slave Address

1

A

M+2

M+L-2

M+L-1

M+3

M+L

A

Read Data

(15:8)

Read Data

(15:8)

Read Data

(7:0)

Read Data

(7:0)

Read Data

(15:8)

Read Data

(7:0)

A

P

(15:8)

(7:0)

AP0100CS/D Rev. 6, Pub. 1/16 EN

45

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

Protocol

Sequential READ, Start from Current Location

This sequence (Figure 35) starts in the same way as the single READ from current loca-

tion (Figure 33). Instead of generating a no-acknowledge bit after the first byte of data

has been transferred, the master generates an acknowledge bit and continues to

perform byte reads until “L” bytes have been read.

Figure 35: Sequential READ, Start from Current Location

Previous Reg Address, N

N+1

N+2

A

N+L-1

N+L

P

_{Read D}R_ate_aad D_Ra_et_aa_{d Data}

A

Read Data

(7:0)

Read Data

(7:0)

Read Data

(15:8)

Read Data

(7:0)

A

S

Slave Address 1 A

Read Data

(15:8)

(7:0)

Single Write to Random Location

Figure 36 shows the typical WRITE cycle from the host to the AP0100CS.The first 2 bytes

indicate a 16-bit address of the internal registers with most-significant byte first. The

following 2 bytes indicate the 16-bit data.

Figure 36: Single WRITE to Random Location

PreviousRegAddress,N

RegAddress, M

WriteData

M+1

P

A

S

Slave Address

0

RegAddress[15:8]

RegAddress[7:0]

A

AP0100CS/D Rev. 6, Pub. 1/16 EN

46

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

Protocol

Sequential WRITE, Start at Random Location

This sequence (Figure 37) starts in the same way as the single WRITE to random location

(Figure 36). Instead of generating a no-acknowledge bit after the first byte of data has

been transferred, the master generates an acknowledge bit and continues to perform

byte writes until “L” bytes have been written. The WRITE is terminated by the master

generating a stop condition.

Figure 37: Sequential WRITE, Start at Random Location

Previous Reg Address, N

Reg Address, M

Write Data

M+1

S

Slave Address

M+1

0

Reg Address[15:8]

A

Reg Address[7:0]

A

M+2

M+L-2

M+L-1

M+3

M+L

P

Write Data

(15:8)

Write Data

(7:0)

Write Data

A

_(15:W₈₎rite Dat₍a_7:0)

A

_(15:W₈₎rite Dat₍a_7:0)

A

_(15:W₈₎rite Dat₍a_7:0)

A

AP0100CS/D Rev. 6, Pub. 1/16 EN

47

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

Protocol

Device Configuration

After power is applied and the device is out of reset (either the power on reset, hard or

soft reset), it will enter a boot sequence to configure its operating mode. There are essen-

tially three configuration modes: Flash/EEPROM Config, Auto Config, and Host Config.

The AP0100CS firmware supports a System Configuration phase at start-up. This

consists of three sub-phases of execution:

Flash detection, then one of:

a. Flash Config

b. Auto Config

c. Host Config

The System Configuration phase is entered immediately following power-up or reset.

Then the firmware performs Flash Detection.

Flash Detection attempts to detect the presence of an SPI Flash or EEPROM device:

•

If no device is detected, the firmware then samples the SPI_SDI pin state to determine

the next mode:

– If SPI_SDI is low, then it enters the Host-Config mode.

– If SPI_SDI is high, then it enters the Auto-Config mode.

If a device is detected, the firmware switches to the Flash-Config mode.

•

In the Flash-Config mode, the firmware interrogates the device to determine if it

contains valid configuration records:

•

If no records are detected, then the firmware enters the Auto-Config mode.

If records are detected, the firmware processes them. By default, when all Flash

records are processed the firmware switches to the Host-Config mode. However, the

records encoded into the Flash can optionally be used to instruct the firmware to

proceed to auto-config, or to start streaming (via a Change-Config).

In the Host-Config mode, the firmware performs no configuration, and remains idle

waiting for configuration and commands from the host. The System Configuration

phase is effectively complete and the AP0100CS will take no actions until the host issues

commands.

The Auto-Config mode uses the GPIO [5..2] pins to configure the operation of the device,

such as video format and pedestal (see Table 18, “GPIO Bit Descriptions in Auto-Config,”

on page 49). After Auto-Config completes the firmware switches to the Change-Config

mode.

AP0100CS/D Rev. 6, Pub. 1/16 EN

48

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

Protocol

Supported SPI Devices

Table 17 lists supported EEPROM/Flash devices. Devices not compatible will require a

firmware patch. Contact ON Semiconductor for additional support.

Table 17:

SPI Flash Devices

Manufacturer

Device

Type

Size

Autodetected

ManuID

Atmel

Sanyo¹

ST

AT26DF081A

AT25DF161

LE25FW806

M25P05A

M25P16

Flash

1Mbyte

2Mbyte

1Mbyte

64kbyte

2Mbyte

512byte

256byte

128byte

128kbyte

1kbyte

Yes

No

0x1f4501

0x1f4602

0x622662

0x202010

0x202015

0x20ffff

0x29ffff

Flash

ST

Flash

ST

M95040

EEPROM

ST

M95020

ST

M95010

ST

M95M01

M25AA080

M25LC080

Microchip

1kbyte

Notes: 1. Has been obsoleted.

Table 18: GPIO Bit Descriptions in Auto-Config

GPIO[5]

GPIO[4]

GPIO[3]

GPIO[2]

Low (“0”)

High (“1”)

Normal

NTSC

PAL

No pedestal

Pedestal

Vertical Flip

Horizontal mirror

AP0100CS/D Rev. 6, Pub. 1/16 EN

49

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

Host Command Interface

The AP0100CS has a mechanism to write higher level commands, the Host Command

Interface (HCI). Once a command has been written through the HCI, it will be executed

by on chip firmware and the results are reported back. EEPROM or Flash memory is also

available to store commands for later execution.

Figure 38: Interface Structure

14

bit

15

0

1

0

Host Command to FW

Response from FW

Addr 0x40

command register

door bell

bit

15

0

Addr 0xFC00

Parameter 0

cmd_handler_params_pool_0

cmd_handler_params_pool_1

cmd_handler_params_pool_2

Addr 0xFC02

Addr 0xFC04

Addr 0xFC06

Addr 0xFC08

Addr 0xFC0A

Addr 0xFC0C

cmd_handler_params_pool_3

cmd_handler_params_pool_4

cmd_handler_params_pool_5

cmd_handler_params_pool_6

cmd_handler_params_pool_7

Addr 0xFC0E

Parameter 7

Command Flow

The host issues a command by writing (through the two wire interface) to the Command

Register. All commands are encoded with bit 15 set, which automatically generates the

‘host command’ (doorbell) interrupt to the microprocessor.

Assuming initial conditions, the host first writes the command parameters (if any) to the

Parameters Pool (in the Command Handler’s shared-variable page), then writes the

command to Command Register. The firmware’s interrupt handler is invoked, which

immediately copies the Command Register contents. The interrupt handler then signals

the Command Handler task to process the command.

AP0100CS/D Rev. 6, Pub. 1/16 EN

50

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

Host Command Interface

If the host wishes to determine the outcome of the command, it must poll the Command

Register waiting for the doorbell bit to become cleared. This indicates that the firmware

completed processing the command. The contents of the Command Register indicate

the command’s result status. If the command generated response parameters, the host

can now retrieve these from the Parameters Pool.

The host must not write to the Parameters Pool, nor issue another command, until the

previous command completes. This is true even if the host does not care about the result

of the previous command. It is strongly recommended that the host tests that the door-

bell bit is clear before issuing a command.

Synchronous Command Flow

The typical ‘flow’ for synchronous commands is:

1. The host issues a ‘request’ command to perform an operation.

2. The registered command handler is invoked, validates the command parameters,

then performs the operation. The handler returns the command result status to indi-

cate the result of the operation.

3. The host retrieves the command result value, and any associated command response

parameters.

Asynchronous Command Flow

The typical ‘flow’ for asynchronous commands is:

1. The host issues a ‘request’ command to start an operation.

2. The registered command handler is invoked, validates and copies the command

parameters, then signals a separate task to perform the operation. The handler

returns the ENOERR return value to indicate the command was acceptable and is in

progress.

3. The host retrieves the command return value – if it is not ENOERR the host knows that

the command was not accepted and is not in progress.

4. Subsequently, the host issues an appropriate ‘get status’ command to both poll

whether the command has completed, and if so, retrieve any associated response

parameters.

5. The registered command handler is invoked, determines the state of the command

(via shared variables with the processing task), and returns either ‘EBUSY’ to indicate

the command is still in progress, or it returns the result status of the command.

6. The host must re-issue the ‘get status’ command until it does not receive the EBUSY

response.

Asynchronous commands exist to allow the Host to issue multiple commands to the

various subsystems without having to wait for each command to complete. This

prevents the host command interface from being blocked by a long-running command.

Therefore, each asynchronous command has a “Get Status” (or similar) command to

allow the Host to determine when the asynchronous command completes.

AP0100CS/D Rev. 6, Pub. 1/16 EN

51

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

Start-up Host Command Lock-out

The AP0100CS firmware implements an internal Host Command ‘lock’. At start-up, the

firmware obtains this lock, which prevents the Host from successfully issuing a host

command. All host commands will be rejected with EBUSY until the lock is freed.

The firmware releases the Host Command lock when it completes its start-up configura-

tion processing. The time to do this is dependent upon the configuration mechanism. It

is recommended that the Host poll the device with the System Manager Get State

command until ENOERR is returned.

Once the host can send serial commands it should perform the following sequence.

1. POLL command_register[15] until it clears (This is called the doorbell bit).

2. Continuously issue the SYSMGR_GET_STATE command (0x8101) until the result sta-

tus is not EBUSY

Below is some pseudocode that a host could use to implement the above sequence:

def systemWaitReadyFollowingReset(numRetries=10):

"""API function: waits for the system to be ready following reset (or powerup)

- first wait for the doorbell bit to clear - this indicates that the device can

accept host commands.

- then wait until the system has completed its configuration phase; the system is

ready when the SYSMGR_GET_STATE command does not return EBUSY.

- note the time for the system to be ready is dependent upon the active system

configuration mode.

- numRetries is the number of retries before timing-out

- returns result status code

"""

# Wait for doorbell bit to clear (indicates device can receive host commands)

retries = numRetries

while (0 != retries):

if (reg.COMMAND_REGISTER.DOORBELL.uncached_value == 0): break

# ready to receive

commands

retries -= 1

if (0 == retries):

# device failed to respond in time

return printError(ResultStatus.EIO, 'systemWaitReadyFollowingReset failed (doorbell

failed to clear)')

# Wait for the System Manager to complete the System Configuration phase

retries = numRetries

while (0 != retries):

res, currentState = sysmgrGetState()

if (ResultStatus.ENOERR == res): break # we're done

if (ResultStatus.EBUSY != res):

return printError(res, 'systemWaitReadyFollowingReset failed (sysmgrGetState

failed)')

retries -= 1

if (0 == retries):

# device failed to respond in time

return printError(ResultStatus.EAGAIN, 'systemWaitReadyFollowingReset failed (device

busy)')

return res

AP0100CS/D Rev. 6, Pub. 1/16 EN

52

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

Multitasking

The AP0100CS firmware is multitasking; therefore note that it is possible for an inter-

nally requested command to be in-progress when the Host issues a command. In these

circumstances, the Host command is immediately rejected with EBUSY. The Host

should reissue the command after a short interval.

Host Commands

Overview

The AP0100CS supports a number of functional modules or processing subsystems.

Each module or subsystem exposes commands to the host to control and configure its

operation.

Command Parameters

Result Status Codes

Command parameters are written to the Parameters Pool shared-variables by the host

prior to invoking the command. Similarly, any Command Response parameters are also

written back to the Parameters Pool by the firmware.

Table 19 shows the result status codes that are written by the Command Handler to the

Host Command register, in response to a command.

Table 19:

Result Status Codes

Value

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

Mnemonic

ENOERR

ENOENT

EINTR

Typical Interpretation – each command may re-interpret

No error – command was successful

No such entity

Operation interrupted

I/O failure

EIO

E2BIG

Too big

EBADF

Bad file/handle

EAGAIN

ENOMEM

EACCES

EBUSY

Would-block, try again

Not enough memory/resource

Permission denied

Entity busy, cannot support operation

Entity exists

EEXIST

ENODEV

EINVAL

ENOSPC

ERANGE

ENOSYS

EALREADY

Device not found

Invalid argument

no space/resource to complete

parameter out-of-range

operation not supported

already requested/exists

Note:

Any unrecognized host commands will be immediately rejected by the Command Handler, with

result status code ENOSYS.

AP0100CS/D Rev. 6, Pub. 1/16 EN

53

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

Summary of Host Commands

Table 20 on page 54 through Table 31 on page 56 show summaries of the host

commands. The commands are divided into the following sections:

•

System Manager

Overlay

GPIO

Flash Manager

STE

Sequencer

Patch Loader

Miscellaneous

Calibration Stats

Following is a summary of the Host Interface commands. The description gives a quick

orientation. The “Type” column shows if it is an asynchronous or synchronous

command. For a complete list of all commands including parameters, consult the Host

Command Interface Specification document.

Table 20:

System Manager Host Command

Set State

Value

0x8100

0x8101

0x8102

Type

Description

Asynchronous

Synchronous

Request the system enter a new state

Get the current state of the system

Configures the power state of the system

Get State

Config Power Management

Table 21:

Overlay Host Commands

Value

Overlay Host Command

Type

Description

Enable Overlay

Get Overlay State

Set Calibration

Set Bitmap Property

Get Bitmap Property

Set String Property

Load Buffer

0x8200

0x8201

0x8202

0x8203

0x8204

0x8205

0x8206

0x8207

0x8208

0x8209

0x820A

0x820B

0x820C

0x820D

0x820E

Synchronous

Enable or disable the overlay subsystem

Retrieves the state of the overlay subsystem

Set the calibration offset

Synchronous

Asynchronous

Synchronous

Asynchronous

Set a property of a bitmap

Get a property of a bitmap

Set a property of a character string

Load an overlay buffer with a bitmap (from Flash)

Retrieve status of an active load buffer operation

Write directly to an overlay buffer

Read directly from an overlay buffer

Enable or disable an overlay layer

Retrieve the status of an overlay layer

Set the character string

Load Status

Write Buffer

Read Buffer

Enable Layer

Get Layer Status

Set String

Get String

Get the current character string

Load String

Load a character string (from Flash)

AP0100CS/D Rev. 6, Pub. 1/16 EN

54

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

Summary of Host Commands

Table 22:

STE Manager Host Commands

STE Manager Host

Command

Value

Type

Description

Config

0x8310

0x8311

0x8312

0x8313

Synchronous

Asynchronous

Synchronous

Configure using the default NTSC or PAL configuration stored in ROM

Load a configuration from SPI NVM to the configuration cache

Get status of a Load Config request

Load Config

Load Status

Write Config

Write a configuration (via CCIS) to the configuration cache

Table 23:

GPIO Host Command

Set GPIO Property

GPIO Host Commands

Value

Type

Description

0x8400

0x8401

0x8402

0x8403

0x8404

Synchronous Set a property of one or more GPIO pins

Synchronous Retrieve a property of a GPIO pin

Get GPIO Property

Set GPIO State

Synchronous

Set the state of a GPO pin or pins

Get the state of a GPI pin or pins

Get GPIO State

Set GPI Association

Synchronous Associate a GPI pin state with a Command Sequence stored in SPI

NVM

Get GPI Association

0x8405

Synchronous

Retrieve a GPIO pin association

Table 24:

Flash Manager Host Command

Flash Mgr Host Command

Get Lock

Value

Type

Description

0x8500

0x8501

0x8502

0x8503

0x8504

0x8505

0x8506

0x8507

0x8508

0x8509

0x850A

Asynchronous

Synchronous

Asynchronous

Synchronous

Request the Flash Manager access lock

Retrieve the status of the access lock request

Release the Flash Manager access lock

Configure the Flash Manager and underlying SPI NVM subsystem

Read data from the SPI NVM

Lock Status

Release Lock

Config

Read

Write

Write data to the SPI NVM

Erase Block

Erase Device

Query Device

Status

Erase a block of data from the SPI NVM

Erase the SPI NVM device

Query device-specific information

Obtain status of current asynchronous operation

Configure the attached SPI NVM device

Config Device

Table 25:

Sequencer Host Command

Refresh

Value

0x8606

0x8607

Type

Description

Asynchronous Refresh the automatic image processing algorithm configuration

Refresh Status

Synchronous

Retrieve the status of the last Refresh operation

Table 26:

Patch Loader Host Command

Patch Loader Host

Command

Value

0x8700

0x8701

Type

Description

Load Patch

Status

Asynchronous

Synchronous

Load a patch from SPI NVM and automatically apply

Get status of an active Load Patch or Apply Patch request

AP0100CS/D Rev. 6, Pub. 1/16 EN

55

AP0100CS HDR: Image Signal Processor (ISP)

Summary of Host Commands

Table 26:

Patch Loader Host Command

Patch Loader Host

Command

Value

0x8702

0x8706

Type

Description

Apply Patch

Reserve RAM

Asynchronous

Synchronous

Apply a patch (already located in Patch RAM)

Reserve RAM to contain a patch

Table 27:

Miscellaneous Host Command

Invoke Command Seq

Value

0x8900

0x8901

0x8902

Type

Description

Synchronous

Invoke a sequence of commands stored in SPI NVM

Configures the Command Sequence processor

Wait for a system event to be signalled

Config Command Seq Processor

Wait for Event

Table 28:

Calibration Stats Host Commands

Calibration Stats Host Command

Calib Stats Control

Value

0x8B00

0x8B01

Type

Description

Asynchronous

Synchronous

Start statistics gathering

Read the results back

Calib Stats Read

Table 29:

Event Monitor Host Command

Value

Type

Description

Event Monitor Set Association

0x8C00

Synchronous

Associate an system event with a Command Sequence stored in

NVM

Event Monitor Get Association

0x8C01

Synchronous

Retrieve an event association

Table 30:

CCI Manager Host Commands

CCI Manager Host

Command

Value

Type

Description

Get Lock

Lock Status

Release Lock

Config

0x8D00

0x8D01

0x8D02

0x8D03

0x8D04

0x8D05

0x8D06

0x8D07

0x8D08

Asynchronous

Synchronous

Asynchronous

Synchronous

Request the CCI Manager access lock

Retrieve the status of the access lock request

Release the CCI Manager access lock

Configure the CCI Manager and underlying CCI subsystem

Set the target CCI device address

Set Device

Read

Read one or more bytes from a 16-bit address

Write one or more bytes to a 16-bit address

Read-modify-write 16-bit data to a 16-bit address

Obtain status of current asynchronous operation

Write

Write Bitfield

CCI Status

Table 31:

Sensor Manager Host Commands

Sensor Manager Host Command

Value

0x8E00

0x8E01

Type

Description

Discover Sensor

Initialize Sensor

Synchronous

Discover sensor

Initialize attached sensor

AP0100CS/D Rev. 6, Pub. 1/16 EN

56

AP0100CS HDR: Image Signal Processor (ISP)

Usage Modes

How a camera based on the AP0100CS will be configured depends on what features are

used. In the simplest case, an AP0100CS operating in Auto-Config mode with no

customized settings might be sufficient. A back-up camera with dynamic input from the

steering system will require a µC with a system bus interface. Flash sizes vary depending

on the register and firmware data being transferred—somewhere between 1KB to 16MB.

The two-wire bus is adequate since only high-level commands are used.

In the simplest case no EEPROM or Flash memory or µC is required, as shown in

Figure 39. This is truly a single chip operation.

Figure 39: Auto-Config Mode

AP0100CS + image sensor

Auto-Config Mode

Analog Output

Digital Out

The AP0100CS can be configured by a serial EEPROM or Flash through the SPI Interface.

Figure 40: Flash Mode

AP0100CS

+ image sensor

Serial

EEPROM/Flash

SPI

Figure 41: Host Mode with Flash

AP0100CS

+ image sensor

Serial

EEPROM/Flash

8/16bit μC

two-wire

System Bus

SPI

AP0100CS/D Rev. 6, Pub. 1/16 EN

57

AP0100CS HDR: Image Signal Processor (ISP)

Usage Modes

In this configuration all settings are communicated to the AP0100CS and sensor through

the microcontroller.

Figure 42: Host Mode

AP0100CS

+ image sensor

8/16bit μC

two-wire

System Bus

AP0100CS/D Rev. 6, Pub. 1/16 EN

58

AP0100CS HDR: Image Signal Processor (ISP)

Usage Modes

Caution Stresses greater than those listed in Table 32 may cause permanent damage to the device.

This is a stress rating only, and functional operation of the device at these or any other con-

ditions above those indicated in the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect reliabil-

ity.

Table 32:

Absolute Maximum Ratings

Rating

Parameter

Min

Max

Unit

Digital power (1.8V)

Host I/O power (2.5V,3.3V)

Sensor I/O power (1.8V, 2.8V)

Digital DAC power

-0.3

2.25

1.7

4.95

V

°C

5.4

1.1

2.5

PLL power

1.1

Digital core power

1.1

2.5

OTPM power (2.5V, 3.3V)

DC Input Voltage

2.25

-0.3

-50

5.4

VDDIO_*+0.3

150

DC Output Voltage

Storage temperature

AP0100CS/D Rev. 6, Pub. 1/16 EN

59

AP0100CS HDR: Image Signal Processor (ISP)

Usage Modes

Table 33:

Parameter

Electrical Characteristics and Operating Conditions

Condition

Min

1.62

2.25

1.7

Typ

1.8

Max

1.98

3.6

Unit

V

Supply input to on-chip regulator (VDD_REG)

Host IO voltage (VDDIO_H)

2.5/3.3

1.8/2.8

1.2

V

Sensor IO voltage (VDDIO_S)

Core voltage (VDD)

3.1

V

1.08

3

1.32

3.6

V

PLL voltage (VDD_PLL)

1.2

V

DAC digital voltage (VDD_DAC)

DAC analog voltage (VDDA_DAC)

HiSPi PHY votlage (VDD_PHY)

OTPM power supply (VDDIO_OTPM)

1.2

V

3.3

V

2.3

2.8

3.1

V

2.25

-30

2.5/3.3

3.6

V

Functional operating temperature

(ambient - T_A)

70

°C

Storage temperature

-55

150

°C

AP0100CS/D Rev. 6, Pub. 1/16 EN

60

AP0100CS HDR: Image Signal Processor (ISP)

Usage Modes

Table 34:

AC Electrical Characteristics

Default Setup Conditions: fEXTCLK= 27 MHz, VDDIO_H = VDD_OTPM = 2.8V, VDD_REG = VDDIO_S = 1.8V, VDDA_DAC=3.3V,

VDD_DAC=1.2V; T_A= 25°C unless otherwise stated

Symbol Parameter

Conditions

Min

6

Typ

Max

Unit

MHz

ns

Notes

f_EXTCLKExternal clock frequency

30

1

2

t_R

t_F

External input clock rise time

External input clock fall time

10%-90% VDDIO_H

90%-10% VDDIO_H

–

2

5

–

5

ns

D_EXTCLKExternal input clock duty cycle

40

–

50

500

60

%

t_JITTER

External input clock jitter

–

ps

Pixel clock frequency (one-clock/pixel)

Pixel clock frequency (two-clocks/pixel)

6

74.125

MHz

f_PIXCLK

6

84

5

t_RPIXCLKPixel clock rise time (10-90%)

t_FPIXCLKPixel clock fall time (10-90%)

C_LOAD=35pf

–

2

1

ns

–

5

t_PD

PIXCLK to data valid

PIXCLK to FV HIGH

PIXCLK to LV HIGH

PIXCLK to FV LOW

PIXCLK to LV LOW

–

5

t_PFH

t_PLH

t_PFL

t_PLL

–

5

–

5

–

5

–

5

Notes: 1. VIH/VIL restrictions apply.

2. This is applicable only a when the PLL is bypassed. When the PLL is being used then the user should

ensure that VIH/VIL is met.

Table 35:

DC Electrical Characteristics

Symbol

Parameter

Condition

Min

Max

Unit Notes

VIH

Input HIGH voltage

VDDIO_H or VDDIO_S *

0.8

–

V

1

2

VIL

IIN

Input LOW voltage

–

VDDIO_H or VDDIO_S *

0.2

V

Input leakage current VIN= 0V or VIN = VDDIO_H

or VDDIO_S

10

A

V

VOH

VOL

Output HIGH voltage

VDDIO_H or VDDIO_S*

0.80

–

Output LOW voltage

–

VDDIO_H or VDDIO_S *

0.2

V

Notes: 1. VIL and VIH have min/max limitations specified by absolute ratings.

2. Excludes pins that have internal PU resistors.

Table 36:

Video DAC Electrical Characteristics

Default Setup Conditions: f_EXTCLK= 27 MHz, VDDIO_H = VDD_OTPM = 2.8V, VDD_REG = VDDIO_S = 1.8V,

VDDA_DAC=3.3V, VDD_DAC=1.2V; T_A= 25°C unless otherwise stated

Parameter

Symbol

Min

Typ

Max Unit

Comments

DC Accuracy

Differential Nonlinearity

Integral Nonlinearity

Load Capacitance

DNL

INL

1

3

LSB

CLOAD

10

pF

At maximum output current

AP0100CS/D Rev. 6, Pub. 1/16 EN

61

AP0100CS HDR: Image Signal Processor (ISP)

Usage Modes

Table 36:

Video DAC Electrical Characteristics

Default Setup Conditions: f_EXTCLK= 27 MHz, VDDIO_H = VDD_OTPM = 2.8V, VDD_REG = VDDIO_S = 1.8V,

VDDA_DAC=3.3V, VDD_DAC=1.2V; T_A= 25°C unless otherwise stated

Parameter

Symbol

OER

Min

Typ

Max Unit

Comments

Offset Error

1

2

5

% FS

For differental output only

Gain Error

DGER

GER

Absolute Gain Error

Figure 43: Frame_Sync (Interlaced Operation) Diagram

Table 37:

Frame_Sync (Interlaced Operation) Parameters

Parameter

Name

Conditions Min

Typ Max Unit

EXTCLK cycles

ms

T_FRAME_SYNC

T_RESYNC

T_FRAME_SYNC

T_RESYNC

3

NTSC

PAL

100

120

T_RESYNC

AP0100CS/D Rev. 6, Pub. 1/16 EN

62

AP0100CS HDR: Image Signal Processor (ISP)

Usage Modes

Figure 44: Frame_Sync (Progressive Operation) Diagram

Table 38:

Trigger Timing

Parameter

Name

Conditions

Min

Typ

Max

Unit

FRAME_SYNC to FV_OUT

t_{FRMSYNC_FVH}

8 lines+ exposure

–

Lines

time + sensor delay

FRAME_SYNC to

TRIGGER_OUT

t_{TRIGGER_PROP}

t_FRAMESYNC

–

3

–

9

–

ns

t_{FRAME_SYNC}

EXTCLK cycles

AP0100CS/D Rev. 6, Pub. 1/16 EN

63

AP0100CS HDR: Image Signal Processor (ISP)

Usage Modes

NTSC Signal Parameters

Table 39:

NTSC Signal Parameters

Default Setup Conditions: f_EXTCLK= 27 MHz, VDD_REG = 1.8V, VDD_IO_S = 1.8V, VDDA_DAC= 3.3V,

VDDIO_OTPM=2.5V, VDD_PHY = 2.5V

Parameter

Min

15734.25

59.94

111

Typ

15734.27

59.94

148

Max

15734.28

59.94

222

Units

Hz

ns

Notes

Line Frequency

Field Frequency

Sync Rise Time

Sync Fall Time

Sync Width

111

148

222

ns

4.60

39

4.74

40

4.80

s

Sync Level

41

IRE

s

2

Burst Level

36

40

44

Sync to Setup

9.2

9.5

10.3

(with pedestal off)

Sync to Burst Start

Front Porch

4.71

1.27

5

5.3

1.7

7.5

100

5.71

2.22

10

s

Black Level

IRE

1, 2, 3

White Level

90

110

Notes: 1. Black and white levels are referenced to the blanking level.

2. NTSC convention standardized by the IRE (1 IRE = 7.14mV).

3. DAC ref = 3.74k, load = 37.5

AP0100CS/D Rev. 6, Pub. 1/16 EN

64

AP0100CS HDR: Image Signal Processor (ISP)

Usage Modes

Figure 45: Video Timing

A

D

E

C

B

J

F

K

H

G

H

Table 40:

Video Timing: Specification from Rec. ITU-R BT.470

NTSC

PAL

27 MHz

Signal

27 MHz

Units

A

B

C

D

E

H Period

Hsync to burst

burst

63.556

4.71 to 5.71

2.23 to 3.11

9.20 to 10.30

2.655 ±0.20

1.27 to 2.22

4.70 ± 0.10

0.25

64.00

s

5.60 ± 0.10

2.25 ± 0.23

10.20 ± 0.30

52 +0, -0.3

1.5 +0.3, -0.0

4.70 ± 0.20

0.20 ±0.10

Hsync to Signal

Video Signal

Front

F

G

H

Hsync Period

Sync rising/falling edge

AP0100CS/D Rev. 6, Pub. 1/16 EN

65

AP0100CS HDR: Image Signal Processor (ISP)

Usage Modes

Figure 46: Equalizing Pulse

L

I

J

K

Table 41:

Equalizing Pulse: Specification from Rec. ITU-R BT.470

NTSC

27 MHz

PAL

27 MHz

Signal

Units

I

J

H/2 Period

Pulse width

31.778

2.30 ± 0.10

0.25

32.00

s

2.35 ± 0.10

0.25 ± 0.05

3.0 ± 2.0

K

L

Pulse rising/falling edge

Signal to pulse

1.50 ± 0.10

AP0100CS/D Rev. 6, Pub. 1/16 EN

66

AP0100CS HDR: Image Signal Processor (ISP)

Usage Modes

Figure 47: V Pulse

M

O

N

P

Table 42:

V Pulse: Specification from Rec. ITU-R BT.470

NTSC

PAL

27 MHz

Signal

27 MHz

Units

M

N

O

P

H/2 Period

Pulse width

31.778

27.10 (nominal)

4.70 ± 0.10

0.25

32.00

s

27.30 ± 0.10

4.70 ± 0.10

0.25 ± 0.05

V pulse interval

Pulse rising/falling edge

Table 43:

Standby Current Consumption

Default Setup Conditions: f_EXTCLK= 27 MHz, VDD_REG=1.8V; VDDIO_H not included in measurement

VDDIO_S= 1.8V, VDDA_DAC=3.3V, VDDIO_OTPM=2.5V, VDD_PHY=2.5V, T_A= 70°C unless otherwise stated

Parameter

Condition

Typ Max

Unit

3.2

6.9

3.5

7.6

mA

mW

mA

Total standby current when asserting the STANDBY signal

Total standby current

f

_EXTCLK= 27 MHz

mW

AP0100CS/D Rev. 6, Pub. 1/16 EN

67

AP0100CS HDR: Image Signal Processor (ISP)

Usage Modes

Table 44:

Operating Current Consumption

Default Setup Conditions: f_EXTCLK= 27 MHz, VDD_REG=1.8V; VDDIO_H not included in measurement

VDDIO_S= 1.8V, VDDA_DAC=3.3V, VDDIO_OTPM=2.5V, VDD_PHY=2.5V, T_A= 70°C unless otherwise stated

Symbol

Conditions

Min

1.62

2.25

3

Typ

1.8

Max

1.98

2.75

3.6

Unit

V

VDD_REG

VDDIO_H=2.5V

VDDIO_H=3.3V

VDDIO_S=1.8V

VDDIO_S=2.8V

VDDIO_OTPM=2.5V

VDDIO_OTPM=3.3V

VDDA_DAC

2.5

V

3.3

V

1.7

2.5

2.25

3

1.8

1.9

V

2.8

3.1

V

2.5

2.75

3.6

V

3.3

V

3

3.3

3.6

V

VDD_PHY

2.3

2.8

3.1

V

NTSC HiSPi 12-bit

NTSC HiSPi 14-bit

NTSC

63.7

63.6

64.1

59.5

3.2

mA

mW

IDD_REG

PAL

NTSC HiSPi 12-bit

NTSC HiSPi 14-bit

NTSC

3.2

3.3

IDDIO_S

PAL

3.3

NTSC HiSPi 12-bit

NTSC HiSPi 14-bit

NTSC

0.1

IDDIO_OTPM

IDDA_DAC

PAL

0.1

NTSC HiSPi 12-bit

NTSC HiSPi 14-bit

NTSC

1, 2

19.54

0.3

PAL

NTSC HiSPi 12-bit

NTSC HiSPi 14-bit

NTSC

0.3

0.0

IDD_PHY

PAL

0.0

NTSC HiSPi 12-bit

NTSC HiSPi 14-bit

NTSC

185.66

185.56

177.46

Total power consumption

PAL

Notes: 1. R_DAC_POS=75, R_DAC_NEG=37.5, R_DAC_REF= 3.74k

2. . Current in single ended mode. When in differential mode the current will be 37.9mA.

AP0100CS/D Rev. 6, Pub. 1/16 EN

68

AP0100CS HDR: Image Signal Processor (ISP)

Usage Modes

Table 45:

Inrush Current

Supply

Max Current

(mA)

Voltage

AVDD

1.8

2.5/3.3

1.8

240

260

15

VDDIO_H

VDDIO_S

2.8

55

VDDA_DAC

3.3

270

180

VDDIO_OTPM

2.5/3.3

AP0100CS/D Rev. 6, Pub. 1/16 EN

69

AP0100CS HDR: Image Signal Processor (ISP)

Two-Wire Serial Register Interface

The electrical characteristics of the two-wire serial register interface (SCLK, SDATA) are

shown in Figure 48 and Table 46.

Figure 48: Slave Two Wire Serial Bus Timing Parameters (CCIS)

SDATA

t

f

t

BUF

SU;DAT

LOW

f

r

HD;STA

r

SCLK

t

SU;STA

t

HD;STA

SU;STO

t

HIGH

HD;DAT

P

S

Sr

Table 46:

Slave Two-Wire Serial Bus Characteristics (CCIS)

Default Setup Conditions: fEXTCLK = 27 MHz; VDDIO_H = VDD_OTPM = 2.8V; VDD_REG = VDDIO_S = 1.8V; VDDA_DAC=

3.3V; VDD_DAC = 1.2V; T_A= 25°C unless otherwise stated

Standard-Mode

Fast-Mode

Parameter

Symbol

Min

Max

Min

Max

Unit

SCLK Clock Frequency

f_SCL

0

100

0

400

KHz

Hold time (repeated) START condition.

After this period, the first clock pulse is generated

LOW period of the SCLK clock

t_HD;STA

t_LOW

t_HIGH

t_SU;STA

t_HD;DAT

t_SU;DAT

t_r

4.0

4.7

4.0

4.7

0²

-

0.6

-

s

ns

s

-

1.3

-

HIGH period of the SCLK clock

-

0.6

-

Set-up time for a repeated START condition

Data hold time

-

0.6

-

0.9³

-

3.45³

0

Data set-up time

250

-

1000

300

-

100

Rise time of both SDATA and SCLK signals (10-90%)

Fall time of both SDATA and SCLK signals (10-90%)

Set-up time for STOP condition

20 + 0.1Cb⁴

0.6

300

-

t_f

-

t_SU;STO

t_BUF

4.0

4.7

Bus free time between a STOP and START

condition

-

1.3

-

Capacitive load for each bus line

Serial interface input pin capacitance

SDATA max load capacitance

SDATA pull-up resistor

Cb

C_{IN_SI}

C_{LOAD_SD}

R_SD

-

400

3.3

30

-

400

3.3

30

pF

-

pF

1.5

4.7

1.5

4.7

K

Notes: 1. All values referred to VIHmin = 0.9 VDD and VILmax = 0.1VDD levels. EXCLK = 27 MHz.

2. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the

undefined region of the falling edge of SCLK.

3. The maximum t_HD;DAThas only to be met if the device does not stretch the LOW period (t_LOW) of

the SCLK signal.

4. Cb = total capacitance of one bus line in pF.

The electrical characteristics of the master two-wire serial register interface (M_SCLK,

M_SDATA) are shown in Figure 49 and Table 47.

AP0100CS/D Rev. 6, Pub. 1/16 EN

70

AP0100CS HDR: Image Signal Processor (ISP)

Two-Wire Serial Register Interface

Figure 49: Master Two Wire Serial Bus Timing Parameters (CCIM)

SDATA

t

f

t

BUF

SU;DAT

LOW

f

r

HD;STA

r

SCLK

t

SU;STA

t

HD;STA

SU;STO

t

HIGH

HD;DAT

P

S

Sr

Table 47:

Parameter

Master Two-Wire Serial Bus Characteristics (CCIM)

Default Setup Conditions: fEXTCLK = 27 MHz; VDDIO_H = VDD_OTPM = 2.8V; VDD_REG = VDDIO_S = 1.8V; VDDA_DAC=

3.3V; VDD_DAC = 1.2V; T_A= 25°C unless otherwise stated

Standard-Mode

Fast-Mode

Symbol

Min

Max

Min

Max

Unit

M_SCLK Clock Frequency

f_SCL

0

100

0

400

KHz

Hold time (repeated) START condition.

After this period, the first clock pulse is generated

LOW period of the M_SCLK clock

t_HD;STA

t_LOW

4.0

4.7

4.0

4.7

0²

250

-

0.6

-

s

ns

s

pF

K

-

1.2

HIGH period of the M_SCLK clock

Set-up time for a repeated START condition

Data hold time

t_HIGH

t_SU;STA

t_HD;DAT

t_SU;DAT

t_r

0.6

-

0.6

-

3.45³

0

0.9³

Data set-up time

-

100

20 + 0.1Cb⁴

-

Rise time of both M_SDATA and M_SCLK time (10-90%)

Fall time of both M_SDATA and M_SCLK time (10-90%)

Set-up time for STOP condition

1000

300

-

300

-

t_f

-

t_SU;STO

t_BUF

4.0

4.7

-

0.6

1.3

-

Bus free time between a STOP and START condition

Capacitive load for each bus line

Serial interface input pin capacitance

M_SDATA max load capacitance

-

Cb

400

3.3

30

4.7

400

3.3

30

4.7

C_{IN_SI}

C_{LOAD_SD}

R_SD

-

M_SDATA pull-up resistor

1.5

Notes: 1. All values referred to VIHmin = 0.9 VDD and VILmax = 0.1VDD levels. EXCLK = 27 MHz.

2. A device must internally provide a hold time of at least 300 ns for the M_SDATA signal to bridge the

undefined region of the falling edge of M_SCLK.

3. The maximum t_HD;DAThas only to be met if the device does not stretch the LOW period (t_LOW) of

the M_SCLK signal.

4. Cb = total capacitance of one bus line in pF.

AP0100CS/D Rev. 6, Pub. 1/16 EN

71

AP0100CS HDR: Image Signal Processor (ISP)

Package Diagram

Figure 50: Package Diagram

VFBGA100 7x7

CASE 138AH

ISSUE O

DATE 30 DEC 2014

AP0100CS/D Rev. 6, Pub. 1/16 EN

72

AP0100CS HDR: Image Signal Processor (ISP)

Package Diagram

ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the

rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/

Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its

products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including

without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications

and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey

any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,

or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.

Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and

distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such

unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

This literature is subject to all applicable copyright laws and is not for resale in any manner.

AP0100CS/D Rev. 6, Pub. 1/16 EN

73


型号：	AP0100CS2L00SPGAH-GEVB
厂家：	ONSEMI
描述：	High-Dynamic Range (HDR) Image Signal Processor (ISP)
文件：	总73页 (文件大小：4019K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AP0100CS2L00SPGAH-GEVB [ONSEMI]

相关型号：

AP0100CS2L00SUGA0-DR

AP0100CS2L00SUGA0-DR-E

AP0100CS2L00SUGA0-DR1

AP0101AT2L00XPGA0-AM-DR

AP0101AT2L00XPGA0-AM-TR

AP0101AT2L00XPGA0-DR

AP0101AT2L00XPGA0-TR

AP0101AT2L00XPGA0-TR-E

AP0101CS

AP0101CS2L00SPGA0-DR

AP0101CS2L00SPGA0-DR1

AP0101CS2L00SPGAD3-GEVK