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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Features

1/3-Inch CMOS Digital Image Sensor

AR0132AT Datasheet, Rev. 9

For the latest data sheet, please visit www.onsemi.com

Table 1:

Key Parameters

Features

Parameter

Typical Value

• Superior low-light performance

• HD video (720p60)

Optical format

Active pixels

1/3-inch (6 mm)

1280 x 960 = 1.2 Mp

3.75 m

RGB Bayer, or monochrome

Electronic rolling shutter

6 – 50 MHz

74.25 MHz

• Linear or high dynamic range capture

• Video/Single Frame modes

• On-chip AE and statistics engine

• Parallel and serial output

• Auto black level calibration

• Context switching

Pixel size

Color filter array

Shutter type

Input clock range

Output clock maximum

• Temperature Sensor

Output

Serial

HiSPi 12-, 14-, or 20-bit

12-bit

Parallel

Full resolution

720p

Applications

• Automotive imaging

Frame

rate

45 fps

60 fps

• Video surveillance

• 720p60 video applications

• High dynamic range imaging

Responsivity

5.48 V/lux-sec

43.9 dB

SNR_MAX

Maximum dynamic range

>115 dB

Supply

voltage

I/O

1.8 or 2.8 V*

1.8 V

Digital

Analog

HiSPi

General Description

2.8 V

ON Semiconductor's AR0132AT is a 1/3-inch CMOS

digital image sensor with an active-pixel array of

1280H x 960V. It captures images in either linear or

high dynamic range modes, with a rolling-shutter

readout. It includes sophisticated camera functions

such as auto exposure control, windowing, and both

video and single frame modes. It is designed for both

low light and high dynamic range scene performance.

It is programmable through a simple two-wire serial

interface. The AR0132AT produces extraordinarily

clear, sharp digital pictures, and its ability to capture

both continuous video and single frames makes it the

perfect choice for a wide range of applications, includ-

ing surveillance and HD video.

0.4V or 1.8V

Power consumption

(typical)

270 mW (1280 x 720 60 fps

Parallel output Linear Mode)

460 mW (1280x720 60 fps

Parallel output HDR Mode)

–40°C to + 105° C (ambient)

Operating temperature

Package options

–40°C to + 120° C (junction)

9x9 mm iBGA

Bare die

Note: *1.8V VDD_IO is recommended for better row noise

performance

AR0132AT/D Rev. 9, 2/16 EN

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Ordering Information

Table 2:

Available Part Numbers

Part Number

Product Description

Orderable Product Attribute Description

AR0132AT6C00XPEA0-DPBR1

AR0132AT6C00XPEA0-DRBR1

AR0132AT6C00XPEA0-TPBR

AR0132AT6C00XPEA0-TRBR

AR0132AT6C00XPD20

RGB, 0deg CRA, iBGA Package

Drypack, Protective Film, Anti-Reflective Glass

Drypack, Anti-Reflective Glass

Tape & Reel, Protective Film, Anti-Reflective Glass

Tape & Reel, Anti-Reflective Glass

RGB, 0deg CRA, Reconstruct Die

RGB, 0deg CRA, Wafer

AR0132AT6C00XPW90

AR0132AT6B00XPEA0-DRBR1

AR0132AT6B00XPW90

RCCB, 0deg CRA, iBGA Package

RCCB, 0deg CRA, Wafer

Drypack, Anti-Reflective Glass

AR0132AT6G00XPEA0-DPBR1

AR0132AT6G00XPEA0-DRBR1

AR0132AT6G00XPEA0-TPBR

AR0132AT6G00XPEA0-TRBR

AR0132AT6M00XPEA0-DPBR1

AR0132AT6M00XPEA0-DRBR1

AR0132AT6M00XPEA0-TPBR

AR0132AT6M00XPW90

RGBC, 0deg CRA, iBGA Package

Mono, 0deg CRA, iBGA Package

Mono, 0deg CRA, Wafer

Drypack, Protective Film, Anti-Reflective Glass

Drypack, Anti-Reflective Glass

Tape & Reel, Protective Film, Anti-Reflective Glass

Tape & Reel, Anti-Reflective Glass

Drypack, Protective Film, Anti-Reflective Glass

Drypack, Anti-Reflective Glass

Tape & Reel, Protective Film, Anti-Reflective Glass

AR0132AT6R00XPEA0-DPBR1

AR0132AT6R00XPEA0-DRBR1

AR0132AT6R00XPEA0-TPBR

AR0132AT6R00XPEA0-TRBR

AR0132AT6R00XPW90

RCCC, 0deg CRA, iBGA Package

RCCC, 0deg CRA, Wafer

Drypack, Protective Film, Anti-Reflective Glass

Drypack, Anti-Reflective Glass

Tape & Reel, Protective Film, Anti-Reflective Glass

Tape & Reel, Anti-Reflective Glass

AR0132AT6C00XPEAD3-GEVK

AR0132AT6C00XPEAH3-GEVB

AR0132AT6C00XPEAD3-S215-GEVK

AR0132AT6C00XPEAH3-S215-GEVB

AR0132AT6B00XPEAD3-GEVK

AR0132AT6B00XPEAH3-GEVB

AR0132AT6G00XPEAD3-GEVK

AR0132AT6G00XPEAH3-GEVB

AR0132AT6M00XPEAD3-GEVK

AR0132AT6M00XPEAH3-GEVB

AR0132AT6R00XPEAD3-GEVK

AR0132AT6R00XPEAH3-GEVB

RGB Demo Kit, Sunex DSL945D

RGB Headboard, Sunex DSL945D

RGB Demo Kit, Sunex DSL215

RGB Headboard, Sunex DSL215

RCCB Demo Kit, Sunex DSL945D

RCCB Headboard, Sunex DSL945D

RGBC Demo Kit, Sunex DSL945D

RGBC Headboard, Sunex DSL945D

Mono Demo Kit, Sunex DSL945D

Mono Headboard, Sunex DSL945D

RCCC Demo Kit, Sunex DSL945D

RCCC Headboard, Sunex DSL945D

See the ON Semiconductor Device Nomenclature document (TND310/D) for a full

description of the naming convention used for image sensors. For reference documenta-

tion, including information on evaluation kits, please visit our web site at

www.onsemi.com.

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Table of Contents

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Functional Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Pixel Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Output Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

High Dynamic Range Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Real-Time Context Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Two-Wire Serial Register Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Spectral Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Power-On Reset and Standby Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Package Dimensions (Case 503AF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

General Description

The ON Semiconductor AR0132AT can be operated in its default mode or programmed

for frame size, exposure, gain, and other parameters. The default mode output is a 960p-

resolution image at 45 frames per second (fps). In linear mode, it outputs 12-bit raw

data, using either the parallel or serial (HiSPi) output ports. In high dynamic range

mode, it outputs 12-bit compressed data using parallel output, or 12-bit or 14-bit

compressed or 20-bit linearized data using the HiSPi port. The device may be operated

in video (master) mode or in single frame trigger mode.

FRAME_VALID and LINE_VALID signals are output on dedicated pins, along with a

synchronized pixel clock in parallel mode.

The AR0132AT includes additional features to allow application-specific tuning:

windowing and offset, adjustable auto-exposure control, auto black level correction, and

on-board temperature sensor. Optional register information and histogram statistic

information can be embedded in first and last two lines of the image frame.

The sensor is designed to operate in a wide temperature range (–40°C to +105°C).

Functional Overview

The AR0132AT is a progressive-scan sensor that generates a stream of pixel data at a

constant frame rate. It uses an on-chip, phase-locked loop (PLL) that can be optionally

enabled to generate all internal clocks from a single master input clock running between

6 and 50 MHz. The maximum output pixel rate is 74.25 Mp/s, corresponding to a clock

rate of 74.25 MHz. Figure 1 shows a block diagram of the sensor.

Figure 1:

Block Diagram

External

Clock

OTPM

Memory

PLL

Active Pixel Sensor

(APS)

Array

Timing and Control

(Sequencer)

Auto Exposure

and Stats Engine

Power

Serial

Output

Parallel

Output

Pixel Data Path

(Signal Processing)

Analog Processing and

A/D Conversion

Trigger

Two-Wire

Serial

Control Registers

Interface

User interaction with the sensor is through the two-wire serial bus, which communi-

cates with the array control, analog signal chain, and digital signal chain. The core of the

sensor is a 1.2 Mp Active-Pixel Sensor array. The timing and control circuitry sequences

through the rows of the array, resetting and then reading each row in turn. In the time

interval between resetting a row and reading that row, the pixels in the row integrate

incident light. The exposure is controlled by varying the time interval between reset and

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Functional Overview

readout. Once a row has been read, the data from the columns is sequenced through an

analog signal chain (providing offset correction and gain), and then through an analog-

to-digital converter (ADC). The output from the ADC is a 12-bit value for each pixel in

the array. The ADC output passes through a digital processing signal chain (which

provides further data path corrections and applies digital gain). The sensor also offers a

high dynamic range mode of operation where multiple images are combined on-chip to

produce a single image at 20-bit per pixel value. A compressing mode is further offered

to allow this 20-bit pixel value to be transmitted to the host system as a 12- or 14-bit

value with close to zero loss in image quality. The pixel data are output at a rate of up to

74.25 Mp/s, in parallel to frame and line synchronization signals.

Figure 2:

Typical Configuration: Serial Four-Lane HiSPi Interface

Digital Digital

I/O

Core

HiSPi

power

PLL

Analog Analog

1

power power

power power power

VDD_IO

VDD

VDD_PLL

VAA VAA_PIX

SLVS0P

SLVS0N

SLVS1P

Master clock

(6–50 MHz)

EXTCLK

SLVS1N

SLVS2P

SLVS2N

To

controller

S

ADDR

S

DATA

SLVS3P

SCLK

From

controller

SLVS3N

SLVSCP

TRIGGER

OE_BAR

STANDBY

RESET_BAR

TEST

SLVSCN

DGND

AGND

V

DD_IO

VDD

V

DD_SLVS

VDD_PLL

V

AA

VAA_PIX

Digital

ground

Analog

ground

Notes: 1. All power supplies must be adequately decoupled.

2. ON Semiconductor recommends a resistor value of 1.5k, but a greater value may be used for

slower two-wire speed.

3. This pull-up resistor is not required if the controller drives a valid logic level on SCLK at all times.

4. The parallel interface output pads can be left unconnected if the serial output interface is used.

5. ON Semiconductor recommends that 0.1F and 10F decoupling capacitors for each power supply

are mounted as close as possible to the pad. Actual values and results may vary depending on lay-

out and design considerations. Check the AR0132AT demo headboard schematics for circuit recom-

mendations.

6. ON Semiconductor recommends that analog power planes are placed in a manner such that cou-

pling with the digital power planes is minimized.

7. I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage currents.

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Functional Overview

Figure 3:

Typical Configuration: Parallel Pixel Data Interface

Digital Digital

I/O core

power power

PLL Analog Analog

power power power

1

VDD_IO

VDD

VDD_PLL

VAA VAA_PIX

Master clock

(6–50 MHz)

EXTCLK

D

OUT [11:0]

PIXCLK

To

controller

LINE_VALID

FRAME_VALID

SADDR

SDATA

SCLK

From

Controller

TRIGGER

OE_BAR

STANDBY

RESET_BAR

TEST

AGND

DGND

V

AA

VDD_IO

VDD

VDD_PLL

VAA_PIX

Digital

ground

Analog

ground

Notes: 1. All power supplies must be adequately decoupled.

2. ON Semiconductor recommends a resistor value of 1.5k, but a greater value may be used for

slower two-wire speed.

3. This pull-up resistor is not required if the controller drives a valid logic level on SCLK at all times.

4. The serial interface output pads and VDDSLVS can be left unconnected if the parallel output inter-

face is used.

5. ON Semiconductor recommends that 0.1F and 10F decoupling capacitors for each power supply

are mounted as close as possible to the pad. Actual values and results may vary depending on lay-

out and design considerations. Check the AR0132AT demo headboard schematics for circuit recom-

mendations.

6. ON Semiconductor recommends that analog power planes are placed in a manner such that cou-

pling with the digital power planes is minimized.

7. I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage currents.

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Functional Overview

Table 3:

Name

Pin Descriptions, 9 x 9 mm, 63-ball iBGA

iBGA Pin

Type

Description

SLVS0N

SLVS0P

SLVS1N

SLVS1P

STANDBY

VDD_PLL

SLVSCN

SLVSCP

SLVS2N

SLVS2P

VAA

A2

A3

Output

Input

HiSPi serial data, lane 0, differential N.

HiSPi serial data, lane 0, differential P.

HiSPi serial data, lane 1, differential N.

HiSPi serial data, lane 1, differential P.

Standby-mode enable pin (active HIGH).

PLL power.

A4

A5

A8

B1

Power

Output

Power

Input

B2

HiSPi serial DDR clock differential N.

HiSPi serial DDR clock differential P.

HiSPi serial data, lane 2, differential N.

HiSPi serial data, lane 2, differential P.

Analog power.

B3

B4

B5

B7, B8

C1

EXTCLK

VDD_SLVS

SLVS3N

SLVS3P

DGND

External input clock.

C2

Power

Output

HiSPi power.

C3

HiSPi serial data, lane 3, differential N.

HiSPi serial data, lane 3, differential P.

Digital ground.

C4

C5, D4, D5, E5, F5, G5, H5 Power

VDD

A6, A7, B6, C6, D6

Power

Input

Digital power.

AGND

C7, C8

Analog ground.

SADDR

D1

Two-Wire Serial address select.

Two-Wire Serial clock input.

Two-Wire Serial data I/O.

SCLK

D2

Input

SDATA

D3

I/O

VAA_PIX

LINE_VALID

FRAME_VALID

PIXCLK

VDD_IO

DOUT8

D7, D8

Power

Output

Power

Output

Input.

Pixel power.

E1

Asserted when DOUT line data is valid.

Asserted when DOUT frame data is valid.

Pixel clock out. DOUT is valid on rising edge of this clock.

I/O supply power.

E2

E3

E6, F6, G6, H6, H7

F1

F2

Parallel pixel data output.

DOUT9

Parallel pixel data output.

DOUT10

DOUT11

TEST

F3

Parallel pixel data output.

F4

Parallel pixel data output (MSB)

Manufacturing test enable pin (connect to DGND).

Parallel pixel data output.

F7

DOUT4

G1

G2

G3

G4

G7

G8

H1

H2

H3

H4

H8

Output

Input

DOUT5

Parallel pixel data output.

DOUT6

Parallel pixel data output.

DOUT7

Parallel pixel data output.

TRIGGER

OE_BAR

DOUT0

Exposure synchronization input.

Output enable (active LOW).

Parallel pixel data output (LSB)

Parallel pixel data output.

Input

Output

Input

DOUT1

DOUT2

Parallel pixel data output.

DOUT3

Parallel pixel data output.

RESET_BAR

Asynchronous reset (active LOW). All settings are restored to factory

default.

FLASH

NC

E4

E7, E8

F8

Output

Flash control output.

No connection.

Reserved

No connection. Must be left floating for normal operation.

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Functional Overview

Figure 4:

9 x 9 mm 63-Ball IBGA Package

1

2

3

4

5

6

7

8

SLVS0N

SLVS0P

SLVS1N

SLVS1P

VDD

STANDBY

A

B

C

D

E

V^DD

V^DD_PLL

EXTCLK

SADDR

SLVSCN

SLVSCP

SLVS3N

SLVS2N

SLVS2P

V^DD

VAA

AGND

VAA_PIX

NC

VAA

AGND

V^DD_

SLVS

D^GND

SLVS3P

VDD

DGND

SCLK

SDATA

VAA_PIX

LINE_

VALID

FRAME_

VALID

PIXCLK

VDD_IO

FLASH

D^GND

NC

Reserved

D^OUT8

D^OUT9

DOUT10

DOUT11

D^GND

TEST

F

D^OUT4

DOUT5

DOUT1

DOUT6

DOUT2

DOUT7

DOUT3

DGND

VDD_IO

TRIGGER

V^DD_IO

OE_BAR

G

H

RESET_

BAR

D^OUT0

Top View

(Ball Down)

Note:

No ball on A1 pin, 63 balls in total in actual iBGA package.

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Pixel Data Format

Pixel Array Structure

The AR0132AT pixel array is configured as 1412 columns by 1028 rows, (see Figure 5).

The dark pixels are optically black and are used internally to monitor black level. Of the

right 96 columns, 64 are dark pixels used for row noise correction. Of the top 24 rows of

pixels, 12 of the dark rows are used for black level correction. There are 1288 columns by

972 rows of optically active pixels that can be readable. While the sensor's format is 1280

x 960, the additional active columns and active rows are included for use when hori-

zontal or vertical mirrored readout is enabled, to allow readout to start on the same

pixel. The pixel adjustment is always performed for monochrome or color versions. The

active area is surrounded with optically transparent dummy pixels to improve image

uniformity within the active area. Not all dummy pixels or barrier pixels can be read out.

Figure 5:

Pixel Array Description

1412

2 extra active +

2 light dummy +

4 barrier +

100 dark +

4 barrier

4 extra active +

2 light dummy +

4 barrier +

24 dark +

1028

10 barrier

1288x972(readable active pixel)

4.83x3.645 mm ^2

2 light dummy +

10 barrier

6 extra active +

2 light dummy +

4 barrier

E xtra

active

pixel

R eadable

A ctive

pixel

Light

dummy

pixel

B arrier

pixel

D ark

pixel

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Pixel Data Format

Figure 6:

Pixel Color Pattern Detail (Top Right Corner)

Column Readout Direction

Readable Active Pixel (0,0)

Physical Pixel (112, 44)

R

G

R

G

B

G

B

G

B

R

G

R

G

B

G

B

G

B

R

G

R

G

B

G

B

G

B

R

G

R

G

B

G

B

G

B

G

R

G

R

G

R

G

R

G

Default Readout Order

By convention, the sensor core pixel array is shown with pixel (0,0) in the top right

2corner (see Figure 6). This reflects the actual layout of the array on the die. Also, the first

readable pixel location of the sensor in default condition is that of physical pixel

address(112, 44). This first readable pixel location corresponds to the register

x_addr_start(R0x3004)=0x0000 and the register y_addr_start(R0x3002)=0x0000.

The optical center of the readable pixel array is the location of the register x_ad-

dr_end(R0x3008)=643 and the register y_addr_end(R0x3006)=485.

When the sensor is imaging, the active surface of the sensor faces the scene as shown in

Figure 7. When the image is read out of the sensor, it is read one row at a time, with the

rows and columns sequenced as shown in Figure 7 on page 10.

Figure 7:

Imaging a Scene

Lens

Scene

Sensor (rear view)

Row

Readout

Order

Column Readout Order

Pixel (0,0)

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Pixel Data Format

Digital Gain Control

AR0132AT supports four digital gains for the color channels: Red, Green1 (green pixels

on the red rows), Green2 (green pixels on the blue rows), and Blue. Digital gain control of

the AR0132AT is dependent on the configuration of the x_addr_start register. Table 4

illustrates how the digital gains are applied when x_addr_start is even or odd number.

Table 4:

Digital Gain Control for odd and even x_addr_start (R0x3004)

Pixels

x_addr_start

Gain

Register

Red

Even

Odd

Even

Odd

Even

Odd

Even

Odd

red_gain

green1_gain

red_gain

R0x305A

R0x3056

R0x305A

R0x305C

R0x3058

R0x305C

Green1 (on Red rows)

Green2 (on Blue rows)

Blue

green2_gain

blue_gain

green2_gain

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Output Data Format

The AR0132AT image data is read out in a progressive scan. Valid image data is

surrounded by horizontal and vertical blanking (see Figure 8). The amount of horizontal

row time (in clocks) is programmable through R0x300C. The amount of vertical frame

time (in rows) is programmable through R0x300A. LINE_VALID (LV) is HIGH during the

shaded region of Figure 8. Optional Embedded Register setup information and Histo-

gram statistics information are available in first two and last row of image data.

Figure 8:

Spatial Illustration of Image Readout

P_0,0P_0,1P_0,2.....................................P_0,n-1P_0,n

P_1,0P_1,1P_1,2.....................................P_1,n-1P_1,n

00 00 00 .................. 00 00 00

HORIZONTAL

BLANKING

VALID IMAGE

P

_m-1,0P_m-1,1.....................................P_m-1,n-1P_m-1,n

P_m,0P_m,1.....................................P_m,n-1P_m,n

00 00 00 .................. 00 00 00

00 00 00 ..................................... 00 00 00

00 00 00 .................. 00 00 00

VERTICAL/HORIZONTAL

BLANKING

VERTICAL BLANKING

00 00 00 .................. 00 00 00

00 00 00 ..................................... 00 00 00

Readout Sequence

Typically, the readout window is set to a region including only active pixels. The user has

the option of reading out dark regions of the array, but if this is done, consideration must

be given to how the sensor reads the dark regions for its own purposes.

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Output Data Format

Parallel Output Data Timing

The output images are divided into frames, which are further divided into lines. By

default, the sensor produces 968 rows of 1284 columns each. The FRAME_VALID (FV)

and LINE_VALID (LV) signals indicate the boundaries between frames and lines, respec-

tively. PIXCLK can be used as a clock to latch the data. For each PIXCLK cycle, with

respect to the falling edge, one 12-bit pixel datum outputs on the DOUT pins. When both

FV and LV are asserted, the pixel is valid. PIXCLK cycles that occur when FV is de-

asserted are called vertical blanking. PIXCLK cycles that occur when only LV is de-

asserted are called horizontal blanking.

Figure 9:

Default Pixel Output Timing

PIXCLK

FV

LV

Pn

P5

DOUT[11:0]

P0

P1

P2

P3

P4

Horizontal

Blanking

Horizontal

Blanking

Vertical Blanking

Valid Image Data

LV and FV

The timing of the FV and LV outputs is closely related to the row time and the frame time.

FV will be asserted for an integral number of row times, which will normally be equal to

the height of the output image.

LV will be asserted during the valid pixels of each row. The leading edge of LV will be

offset from the leading edge of FV by six PIXCLKs. Normally, LV will only be asserted if FV

is asserted; this is configurable as described below.

LV Format Options

The default situation is for LV to be de-asserted when FV is de-asserted. By configuring

R0x306E[1:0], the LV signal can take two different output formats. The formats for

reading out four lines and two vertical blanking lines are shown in Figure 10.

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Output Data Format

Figure 10: LV Format Options

FV

LV

Default

FV

LV

Continuous LV

The timing of an entire frame is shown in Figure 16: “Line Timing and FRAME_VALID/

LINE_VALID Signals,” on page 17.

Serial Output Data Timing

The AR0132AT also uses ON Semiconductor's High-Speed Serial Pixel Interface

(“HiSPi”). The physical interface comprises differential serial data lines and a differential

clock line. The protocol layer formats the data and synchronization signals separately,

with Sync codes defined for active image boundaries. Figure 11 shows the configuration

between the HiSPi transmitter and the receiver. There are two options for HiSPi output:

SLVS or HiVCM mode selectable through register 0x306E bit 9. Setting this bit to 0 selects

SLVS; setting the bit to 1 selects HiVCM.

Figure 11: HiSPi Transmitter and Receiver Interface Block Diagram

A camera containing

the HiSPi transmitter

A host (DSP) containing

the HiSPi receiver

Dp0

Dn0

Dp1

Dn1

Dp0

Dn0

Dp1

Dn1

Rx

PHY0

Tx

PHY0

Dp2

Dn2

Dp3

Dn3

Dp3

Dn3

Cp0

Cn0

Cp0

Cn0

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Output Data Format

HiSPi Physical Layer

The HiSPi physical layer has four data lanes and an associated clock lane. Depending on

the sensor operating mode and data rate, it can be configured to use either 2, 3, or 4

lanes. The PHY will serialize a 12- to 20-bit data word and transmit each bit of data

centered on a rising edge of the clock, the second on the following falling edge of clock.

Figure 12 shows bit transmission. In this example, the word is transmitted in order of

MSB to LSB. The receiver latches data at the rising and falling edge of the clock.

Figure 12: Timing Diagram

TxPost

cp

… .

cn

TxPre

dp

dn

MSB

LSB

1 UI

DLL Timing Adjustment

The AR0132AT includes a DLL to compensate for differences in group delay for each

data lane. The DLL is connected to the clock lane and each data lane, which acts as a

control master for the output delay buffers. Once the DLL has gained phase lock, each

lane can be delayed in 1/8 unit interval (UI) steps. This additional delay allows the user

to increase the setup or hold time at the receiver circuits and can be used to compensate

for skew introduced in PCB design.

Delay compensation may be set for clock and/or data lines in the hispi_timing register

R0x31C0. If the DLL timing adjustment is not required, the data and clock lane delay

settings should be set to a default code of 0x000 to reduce jitter, skew, and power dissipa-

tion.

Figure 13: Block Diagram of DLL Timing Adjustment

delay

data_lane 0 data_lane 1 clock _lane 0 data_lane 2 data_lane 3

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Output Data Format

Figure 14: Delaying the Clock with Respect to Data

1 UI

dataN (DATAN_DEL = 000)

cp (CLOCK_DEL = 000)

cp (CLOCK_DEL = 001)

cp (CLOCK_DEL = 010)

cp (CLOCK_DEL = 011)

cp (CLOCK_DEL = 100)

cp (CLOCK_DEL = 101)

cp (CLOCK_DEL = 110)

cp (CLOCK_DEL =111)

increasing CLOCK_DEL[2:0] increases clock delay

Figure 15: Delaying Data with Respect to the Clock

cp (CLOCK_DEL = 000)

dataN (DATAN_DEL = 000)

dataN(DATAN_DEL = 001)

dataN(DATAN_DEL = 010)

dataN(DATAN_DEL = 011)

dataN(DATAN_DEL = 100)

dataN(DATAN_DEL = 101)

dataN(DATAN_DEL = 110)

dataN(DATAN_DEL = 111)

increasing DATAN_DEL[2:0] increases data delay

t

1 UI

DLLSTEP

HiSPi Protocol Layer

The HiSPi protocol is described the HiSPi Protocol Specification document. Contact

your local Field Applications Engineer or sales representative to get a copy.

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Output Data Format

Frame Time

The pixel clock (PIXCLK) represents the time needed to sample 1 pixel from the array.

The sensor outputs data at the maximum rate of 1 pixel per PIXCLK. One row time

(t

) is the period from the first pixel output in a row to the first pixel output in the next

ROW

row. The row time and frame time are defined by equations in Table 5.

Figure 16: Line Timing and FRAME_VALID/LINE_VALID Signals

...

FRAME_VALID

LINE_VALID

...

P1

A

Q

A

Q

A

P2

Table 5:

Frame Time (Example Based on 1280 x 960, 45 Frames Per Second)

Default Timing

at 74.25 MHz

Parameter

Name

Equation

A

Active data time

Context A: R0x3008 - R0x3004 + 1

Context B: R0x308E - R0x308A + 1

1280 pixel clocks

= 17.23s

P1

Frame start blanking

Frame end blanking

Horizontal blanking

Line (Row) time

6 (fixed)

6 pixel clocks

= 0.08s

6 pixel clocks

= 0.08s

370 pixel clocks

= 4.98s

1650 pixel clocks

P2

6 (fixed)

Q

R0x300C - A

R0x300C

A+Q (t_ROW

)

= 22.22s

V

Vertical blanking

Frame valid time

Total frame time

Context A: (R0x300A-(R0x3006-R0x3002+1)) x (A + Q)

Context B: ((R0x30AA-(R0x3090-R0x308C+1)) x (A + Q)

49,500 pixel clocks

= 666.66s

1,584,000 pixel clocks

= 21.33ms

Nrows x (A + Q)

F

Context A: ((R0x3006-R0x3002+1)*(A+Q))-Q+P1+P2

Context B: ((R0x3090-R0x308C+1)*(A+Q))-Q+P1+P2

V + (N rows x (A + Q))

1,633,500 pixel clocks

= 22.22ms

Sensor timing is shown in terms of pixel clock cycles (see Figure 8 on page 12). The

recommended pixel clock frequency is 74.25 MHz. The vertical blanking and the total

frame time equations assume that the integration time (coarse integration time plus fine

integration time) is less than the number of active lines plus the blanking lines:

Window Height + Vertical Blanking

(EQ 1)

If this is not the case, the number of integration lines must be used instead to determine

the frame time, (see Table 6). In this example, it is assumed that the coarse integration

time control is programmed with 2000 rows and the fine integration time total is zero.

For master mode, if the integration time registers exceed the total readout time, then the

vertical blanking time is internally extended automatically to adjust for the additional

integration time required. This extended value is not written back to the

frame_length_lines register. The frame_length_lines register can be used to adjust

frame-to-frame readout time. This register does not affect the exposure time but it may

extend the readout time.

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Output Data Format

Table 6:

Frame Time: Long Integration Time

Equation

Default Timing

at 74.25 MHz

Parameter Name

(Number of Pixel Clock Cycles)

Total frame time (long

integration time)

Context A: (R0x3012 x (A + Q)) + R0x3014 + P1 + P2

Context B: (R0x3016 x (A + Q)) + V R0x3018 + P1 + P2

3,300,012 pixel clocks

= 44.44ms

F’

Note:

The AR0132AT uses column parallel analog-digital converters; thus short line timing is not possi-

ble. The minimum total line time is 1650 columns (horizontal width + horizontal blanking). The

minimum horizontal blanking is 370.

Exposure

Total integration time is the result of Coarse_Integration_Time and Fine_Integration_-

Time registers in Linear mode and is the result of Coarse_Integration_Time in HDR

mode, and it depends also on whether manual or automatic exposure is selected.

The actual total integration time, t

is defined as:

INT

tINT = tINTCoarse - 410 - tINTFine

(EQ 2)

= (number_of_lines_of_integration x line_time) - ((410 + number_of_pixels_of_integra-

tion) x pixel_time)

where:

– Number of Lines of Integration (Auto Exposure Control: Enabled)

When automatic exposure control (AEC) is enabled, the number of lines of integra-

tion may vary from frame to frame, with the limits controlled by R0x311E (mini-

mum auto exposure time) and R0x311C (maximum auto exposure time).

– Number of Lines of Integration (Auto Exposure Control: Disabled)

If AEC is disabled, the number of lines of integration equals the value in R0x3012

(context A) or R0x3016 (context B).

– Number of Pixels of Integration

The number of fine integration time pixels is independent of AEC mode (enabled

or disabled):

•

Context A: the number of pixels of integration equals the value in R0x3014.

Context B: the number of pixels of integration equals the value in R0x3018.

where < Fine_Integration_Time < (Line_Length_Pck - 545) in linear mode.

Typically, the value of the Coarse_Integration_Time register is limited to the number of

lines per frame (which includes vertical blanking lines), such that the frame rate is not

affected by the integration time. For more information on coarse and fine integration

time settings limits, please refer to the Register Reference document.

Note:

In HDR mode, there are specific limitations on coarse_integration_time due to the

number of line buffers available. Please refer to the section called “HDR Specific

Exposure Settings” on page 21.

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

High Dynamic Range Mode

By default, the sensor powers up in Linear Mode, however, the AR0132AT can be config-

ured to run in HDR mode. The HDR scheme used is multi-exposure HDR. This allows

the sensor to handle 120dB of dynamic range. The sensor also features a linear mode. In

HDR mode, the sensor sequentially captures three exposures by maintaining three sepa-

rate read and reset pointers that are interleaved within the rolling shutter readout. The

intermediate pixel values are stored in line buffers while waiting for the three exposure

values to be present. As soon as a pixel's three exposure values are available, they are

combined to create a linearized 20-bit value for each pixel’s response. This 20-bit value is

then optionally compressed back to a 12- or 14-bit value for output. For 14-bit mode, the

compressing is lossless. In 12-bit mode, there is minimal data loss. Figure 17 shows the

HDR data compression:

Figure 17: HDR Data Compression

Decompressed linear

output

ADC max code

K2 = knee point 2

K1 = knee point 1

Pout = P

Piece-wise Compressed

Signal Output From

Sensor

Signal Response to Light Intensity

The HDR mode is selected when Operation_Mode_Ctrl, R0x3082[1:0] = 0. Further

controls on exposure time limits and compressing are controlled by R0x3082[5:2] and

R0x31D0. More details can be found in the AR0132AT Register Reference.

In HDR mode, when compression is used, there are two types of knee-points: (i) T1/T2

and T2/T3 capture knee-points and (ii) POUT and POUT2 compression knee-points

(Figure 17). Aligning the capture knee-points on top of the compression knee-points,

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

High Dynamic Range Mode

can avoid code losses (SNR loss) in the compression. Table 7 and Table 8 below show the

knee points for the different modes. Alternatively, the sensor automatically reports the

knee points and can be read directly from registers R0x319A and R0x319C.

Table 7:

T1/T2

Knee Points for Compression to 14 Bits

T2/T3

Exposure Ratio

(R2)

Exposure Ratio

(R1)

POUT

MAX

POUT1

= P1

POUT2 = (P2 - P1)/

R1 + POUT1

= (PMAX - P2)/

R0x3082[3:2]

P1

P2

R0x3082[5:4]

PMAX

(R1*R2) + POUT2

4x

2¹²

4096

2¹⁴

7168

7680

7936

4x

8x

2¹⁶

2¹⁷

2¹⁸

2¹⁷

2¹⁸

2¹⁹

2¹⁸

2¹⁹

2²⁰

10240

10752

11008

10752

11264

11520

11008

11520

11776

16x

4x

8x

2¹²

2¹⁵

8x

16x

4x

16x

2¹²

2¹⁶

8x

16x

Table 8:

T1/T2

Knee Points for Compression to 12 Bits

T2/T3

Exposure Ratio

(R2)

Exposure Ratio

(R1)

POUT

MAX

POUT1

= P1

POUT2 = (P2 - P1)/

(R1* 4)+ POUT1

= (PMAX - P2)/

R0x3082[3:2]

P1

P2

R0x3082[5:4]

PMAX

(R1*R2*4) + POUT2

4x

2¹¹

2048

2¹⁴

2944

3008

3040

4x

8x

2¹⁶

2¹⁷

2¹⁸

2¹⁷

2¹⁸

2¹⁹

2¹⁸

2¹⁹

2²⁰

3712

3840

3904

3776

3904

3968

3808

3936

4000

16x

4x

8x

2¹¹

2¹⁵

8x

16x

4x

16x

2¹¹

2¹⁶

8x

16x

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

High Dynamic Range Mode

HDR Specific Exposure Settings

In HDR mode, pixel values are stored in line buffers while waiting for all 3 exposures to

be available for final pixel data combination. There are 42 line buffers used to store inter-

mediate T1 data. Due to this limitation, the maximum coarse integration time possible is

equal to 42*T1/T2 lines.

For example, if R0x3082[3:2] = 2, the sensor is set to have T1/T2 ratio = 16x. Therefore the

maximum number of integration lines is 42*16 = 672 lines. If coarse integration time is

greater than this, the T2 integration time will stay at 42 lines. The sensor calculates the

ratio internally, enabling the linearization to be performed. If companding is being used

then relinearization would still follow the programmed ratio. For example, if the T1/T2

ratio was programmed to 16x but coarse integration was increased beyond 672 then one

would still use the 16x relinearization formulas.

An additional limitation is the maximum number of exposure lines in relation to the

frame_length_lines register. In Linear mode, as described on page 20, maximum

coarse_integration_time = frame_length_lines - 1. However in HDR mode, since the

coarse integration time register controls T1, the max coarse_integration time is

frame_length_lines - 45.

Putting the two criteria listed above together, it can be summarized as follows:

maximum coarse_integration_time = minimum42  T1  T2, frame_length_lines – 45

(EQ 3)

In HDR mode, subline integration is not utilized. As such, fine integration time register

changes will have no effect on the image.

There is also a limitation of the minimum number of exposure lines that can be used.

This is summarized in the following formula:



minimum coarse_integration_time = 0.5*T1  T2 T2  T3

(EQ 4)

Due to limitation on the internal floating point calculation, the exact ratio specified by

the RATIO_T2_T3 (R0x3082[5:4]) may not be achievable.

Motion Compensation

In typical multi-exposure HDR systems, motion artifacts can be created when objects

move during the T1, T2 or T3 integration time. When this happens, edge artifacts can

potentially be visible and might look like a ghosting effect.

To correct this feature, the AR0132AT has special 2D motion compensation circuitry that

detects motion artifacts and corrects the image accordingly.

There are two motion compensation options available. One using the default HDR

motion compensation feature can be enabled by setting R0x318C[14] = 1. Additional

parameters are available to control the extent of motion detection and correction as per

the requirements of the specific application. These can be set in R0x318C–R0x3190. The

other is using the DLO method of HDR combination. When using DLO, R0x318C[14] is

ignored. DLO is enabled by setting R0x3190[13] = 1. Noise filtering is enabled by setting

R0x3190[14] = 1. For more information, please refer to the AR0132AT Register Reference

document.

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Real-Time Context Switching

In the AR0132AT, the user may switch between two full register sets (listed in Table 9) by

writing to a context switch change bit in R0x30B0[13]. This context switch will change all

registers (no shadowing) at the frame start time and have the new values apply to the

immediate next exposure and readout time.

Table 9:

Real-Time Context-Switch Registers

Register Number

Register Description

Context A

Context B

Y_Addr_Start

R0x3002

R0x3004

R0x3006

R0x3008

R0x3012

R0x3014

R0x30A6

R0x30B0[5:4]

R0x3056

R0x3058

R0x305A

R0x305C

R0x305E

R0x300A

R0x3032[1:0]

0x3082

R0x308C

R0x308A

R0x3090

R0x308E

R0x3016

R0x3018

R0x30A8

R0x30B0[9:8]

R0x30BC

R0x30BE

R0x30C0

R0x30C2

R0x30C4

R0x30AA

R0x3032[5:4]

0x3084

X_Addr_Start

Y_Addr_End

X_Addr_End

Coarse_Integration_Time

Fine_Integration_Time

Y_Odd_Inc

Column Gain

Green1_Gain (GreenR)

Blue_Gain

Red_Gain

Green2_Gain (GreenB)

Global_Gain

Frame_Length_Lines

Digital_Binning

Operation_Mode_Ctrl

Features

See the AR0132AT Register Reference for additional details.

Reset

The AR0132AT may be reset by using RESET_BAR (active LOW) or the reset register.

Hard Reset of Logic

The RESET_BAR pin can be connected to an external RC circuit for simplicity. The

recommended RC circuit uses a 10k resistor and a 0.1F capacitor. The rise time for the

RC circuit is 1s maximum.

Soft Reset of Logic

Soft reset of logic is controlled by the R0x301A Reset register. Bit 0 is used to reset the

digital logic of the sensor while preserving the existing two-wire serial interface configu-

ration. Furthermore, by asserting the soft reset, the sensor aborts the current frame it is

processing and starts a new frame. This bit is a self-resetting bit and also returns to “0”

during two-wire serial interface reads.

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Features

Clocks

The AR0132AT requires one clock input (EXTCLK).

PLL-Generated Master Clock

The PLL contains a prescaler to divide the input clock applied on EXTCLK, a VCO to

multiply the prescaler output, and two divider stages to generate the output clock. The

clocking structure is shown in Figure 18. PLL control registers can be programmed to

generate desired master clock frequency.

Note:

The PLL control registers must be programmed while the sensor is in the software

Standby state. The effect of programming the PLL divisors while the sensor is in the

streaming state is undefined.

Figure 18: PLL-Generated Master Clock PLL Setup

PLL Input

Clock

PLL Output

Clock

SYSCLK

Pre PLL

Div

(PFD)

PLL

Multiplier

(VCO)

PLL Output

Div1

PLL Output

Div2

EXTCLK

PIXCLK

pll_multiplier

Pre_pll_clk_div

vt_sys_clk_div

vt_pix_clk_div

The PLL is enabled by default on the AR0132AT.

To configure and use the PLL:

1. Bring the AR0132AT up as normal; make sure that f_EXTCLKis between 6 and 50MHz and

ensure the sensor is in software standby (R0x301A-B[2]= 0). PLL control registers must

be set in software standby.

2. Set pll_multiplier, pre_pll_clk_div, vt_sys_clk_siv, and vt_pix_clk_div based on the

desired input (f

) and output (f_PIXCLK) frequencies. Determine the M, N, P1, and

EXTCLK

P2 values to achieve the desired f

using this formula:

PIXCLK

f

= (f

× M) / (N × P1 x P2)

EXTCLK

PIXCLK

where

M = PLL_Multiplier

N = Pre_PLL_Clk_Div

P1 = Vt_Sys_Clk_Div

P2 = Vt_PIX_Clk_Div

3. Wait 1ms to ensure that the VCO has locked.

4. Set R0x301A[2]=1 to enable streaming and to switch from EXTCLK to the PLL-gener-

ated clock.

Notes: 1. The PLL can be bypassed at any time (sensor will run directly off EXTCLK) by setting

R0x30B0[14]=1. However, only the parallel data interface is supported with the PLL

bypassed. The PLL is always bypassed in software standby mode. To disable the PLL,

the sensor must be in standby mode (R0x301A[2] = 0)

2. The following restrictions apply to the PLL tuning parameters:

32  M  255

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Features

1  N  63

P1 = 1 2 4 6 8 10 12 14 16

4  P2  16

3. The VCO frequency, defined as f_VCO= f_EXTCLK M  N must be within

384-768 MHz.

4. When PLL_Multiplier is odd, 2 MHz  f_EXTCLK/ N  24 MHz.

5. If using HiSPi output mode, use the following settings for P2 (Vt_Pix_Clk_Div).

5a. If 20-bit mode (4 lanes): set P2 (R0x302A) = 5

5b. If 12-/14-bit mode (3 lanes): set P2 (R0x302A) = 5

5c. If 12-bit mode (2 lanes): set P2 (R0x302A) = 6

5d. If 14-bit mode (2 lanes): set P2 (R0x302A) = 7

The user can utilize the Register Wizard tool accompanying DevWare to generate PLL

settings given a supplied input clock and desired output frequency.

Spread-Spectrum Clocking

To facilitate improved EMI performance, the external clock input allows for spread spec-

trum sources, with no impact on image quality. Limits of the spread spectrum input

clock are:

•

5% maximum clock modulation

35 KHz maximum modulation frequency

Accepts triangle wave modulation, as well as sine or modified triangle modulations.

Stream/Standby Control

The sensor supports two standby modes: Hard Standby and Soft Standby. In both

modes, external clock can be optionally disabled to further minimize power consump-

tion. If this is done, then the “Power-Up Sequence” on page 51 must be followed.

Soft Standby

Soft Standby is a low power state that is controlled through register R0x301A[2].

Depending on the value of R0x301A[4], the sensor will go to standby after completion of

the current frame readout (default behavior) or after the completion of the current row

readout. When the sensor comes back from Soft Standby, previously written register

settings are still maintained. Soft standby will not occur if the TRIGGER pin is held high.

A specific sequence needs to be followed to enter and exit from Soft Standby.

Entering Soft Standby:

1. R0x301A[12] = 1 if serial mode was used

2. Set R0x301A[2] = 0 and drive the TRIGGER pin LOW.

3. External clock can be turned off to further minimize power consumption (Optional)

Exiting Soft Standby:

1. Enable external clock if it was turned off

2. R0x301A[2] = 1 or drive the TRIGGER pin HIGH.

3. R0x301A[12] = 0 if serial mode is used

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Features

Hard Standby

Hard Standby puts the sensor in lower power state; previously written register settings

are still maintained.

A specific sequence needs to be followed to enter and exit from Hard Standby.

Entering Hard Standby:

1. R0x301A[8] = 1

2. R0x301A[12] = 1 if serial mode was used

3. Assert STANDBY pin

4. External clock can be turned off to further minimize power consumption (Optional)

Exiting Hard Standby:

1. Enable external clock if it was turned off

2. De-assert STANDBY pin

3. Set R0x301A[8] = 0

Window Control

Blanking Control

Registers x_addr_start, x_addr_end, y_addr_start, and y_addr_end control the size and

starting coordinates of the image window.

The exact window height and width out of the sensor is determined by the difference

between the Y address start and end registers or the X address start and end registers,

respectively.

The AR0132AT allows different window sizes for context A and context B.

Horizontal blank and vertical blank times are controlled by the line_length_pck and

frame_length_lines registers, respectively.

•

Horizontal blanking is specified in terms of pixel clocks. It is calculated by subtracting

the X window size from the line_length_pck register. The minimum horizontal

blanking is 370 pixel clocks.

•

Vertical blanking is specified in terms of numbers of lines. It is calculated by

subtracting the Y window size from the frame_length_lines register. The minimum

vertical blanking is 26 lines.

The actual imager timing can be calculated using Table 5 on page 17 and Table 6 on

page 18, which describe the Line Timing and FV/LV signals.

When in HDR mode, the maximum size is 1280 x 960.

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Features

Readout Modes

Digital Binning

By default, the resolution of the output image is the full width and height of the FOV as

defined above. The output resolution can be reduced by digital binning. For RGB and

monochrome mode, this is set by the register R0x3032. For Context A, use bits [1:0], for

Context B, use bits [5:4]. Available settings are:

0b00 = No binning

0b01 = Horizontal binning

0b10 = Horizontal and vertical binning

Binning gives the advantage of reducing noise at the cost of reduced resolution. When

both [horizontal and vertical binning are used, a 2x improvement in SNR is achieved,

therefore improving low light performance. Binning results in a smaller resolution

image, but the FOVs between binned and unbinned images are the same.

Bayer Space Resampling

All of the pixels in the FOV contribute to the output image in digital binning mode. This

can result in a more pleasing output image with reduced subsampling artifacts. It also

improves low-light performance. For RGB mode, resampling can be enabled by setting

of register 0x306E[4] = 1.

Mirror

Column Mirror Image

By setting R0x3040[14] = 1, the readout order of the columns is reversed, as shown in

Figure 19. The starting Bayer color pixel is maintained in this mode by a 1-pixel shift in

the imaging array.

When using horizontal mirror mode, the user must retrigger column correction. Please

refer to the column correction section to see the procedure for column correction retrig-

gering. Bayer resampling must be enabled, by setting R0x306E[4] = 1.

Figure 19: Eight Pixels in Normal and Column Mirror Readout Modes

LV

Normal readout

G0[11:0] R0[11:0] G1[11:0] R1[11:0] G2[11:0] R2[11:0]

D^OUT[11:0]

G3[11:0] R3[11:0]

G0[11:0] R0[11:0]

Reverse readout

G3[11:0] R3[11:0] G2[11:0] R2[11:0] G1[11:0] R1[11:0]

D^OUT[11:0]

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Features

Row Mirror Image

By setting R0x3040[15] = 1, the readout order of the rows is reversed as shown in

Figure 20. The starting Bayer color pixel is maintained in this mode by a 1-pixel shift in

the imaging array. When using horizontal mirror mode, the user must retrigger column

correction. Please refer to the column correction section to see the procedure for

column correction retriggering.

Figure 20: Six Rows in Normal and Row Mirror Readout Modes

FV

Normal readout

Row0 [11:0] Row1 [11:0] Row2 [11:0] Row3 [11:0] Row4 [11:0] Row5 [11:0]

Row5 [11:0] Row4 [11:0] Row3 [11:0] Row2 [11:0] Row1 [11:0] Row0 [11:0]

DOUT[11:0]

Reverse readout

OUT[11:0]

D

Maintaining a Constant Frame Rate

Maintaining a constant frame rate while continuing to have the ability to adjust certain

parameters is the desired scenario. This is not always possible, however, because register

updates are synchronized to the read pointer, and the shutter pointer for a frame is

usually active during the readout of the previous frame. Therefore, any register changes

that could affect the row time or the set of rows sampled causes the shutter pointer to

start over at the beginning of the next frame.

By default, the following register fields cause a “bubble” in the output rate (that is, the

vertical blank increases for one frame) if they are written in video mode, even if the new

value would not change the resulting frame rate. The following list shows only a few

examples of such registers; a full listing can be seen in the AR0132AT Register Reference.

•

x_addr_start

x_addr_end

y_addr_start

y_addr_end

frame_length_lines

line_length_pclk

coarse_integration_time

fine_integration_time

read_mode

The size of this bubble is (Integration_Time × t

to the new settings.

), calculating the row time according

ROW

The Coarse_Integration_Time and Fine_Integration_Time fields may be written to

without causing a bubble in the output rate under certain circumstances. Because the

shutter sequence for the next frame often is active during the output of the current

frame, this would not be possible without special provisions in the hardware. Writes to

these registers take effect two frames after the frame they are written, which allows the

integration time to increase without interrupting the output or producing a corrupt

frame (as long as the change in integration time does not affect the frame time).

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Features

Synchronizing Register Writes to Frame Boundaries

Changes to most register fields that affect the size or brightness of an image take effect

on two frames after the one during which they are written. These fields are noted as

“synchronized to frame boundaries” in the AR0132AT Register Reference. To ensure that

a register update takes effect on the next frame, the write operation must be completed

after the leading edge of FV and before the trailing edge of FV.

As a special case, in single frame mode, register writes that occur after FV but before the

next trigger will take effect immediately on the next frame, as if there had been a Restart.

However, if the trigger for the next frame occurs during FV, register writes take effect as

with video mode.

Fields not identified as being frame-synchronized are updated immediately after the

register write is completed. The effect of these registers on the next frame can be difficult

to predict if they affect the shutter pointer.

Restart

To restart the AR0132AT at any time during the operation of the sensor, write a “1” to the

Restart register (R0x301A[1] = 1). This has two effects: first, the current frame is inter-

rupted immediately. Second, any writes to frame-synchronized registers and the shutter

width registers take effect immediately, and a new frame starts (in video mode). The

current row completes before the new frame is started, so the time between issuing the

Restart and the beginning of the next frame can vary by about t

.

ROW

Image Acquisition Modes

The AR0132AT supports two image acquisition modes: video (master) and single frame.

Video

The video mode takes pictures by scanning the rows of the sensor twice. On the first

scan, each row is released from reset, starting the exposure. On the second scan, the row

is sampled, processed, and returned to the reset state. The exposure for any row is there-

fore the time between the first and second scans. Each row is exposed for the same dura-

tion, but at slightly different point in time, which can cause a shear in moving subjects as

is typical with electronic rolling shutter sensors.

Single Frame

The single-frame mode operates similar to the video mode. It also scans the rows of the

sensor twice, first to reset the rows and second to read the rows. Unlike video mode

where a continuous stream of images are output from the image sensor, the single-frame

mode outputs a single frame in response to a high state placed on the TRIGGER input

pin. As long as the TRIGGER pin is held in a high state, new images will be read out. After

the TRIGGER pin is returned to a low state, the image sensor will not output any new

images and will wait for the next high state on the TRIGGER pin.

The TRIGGER pin state is detected during the vertical blanking period (i.e. the FV signal

is low). The pin is level sensitive rather than edge sensitive. As such, image integration

will only begin when the sensor detects that the TRIGGER pin has been held high for 3

consecutive clock cycles. If the trigger signal is applied to multiple sensors at the same

time, the single frame output of the sensors will be synchronized to within 1 PIXCLK if is

PLL disabled or 2 PIXCLKs if PLL is enabled.

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Features

During integration time of single-frame mode and video mode, the FLASH output pin is

at high.

Continuous Trigger

In certain applications, multiple sensors need to have their video streams synchronized

(for example, surround view or panorama view applications). The TRIGGER pin can also

be used to synchronize output of multiple image sensors together and still get a video

stream. This is called continuous trigger mode. Continuous trigger is enabled by holding

the TRIGGER pin high. Alternatively, the TRIGGER pin can be held high until the stream

bit is enabled (R0x301A[2]=1) then can be released for continuous synchronized video

streaming.

If the TRIGGER pins for all connected AR0132AT sensors are connected to the same

control signal, all sensors will receive the trigger pulse at the same time. If they are

configured to have the same frame timing, then the usage of the TRIGGER pin guaran-

tees that all sensors will be synchronized within 1 PIXCLK cycle if PLL is disabled, or 2

PIXCLK cycles if PLL is enabled.

With continuous trigger mode, the application can now make use of the video streaming

mode while guaranteeing that all sensor outputs are synchronized. As long as the initial

trigger for the sensors takes place at the same time, all subsequent video streams will be

synchronous.

Temperature Sensor

The AR0132AT sensor has a built-in PTAT-based temperature sensor, accessible through

registers, that is capable of measuring die junction temperature.

The temperature sensor can be enabled by writing R0x30B4[0]=1 and R0x30B4[4]=1.

After this, the temperature sensor output value can be read from R0x30B2[10:0].

The value read out from the temperature sensor register is an ADC output value that

needs to be converted downstream to a final temperature value in degrees Celsius. Since

the PTAT device characteristic response is quite linear in the temperature range of oper-

ation required, a simple linear function in the format of listed in the equation below can

be used to convert the ADC output value to the final temperature in degrees Celsius.

Temperature = slope  R0x30B210:0 + T₀

(EQ 5)

For this conversion, a minimum of 2 known points are needed to construct the line

formula by identifying the slope and y-intercept "T ". These calibration values can be

0

read from registers R0x30C6 and R0x30C8 which correspond to value read at 70°C and

55°C respectively. Once read, the slope and y-intercept values can be calculated and

used in the above equation.

For more information on the temperature sensor registers, refer to the AR0132AT

Register Reference.

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Features

Automatic Exposure Control

The integrated automatic exposure control (AEC) is responsible for ensuring that

optimal settings of exposure and gain are computed and updated every other frame.

AEC can be enabled or disabled by R0x3100[0].

When AEC is disabled (R0x3100[0] = 0), the sensor uses the manual exposure value in

coarse and fine shutter width registers and the manual gain value in the gain registers.

When AEC is enabled (R0x3100[0]=1), the target luma value in linear mode is set by

R0x3102. For the AR0132AT this target luma has a default value of 0x0800 or about half

scale. For HDR mode, the luma target maximum auto exposure value is limited by

R0x311C; the minimum auto exposure is limited by R0x311E. These values are in units of

line-times.

The exposure control measures current scene luminosity by accumulating a histogram

of pixel values while reading out a frame. It then compares the current luminosity to the

desired output luminosity. Finally, the appropriate adjustments are made to the expo-

sure time and gain. All pixels are used, regardless of color or mono mode. In HDR mode,

the coarse and fine integration time is the longest integration time of the three integra-

tion, the other two shorter integration are generated automatically base on the pre-

defined exposure ratios.

Embedded Data and Statistics

The AR0132AT has the capability to output image data and statistics embedded within

the frame timing. There are two types of information embedded within the frame

readout:

1. Embedded Data: If enabled, these are displayed on the two rows immediately before

the first active pixel row is displayed.

2. Embedded Statistics: If enabled, these are displayed on the two rows immediately

after the last active pixel row is displayed.

Note:

One must have both embedded data and embedded statistics enabled or disabled

together.

Figure 21: Frame Format with Embedded Data Lines Enabled

Register Data

HBlank

Image

Status & Statistics Data

VBlank

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Features

Embedded Data

The embedded data contains the configuration of the image being displayed. This

includes all register settings used to capture the current frame. The registers embedded

in these rows are as follows:

Line 1: Registers R0x3000 to R0x312F

Line 2: Registers R0x3136 to R0x31BF, R0x31D0 to R0x31FF

All non-defined registers will have a value of 0.

Note:

In parallel mode, since the pixel word depth is 12-bits/pixel, the sensor 16-bit register

data will be transferred over 2 pixels where the register data will be broken up into 8 MSB

and 8 LSB. The alignment of the 8-bit data will be on the 8 MSB bits of the 12-bit pixel

word. For example, of a register value of 0x1234 is to be transmitted, it will be trans-

mitted over 2, 12-bit pixels as follows: 0x120, 0x340.

The first pixel of each line in the embedded data is a tag value of 0x0A0. This signifies

that all subsequent data is 8 bit data aligned to the MSB of the 12-bit pixel.

The figure below summarizes how the embedded data transmission looks like. It should

be noted that data, as shown in Figure 22, is aligned to the MSB of each word:

Figure 22: Format of Embedded Data Output within a Frame

{register_

address_MSB}

data_format_

code =8'h0A

{register_

address_LSB}

{register_

value_MSB}

8'hAA

8'h5A

8'hA5

8'h5A

Data line 1

{register_

value_LSB}

{register_

address_MSB}

{register_

address_LSB}

{register_

value_MSB}

data_format_

code =8'h0A

8'h5A

8'hA5

8'h5A

8'hAA

Data line 2

{register_

value_LSB}

The data embedded in these rows are as follows:

•

0x0A0 - identifier

0xAA0

Register Address MSB of the first register

0xA50

Register Address LSB of the first register

0x5A0

Register Value MSB of the first register addressed

0x5A0

Register Value LSB of the first register addressed

0x5A0

Register Value MSB of the register at first address + 2

0x5A0

Register Value LSB of the register at first address + 2

0x5A0

etc.

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Features

Embedded Statistics

The embedded statistics contain frame identifiers and histogram information of the

image in the frame. This can be used by downstream auto-exposure algorithm blocks to

make decisions about exposure adjustment.

This histogram is divided into 244 bins with a bin spacing of 64 evenly spaced bins for

12

16

digital code values 0 to 2 , 120 evenly spaced bins for values 2 to 2 , 60 evenly spaced

16

20

bins for values 2 to 2 . In HDR with a 16x exposure ratio, this approximately corre-

sponds to the T1, T2, T3 exposures respectively.

The first pixel of each line in the embedded statistics is a tag value of 0x0B0. This signi-

fies that all subsequent statistics data is 10 bit data aligned to the MSB of the 12-bit pixel.

The figure below summarizes how the embedded statistics transmission looks like. It

should be noted that data, as shown in Figure 23, is aligned to the msb of each word:

Figure 23: Format of Embedded Statistics Output within a Frame

data_format_

code =8'h0B

{2’b00, frame

_ID MSB}

histogram

bin0 [19:10]

histogram

bin0 [9:0]

{2’b00, frame

_count MSB}

#words =

10’h1EC

{2’b00, frame

_ID LSB}

{2’b00, frame

_count LSB}

stats line 1

histogram

bin1 [19:10]

histogram

bin243 [9:0]

histogram

bin1 [9:0]

histogram

bin243 [19:10]

8'h07

hist_end

[19:10]

hist_begin

[19:10]

#words =

10’h1C

hist_begin

[9:10]

hist_end

[9:10]

data_format_

code =8'h0B

mean [ 19:10]

mean [9:0]

stats line 2

lnorm_abs_dev

[9:0]

perc_lowEnd norm_abs_dev

[9:0] [19:10]

lowEndMean

[9:0]

perc_lowEnd

[19:10]

8'h07

lowEndMean

[19:10]

The statistics embedded in these rows are as follows:

Line 1:

•

0x0B0 - identifier

Register 0x303A - frame_count

Register 0x31D2 - frame ID

Histogram data - histogram bins 0-243

Line 2:

•

0x0B0 (identifier)

Mean

Histogram Begin

Histogram End

Low End Histogram Mean

Percentage of Pixels Below Low End Mean

Normal Absolute Deviation

Gain

Digital Gain

Digital gain can be controlled globally by R0x305E (Context A) or R0x30C4 (Context B).

There are also registers that allow individual control over each Bayer color

(GreenR(Green1_gain) by R0x3056, Blue_gain by R0x3058, Red_gain by R0x305A,

GreenB(Green2_gain) by R0x305C).

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Features

The format for digital gain setting is xxx.yyyyy where 0b00100000 represents a 1x gain

setting and 0b00110000 represents a 1.5x gain setting. The step size for yyyyy is 0.03125

while the step size for xxx is 1. Therefore to set a gain of 2.09375 one would set digital

gain to 01000011.

Analog Gain

The AR0132AT has a column parallel architecture and therefore has an Analog gain stage

per column.

There are two stages of analog gain, the first stage can be set to 1x, 2x, 4x or 8x. This is can

be set in R0x30B0[5:4](Context A) or R0x30B0[9:8] (Context B). The second stage is

capable of setting an additional 0.5X, 0.75X, 1X or 1.25x gain which can be set in

R0x3EE4[9:8]. 0.5X or 0.75X gain other than 1.0X or 1.25X gain will not affect device reli-

ability but could parts to deviate from ON Semiconductor's official specification.

This allows the maximum possible analog gain to be set to 10x.

Black Level Correction

Black level correction is handled automatically by the image sensor. No adjustments are

provided except to enable or disable this feature. Setting R0x30EA[15] disables the auto-

matic black level correction. Default setting is for automatic black level calibration to be

enabled.

The automatic black level correction measures the average value of pixels from a set of

optically black lines in the image sensor. The pixels are averaged as if they were light-

sensitive and passed through the appropriate gain. This line average is then digitally

low-pass filtered over many frames to remove temporal noise and random instabilities

associated with this measurement. The new filtered average is then compared to a

minimum acceptable level, low threshold, and a maximum acceptable level, high

threshold. If the average is lower than the minimum acceptable level, the offset correc-

tion value is increased by a predetermined amount. If it is above the maximum level, the

offset correction value is decreased by a predetermined amount. The high and low

thresholds have been calculated to avoid oscillation of the black level from below to

above the targeted black level.

Row-wise Noise Correction

Row (Line)-wise Noise Correction is handled automatically by the image sensor. No

adjustments are provided except to enable or disable this feature. Clearing R0x3044[10]

disables the row noise correction. Default setting is for row noise correction to be

enabled.

Row-wise noise correction is performed by calculating an average from a set of optically

black pixels at the start of each line and then applying each average to all the active

pixels of the line.

Column Correction

The AR0132AT uses column parallel readout architecture to achieve fast frame rate.

Without any corrections, the consequence of this architecture is that different column

signal paths have slightly different offsets that might show up on the final image as

structured fixed pattern noise.

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Features

The AR0132AT has column correction circuitry that measures this offset and removes it

from the image before output. This is done by sampling dark rows containing tied pixels

and measuring an offset coefficient per column to be corrected later in the signal path.

Column correction can be enabled/disabled via R0x30D4[15]. Additionally, the number

of rows used for this offset coefficient measurement is set in R0x30D4[3:0]. By default

this register is set to 0x7, which means that eight rows are used. This is the recom-

mended value. Other control features regarding column correction can be viewed in the

AR0132AT Register Reference. Any changes to column correction settings need to be

done when the sensor streaming is disabled and the appropriate triggering sequence

must be followed as described below.

Column Correction Triggering

Column correction requires a special procedure to trigger depending on which state the

sensor is in.

Column Correction Triggering on Startup

When streaming the sensor for the first time after power up, a special sequence needs to

be followed to make sure that the column correction coefficients are internally calcu-

lated properly.

1. Follow proper power up sequence for power supplies and clocks

2. Apply sequencer settings if needed (Linear or HDR mode)

3. Apply frame timing and PLL settings as required by application

4. Set analog gain to 1x and low conversion gain (R0x30B0=0x1300)

5. Enable column correction and settings (R0x30D4=0xE007)

6. Disable auto re-trigger for change in conversion gain or col_gain, and enable column

correction always. (R0x30BA = 0x0008).

7. Enable streaming (R0x301A[2] = 1) or drive the TRIGGER pin HIGH.

8. Wait 9 frames to settle. (First frame after coming up from standby is internally column

correction disabled.)

9. Disable streaming (R0x301A[2] = 0)

After this, the sensor has calculated the proper column correction coefficients and the

sensor is ready for streaming. Any other settings (including gain, integration time and

conversion gain etc.) can be done afterwards without affecting column correction.

Column Correction Retriggering due to Mode Change

Since column offsets are sensitive to changes in the analog signal path, such changes

require column correction circuitry to be retriggered for the new path. Examples of such

mode changes include: horizontal mirror, vertical mirror, changes to column correction

settings.

When such changes take place, the following sequence needs to take place:

1. Disable streaming (R0x301A[2]=0) or drive the TRIGGER pin LOW.

2. Enable streaming (R0x301A[2]=1) or drive the TRIGGER pin HIGH.

3. Wait 9 frames to settle.

Note:

The above steps are not needed if the sensor is being reset (soft or hard reset) upon

the mode change.

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Features

Defective Pixel Correction

Defective Pixel Correction is intended to compensate for defective pixels by replacing

their value with a value based on the surrounding pixels, making the defect less notice-

able to the human eye. The defect pixel correction feature supports up to 200 defects.

The locations of defective pixels are stored in a table on chip during the manufacturing

process; this table is accessible through the two-wire serial interface. There is no provi-

sion for later augmenting the defect table entries.

The DPC algorithm is one-dimensional, calculating the resulting averaged pixel value

based on nearby pixels within a row. The algorithm distinguishes between color and

monochrome parts; for color parts, the algorithm uses nearest neighbor in the same

color plane.

At high gain, long exposure, and high temperature conditions, the performance of this

function can degrade.

Test Patterns

The AR0132AT has the capability of injecting a number of test patterns into the top of the

datapath to debug the digital logic. With one of the test patterns activated, any of the

datapath functions can be enabled to exercise it in a deterministic fashion. Test patterns

are selected by Test_Pattern_Mode register (R0x3070). Only one of the test patterns can

be enabled at a given point in time by setting the Test_Pattern_Mode register according

to Table 10. When test patterns are enabled the active area will receive the value speci-

fied by the selected test pattern and the dark pixels will receive the value in Test_Pat-

tern_Green (R0x3074 and R0x3078) for green pixels, Test_Pattern_Blue (R0x3076) for

blue pixels, and Test_Pattern_Red (R0x3072) for red pixels.

Note:

Turn off black level calibration (BLC) by setting R0x30EA[15] = 1 when Test Pattern is

enabled.

Table 10:

Test Pattern Modes

Test_Pattern_Mode

Test Pattern Output

0d0

0d1

No test pattern (normal operation)

Solid color test pattern

0d2

100% color bar test pattern

0d3

Fade-to-gray color bar test pattern

Walking 1s test pattern (12-bit)

0d256

Color Field

When the color field mode is selected, the value for each pixel is determined by its color.

Green pixels will receive the value in Test_Pattern_Green, red pixels will receive the value

in Test_Pattern_Red, and blue pixels will receive the value in Test_Pattern_Blue.

Vertical Color Bars

Walking 1s

When the vertical color bars mode is selected, a typical color bar pattern will be sent

through the digital pipeline.

When the walking 1s mode is selected, a walking 1s pattern will be sent through the

digital pipeline. The first value in each row is 1.

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Two-Wire Serial Register Interface

The two-wire serial interface bus enables read/write access to control and status regis-

ters within the AR0132AT. The interface protocol uses a master/slave model in which a

master controls one or more slave devices. The sensor acts as a slave device. The master

generates a clock (SCLK) that is an input to the sensor and is used to synchronize trans-

fers. Data is transferred between the master and the slave on a bidirectional signal

(SDATA). SDATA is pulled up to VDD_IO off-chip by a 1.5k resistor. Either the slave or

master device can drive SDATA LOW—the interface protocol determines which device is

allowed to drive SDATA at any given time.

The protocols described in the two-wire serial interface specification allow the slave

device to drive SCLK LOW; the AR0132AT uses SCLK as an input only and therefore never

drives it LOW.

Protocol

Data transfers on the two-wire serial interface bus are performed by a sequence of low-

level protocol elements:

1. a (repeated) start condition

2. a slave address/data direction byte

3. an (a no) acknowledge bit

4. a message byte

5. a stop condition

The bus is idle when both SCLK and SDATA are HIGH. Control of the bus is initiated with a

start condition, and the bus is released with a stop condition. Only the master can

generate the start and stop conditions.

Start Condition

A start condition is defined as a HIGH-to-LOW transition on SDATA while SCLK is HIGH.

At the end of a transfer, the master can generate a start condition without previously

generating a stop condition; this is known as a “repeated start” or “restart” condition.

Stop Condition

Data Transfer

A stop condition is defined as a LOW-to-HIGH transition on SDATA while SCLK is HIGH.

Data is transferred serially, 8 bits at a time, with the MSB transmitted first. Each byte of

data is followed by an acknowledge bit or a no-acknowledge bit. This data transfer

mechanism is used for the slave address/data direction byte and for message bytes.

One data bit is transferred during each SCLK clock period. SDATA can change when SCLK

is LOW and must be stable while SCLK is HIGH.

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Two-Wire Serial Register Interface

Slave Address/Data Direction Byte

Bits [7:1] of this byte represent the device slave address and bit [0] indicates the data

transfer direction. A “0” in bit [0] indicates a WRITE, and a “1” indicates a READ. The

default slave addresses used by the AR0132AT are 0x20(write address) and0x21 (read

address) in accordance with the specification. Alternate slave addresses of 0x30 (write

address) and 0x31 (read address) can be selected by enabling and asserting the SADDR

input.

An alternate slave address can also be programmed through R0x31FC.

Message Byte

Message bytes are used for sending register addresses and register write data to the slave

device and for retrieving register read data.

Acknowledge Bit

Each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the

SCLK clock period following the data transfer. The transmitter (which is the master when

writing, or the slave when reading) releases SDATA. The receiver indicates an acknowl-

edge bit by driving SDATA LOW. As for data transfers, SDATA can change when SCLK is

LOW and must be stable while SCLK is HIGH.

No-Acknowledge Bit

The no-acknowledge bit is generated when the receiver does not drive SDATA LOW

during the SCLK clock period following a data transfer. A no-acknowledge bit is used to

terminate a read sequence.

Typical Sequence

A typical READ or WRITE sequence begins by the master generating a start condition on

the bus. After the start condition, the master sends the 8-bit slave address/data direction

byte. The last bit indicates whether the request is for a read or a write, where a “0” indi-

cates a write and a “1” indicates a read. If the address matches the address of the slave

device, the slave device acknowledges receipt of the address by generating an acknowl-

edge bit on the bus.

If the request was a WRITE, the master then transfers the 16-bit register address to which

the WRITE should take place. This transfer takes place as two 8-bit sequences and the

slave sends an acknowledge bit after each sequence to indicate that the byte has been

received. The master then transfers the data as an 8-bit sequence; the slave sends an

acknowledge bit at the end of the sequence. The master stops writing by generating a

(re)start or stop condition.

If the request was a READ, the master sends the 8-bit write slave address/data direction

byte and 16-bit register address, the same way as with a WRITE request. The master then

generates a (re)start condition and the 8-bit read slave address/data direction byte, and

clocks out the register data, eight bits at a time. The master generates an acknowledge

bit after each 8-bit transfer. The slave’s internal register address is automatically incre-

mented after every 8 bits are transferred. The data transfer is stopped when the master

sends a no-acknowledge bit.

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Two-Wire Serial Register Interface

Single READ from Random Location

This sequence (Figure 24) starts with a dummy WRITE to the 16-bit address that is to be

used for the READ. The master terminates the WRITE by generating a restart condition.

The master then sends the 8-bit read slave address/data direction byte and clocks out

one byte of register data. The master terminates the READ by generating a no-acknowl-

edge bit followed by a stop condition. Figure 24 shows how the internal register address

maintained by the AR0132AT is loaded and incremented as the sequence proceeds.

Figure 24: Single READ from Random Location

Previous Reg Address, N

Reg Address, M

M+1

P

S

Slave Address

0

A

Reg Address[15:8]

A

Reg Address[7:0]

A

Sr Slave Address 1 A

Read Data

A

S = start condition

P = stop condition

Sr = restart condition

A = acknowledge

slave to master

master to slave

A = no-acknowledge

Single READ from Current Location

This sequence (Figure 25) performs a read using the current value of the AR0132AT

internal register address. The master terminates the READ by generating a no-acknowl-

edge bit followed by a stop condition. The figure shows two independent READ

sequences.

Figure 25: Single READ from Current Location

Previous Reg Address, N

Reg Address, N+1

N+2

P

S

Slave Address

1

A

Read Data

A

P

S

Slave Address 1 A

Read Data

A

Sequential READ, Start from Random Location

This sequence (Figure 26) starts in the same way as the single READ from random loca-

tion (Figure 24). Instead of generating a no-acknowledge bit after the first byte of data

has been transferred, the master generates an acknowledge bit and continues to

perform byte READs until “L” bytes have been read.

Figure 26: Sequential READ, Start from Random Location

Previous Reg Address, N

Reg Address, M

M+1

S

Slave Address

0

Reg Address[15:8]

A

Reg Address[7:0]

Sr

A

Slave Address

Read Data

M+L

1 A

A

M+1

M+2

M+L-2

M+L-1

M+3

Read Data

A

P

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Two-Wire Serial Register Interface

Sequential READ, Start from Current Location

This sequence (Figure 27) starts in the same way as the single READ from current loca-

tion (Figure 25). Instead of generating a no-acknowledge bit after the first byte of data

has been transferred, the master generates an acknowledge bit and continues to

perform byte READs until “L” bytes have been read.

Figure 27: Sequential READ, Start from Current Location

Previous Reg Address, N

N+1

N+2

N+L-1

N+L

P

S

Slave Address 1 A

Read Data

A

Read Data

A

Read Data

A

Read Data

A

Single WRITE to Random Location

This sequence (Figure 28) begins with the master generating a start condition. The slave

address/data direction byte signals a WRITE and is followed by the HIGH then LOW

bytes of the register address that is to be written. The master follows this with the byte of

write data. The WRITE is terminated by the master generating a stop condition.

Figure 28: Single WRITE to Random Location

Previous Reg Address, N

Reg Address, M

Write Data

M+1

P

A

S

Slave Address

0

Reg Address[15:8]

Reg Address[7:0]

A

Sequential WRITE, Start at Random Location

This sequence (Figure 29) starts in the same way as the single WRITE to random location

(Figure 28). Instead of generating a no-acknowledge bit after the first byte of data has

been transferred, the master generates an acknowledge bit and continues to perform

byte WRITEs until “L” bytes have been written. The WRITE is terminated by the master

generating a stop condition.

Figure 29: Sequential WRITE, Start at Random Location

Previous Reg Address, N

Reg Address, M

Write Data

M+1

S

Slave Address

0

Reg Address[15:8]

A

Reg Address[7:0]

A

M+1

M+2

M+L-2

M+L-1

M+3

M+L

P

A

Write Data

A

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Spectral Characteristics

Figure 30: Quantum Efficiency – Color Sensor

70

60

50

40

30

20

10

0

green

blue

red

350

400

800

850 900

700 750

1000 1050

950

450 500 550 600

650

Wavelength (nm)

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Spectral Characteristics

Figure 31: Quantum Efficiency – Monochrome Sensor

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Electrical Specifications

Unless otherwise stated, the following specifications apply to the following conditions:

VDD = 1.8V – 0.10/+0.15; VDD_IO = VDD_PLL = VAA = VAA_PIX = 2.8V ± 0.3V;

VDD_SLVS = 0.4V – 0.1/+0.2; T = -30°C to +70°C; output load = 10pF;

A

frequency = 74.25 MHz; HiSPi off.

Two-Wire Serial Register Interface

The electrical characteristics of the two-wire serial register interface (SCLK, SDATA) are

shown in Figure 32 and Table 11.

Figure 32: Two-Wire Serial Bus Timing Parameters

S^DATA

t

f

t

SU;DAT

LOW

HD;STA

f

r

BUF

SCLK

t

HD;STA

SU;STA

SU;STO

t

HIGH

HD;DAT

P

S

Sr

Note:

Read sequence: For an 8-bit READ, read waveforms start after WRITE command and register

address are issued.

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Electrical Specifications

Table 11:

Parameter

Two-Wire Serial Bus Characteristics

f_EXTCLK= 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;

VDD_PLL = 2.8V; T_A= 25°C

Standard-Mode

Fast-Mode

Symbol

Min

Max

Min

Max

Unit

SCLK Clock Frequency

SCLK High

^fSCL

0

100

0

400

KHz

8*EXTCLK+

s

SCLK rise time

EXTCLK rise time

SCLK Low

6*EXTCLK+

SCLK rise time

6*EXTCLK+

SCLK rise time

s

Hold time (repeated) START condition

After this period, the first clock pulse

is generated

^tHD;STA

4.0

-

0.6

-

LOW period of the SCLK clock

HIGH period of the SCLK clock

^tLOW

^tHIGH

4.7

4.0

4.7

-

1.3

0.6

-

s

Set-up time for a repeated START

condition

^tSU;STA

Data hold time:

Data set-up time

^tHD;DAT

^tSU;DAT

^tr

0⁴

250

-

3.45⁵

-

0⁶

100⁶

20 + 0.1Cb⁷

0.9⁵

-

s

ns

Rise time of both SDATA and SCLK

signals

1000

300

Fall time of both SDATA and SCLK

signals

^tf

-

300

20 + 0.1Cb⁷

300

ns

Set-up time for STOP condition

^tSU;STO

^tBUF

4.0

4.7

-

0.6

1.3

-

s

Bus free time between a STOP and

START condition

Capacitive load for each bus line

Serial interface input pin capacitance

SDATA max load capacitance

SDATA pull-up resistor

Cb

CIN_SI

CLOAD_SD

RSD

-

400

3.3

30

-

400

3.3

30

pF

-

pF

1.5

4.7

1.5

4.7

K

Notes: 1. This table is based on I²C standard (v2.1 January 2000). Philips Semiconductor.

2. Two-wire control is I²C-compatible.

3. All values referred to V_IHmin= 0.9 VDD and V_ILmax= 0.1VDD levels. Sensor EXCLK = 27 MHz.

4. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the

undefined region of the falling edge of SCLK.

5. The maximum t_HD;DAThas only to be met if the device does not stretch the LOW period (t_LOW) of

the SCLK signal.

6. A Fast-mode I²C-bus device can be used in a Standard-mode I²C-bus system, but the requirement

t_SU;DAT250 ns must then be met. This will automatically be the case if the device does not stretch

the LOW period of the SCLK signal. If such a device does stretch the LOW period of the SCLK signal, it

must output the next data bit to the SDATA line t_Rmax + t_SU;DAT= 1000 + 250 = 1250 ns (according

to the Standard-mode I²C-bus specification) before the SCLK line is released.

7. Cb = total capacitance of one bus line in pF.

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Electrical Specifications

I/O Timing

By default, the AR0132AT launches pixel data, FV, and LV with the falling edge of PIXCLK.

The expectation is that the user captures DOUT[11:0], FV, and LV using the rising edge of

PIXCLK. This can be changed using register R0x3028.

See Figure 33 and Table 12 for I/O timing (AC) characteristics.

Figure 33: I/O Timing Diagram

t

RP

FP

t

R

F

90%

10%

90%

10%

t

EXTCLK

PIXCLK

t

PD

Pxl_0

Pxl_1

Pxl_2

Pxl_n

Data[11:0]

t

PLH

PFL

PLL

t

PFH

LINE_VALID/

FRAME_VALID

FRAME_VALID trails

LINE_VALID by 6 PIXCLKs.

FRAME_VALID leads LINE_VALID by 6 PIXCLKs.

1

Table 12:

I/O Timing Characteristics (2.8V VDD_IO)

Conditions: f_PIXCLK= 74.25 MHz (720P 60fps) VDD_IO = 2.8V;

Slew rate setting = 6 for PIXCLK; Slew rate setting = 7 for parallel ports

Symbol Definition

Condition

Min

Typ

Max

Unit

f_EXTCLKInput clock frequency

t_EXTCLKInput clock period

6

20

–

3

–

50

166

–

MHz

ns

t_R

Input clock rise time

Input clock fall time

Input clock jitter

ns

^tF

–

ns

t_JITTER

t_CP

–

600

13.7

ps

EXTCLK to PIXCLK propagation delay Nominal voltages, PLL Disabled,

PCLK slew rate=4

5.5

ns

t_RP

t_FP

Pixclk rise time

Pixclk fall time

Pixclk duty cycle

PCLK slew rate = 6

1.2

45

6

–

2.9

ns

50

–

55

%

f_PIXCLKPIXCLK frequency²

74.25

2.5

MHz

ns

t_PD

PIXCLK to data valid

PIXCLK to FV HIGH

PIXCLK to LV HIGH

PIXCLK to FV LOW

PIXCLK to LV LOW

PCLK slew rate = 6,

Parallel slew rate = 7

–2

–

t_PFH

t_PLH

t_PFL

t_PLL

PCLK slew rate = 6,

Parallel slew rate = 7

–2

–

2.5

ns

PCLK slew rate = 6,

Parallel slew rate = 7

PCLK slew rate = 6,

Parallel slew rate = 7

PCLK slew rate = 6,

Parallel slew rate = 7

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Electrical Specifications

Notes: 1. Minimum and maximum values are taken at the temperature and voltage limits; for instance,

105°C at 2.5V, and -40°C at 3.1V. All values are taken at the 50% transition point. The loading used

is 10pF.

2. Jitter from PIXCLK is already taken into account as the data of all the output parameters.

3. Input clock pad delay is not included in the total delay numbers for t_CP

.

1

Table 13:

Symbol

I/O Timing Characteristics (1.8V VDD_IO)

Conditions: f_PIXCLK= 74.25 MHz (720P 60fps) VDD_IO = 1.8V;

Slew rate setting = 6 for PIXCLK; Slew rate setting = 7 for parallel ports

Definition

Condition

Min

Typ

Max

Unit

f_EXTCLK

t_EXTCLK

t_R

Input clock frequency

Input clock period

Input clock rise time

Input clock fall time

Input clock jitter

6

20

-

50

166

-

MHz

ns

3

–

ns

t_F

-

ns

tJITTER

t_CP

–

600

15.3

ps

EXTCLK to PIXCLK propagation Nominal voltages, PLL Disabled,

6.2

ns

delay

PCLK slew rate=4

PCLK slew rate = 6

t_RP

t_FP

Pixel rise time

Pixel fall time

Pixel duty cycle

PIXCLK frequency²

PIXCLK to data valid

1.8

1.7

45

-

4.8

4.5

55

ns

50

%

f_PIXCLK

t_PD

6

74.25

2

MHz

ns

PCLK slew rate = 6,

–2.5

–

Parallel slew rate = 7

t_PFH

t_PLH

t_PFL

t_PLL

PIXCLK to FV HIGH

PIXCLK to LV HIGH

PIXCLK to FV LOW

PIXCLK to LV LOW

PCLK slew rate = 6,

Parallel slew rate = 7

–2.5

2

ns

PCLK slew rate = 6,

Parallel slew rate = 7

PCLK slew rate = 6,

Parallel slew rate = 7

PCLK slew rate = 6,

Parallel slew rate = 7

Notes: 1. Minimum and maximum values are taken at the temperature and voltage limits; for instance,

105°C TA at 1.7V, and -40°C TA at 1.95V. All values are taken at the 50% transition point. The loading

used is 10pF.

2. Jitter from PIXCLK is already taken into account as the data of all the output parameters.

3. Input clock pad delay is not included in the total delay numbers for t_CP.

1

Table 14:

I/O Rise Slew Rate (2.8V VDD_IO)

Parallel Slew Rate

(R0x306E[15:13])

Conditions

Min

Typ

Max

Units

7

6

5

4

3

2

1

0

Default

1.08

0.77

0.58

0.44

0.32

0.23

0.16

0.10

1.77

1.26

0.95

0.70

0.51

0.37

0.25

0.15

2.72

1.94

1.46

1.08

0.78

0.56

0.38

0.22

V/ns

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Electrical Specifications

Notes: 1. Minimum and maximum values are taken at the temperature and voltage limits; for instance,

105°C TA at 2.5V, and -40°C TA at 3.1V. The loading used is 20pF.

1

Table 15:

I/O Fall Slew Rate (2.8V VDD_IO)

Parallel Slew Rate

(R0x306E[15:13])

Conditions

Min

Typ

Max

Units

7

6

5

4

3

2

1

0

Default

1.00

0.76

0.60

0.46

0.35

0.25

0.17

0.11

1.62

1.24

0.98

0.75

0.56

0.40

0.27

0.16

2.41

1.88

1.50

1.16

0.86

0.61

0.41

0.24

V/ns

Notes: 1. Minimum and maximum values are taken at the temperature and voltage limits; for instance,

105°C TA at 2.5V, and -40°C TA at 3.1V. The loading used is 20pF.

1

Table 16:

I/O Rise Slew Rate (1.8V VDD_IO)

Min

Typ

Max

Units

Parallel Slew Rate

(R0x306E[15:13])

Conditions

7

6

5

4

3

2

1

0

Default

0.41

0.30

0.24

0.19

0.14

0.10

0.07

0.04

0.65

0.47

0.37

0.28

0.21

0.15

0.10

0.06

1.10

0.79

0.61

0.46

0.34

0.24

0.16

0.10

V/ns

Notes: 1. Minimum and maximum values are taken at the temperature and voltage limits; for instance,

105°C TA at 1.7V, and -40°C TA at 1.95V. The loading used is 20pF.

1

Table 17:

I/O Fall Slew Rate (1.8V VDD_IO)

Parallel Slew Rate

(R0x306E[15:13])

Conditions

Min

Typ

Max

Units

7

6

5

4

3

2

1

0

Default

0.42

0.32

0.26

0.20

0.16

0.12

0.08

0.05

0.68

0.51

0.41

0.32

0.24

0.18

0.12

0.07

1.11

0.84

0.67

0.52

0.39

0.28

0.19

0.11

V/ns

Notes: 1. Minimum and maximum values are taken at the temperature and voltage limits; for instance,

105°C TA at 1.7V, and -40°C TA at 1.95V. The loading used is 20pF.

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Electrical Specifications

DC Electrical Characteristics

The DC electrical characteristics are shown in the tables below.

Table 18:

Symbol

DC Electrical Characteristics

Definition

Condition

Min

Typ

Max

Unit

VDD

Core digital voltage

I/O digital voltage

Analog voltage

1.7

1.7/2.5

2.5

1.8

1.8/2.8

2.8

1.95

1.9/3.1

3.1

V

VDD_IO

VAA

VAA_PIX

VDD_PLL

Pixel supply voltage

PLL supply voltage

2.5

2.8

3.1

2.5

2.8

3.1

VDD_SLVS HiSPi supply voltage for SLVS mode

0.3

0.4

0.6

VDD_SLVS HiSPi supply voltage for HiVCM

mode

1.7

1.8

1.95

VIH

VIL

IIN

Input HIGH voltage

Input LOW voltage

Input leakage current

VDD_IO*0.7

–

VDD_IO*0.3

20

V

–

No pull-up resistor; VIN = VDD_IO or

DGND

A

VOH

VOL

IOH

IOL

Output HIGH voltage

Output LOW voltage

Output HIGH current

Output LOW current

VDD_IO-0.3

–

0.4

–

V

–

-22

–

V

At specified VOH

At specified VOL

mA

22

Note:

TA = -40 °C to 105 °C

Caution Stresses greater than those listed in Table 19 may cause permanent damage to the device.

This is a stress rating only, and functional operation of the device at these or any other con-

ditions above those indicated in the operational sections of this specification is not implied.

Table 19:

Symbol

Absolute Maximum Ratings

Parameter

Minimum

Maximum

Unit

Symbol

VSUPPLY

ISUPPLY

IGND

Power supply voltage (all supplies)

Total power supply current

Total ground current

–0.3

–

4.3

200

V

mA

V

VSUPPLY

ISUPPLY

IGND

–

200

VIN

DC input voltage

–0.3

–40

VDD_IO + 0.3

+150

VIN

VOUT

DC output voltage

V

VOUT

1

TSTG

Storage temperature

°C

TSTG

Notes: 1. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2. To keep dark current and shot noise artifacts from impacting image quality, keep operating tem-

perature at a minimum.

3. TA = -40 °C to 105 °C

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AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Electrical Specifications

Table 20:

Operating Current Consumption in Parallel Output and Linear Mode

Max

Definition

Condition

Symbol

IDD1

Min

–

Typ

63

35

30

10

7

Unit

mA

Digital operating current

Streaming, 1280x960 45fps

90

40

45

15

90

40

45

15

I/O digital operating current Streaming, 1280x960 45fps

IDD_IO

IAA

–

Analog operating current

Pixel supply current

Streaming, 1280x960 45fps

Streaming, 720p 60 fps

–

IAA_PIX

IDD_PLL

IDD1

–

PLL supply current

–

Digital operating current

–

63

35

30

10

7

I/O digital operating current Streaming, 720p 60 fps

IDD_IO

IAA

–

Analog operating current

Pixel supply current

PLL supply current

Streaming, 720p 60 fps

Streaming, 720p 60f ps

–

IAA_PIX

IDD_PLL

–

Notes: 1. Operating currents are measured at the following conditions:

VAA = VAA_PIX = VDD_IO = VDD_PLL = 2.8V

VDD =1.8V

PLL Enabled and PIXCLK = 74.25 MHz

T_A= 25°C

CLOAD = 10pF Measured in dark

Table 21:

Operating Current Consumption in Parallel Output and HDR Mode

Definition

Condition

Symbol

IDD

Min

–

Typ

95

35

65

15

7

Max

Unit

Digital operating current

I/O digital operating current

Analog operating current

Pixel supply current

Streaming, 1280x960 45fps

Streaming, 720p 60 fps

115

40

75

20

15

mA

IDD_IO

IAA

–

IAA_PIX

IDD_PLL

IDD

–

PLL supply current

–

Digital operating current

I/O digital operating current

Analog operating current

Pixel supply current

–

95

35

61

15

7

115

40

75

20

15

IDD_IO

IAA

–

IAA_PIX

IDD_PLL

–

PLL supply current

–

Notes: 1. Operating currents are measured at the following conditions:

VAA = VAA_PIX = VDD_IO = VDD_PLL = 2.8V

VDD = 1.8V

PLL Enabled and PIXCLK = 74.25 MHz

T_A= 25°C

CLOAD = 10pF Measured in dark

AR0132AT/D Rev. 9, 2/16 EN

48

AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Electrical Specifications

Table 22:

Operating Currents in HiSPi Output and Linear Mode

Definition

Condition

Symbol

Min

Typ

Max

Unit

Digital Operating Current

Streaming 1280x960 45fps

IDD

–

95

115

mA

I/O digital operating current Streaming 1280x960 45fps

IDD_IO

IAA

–

100

30

10

7

150

45

A

mA

Analog operating current

Pixel Supply Current

PLL Supply Current

Streaming 1280x960 45fps

IAA_PIX

IDD_PLL

IDD_SLVS

15

SLVS Supply Current

Current LoVCM Mode

8

15

Streaming 1280x960 45fps

Current HiVCM Mode

–

16

25

mA

Streaming 1280x960 45fps

Digital Operating Current

Streaming 720p 60 fps

IDD

IDD_IO

IAA

–

95

100

30

10

7

115

150

45

mA

A

I/O digital operating current Streaming 720p 60 fps

Analog operating current

Pixel Supply Current

PLL Supply Current

Streaming 720p 60 fps

mA

IAA_PIX

IDD_PLL

IDD_SLVS

15

SLVS Supply Current

Current LoVCM Mode

Streaming 720p 60 fps

8

15

Current HiVCM Mode

–

16

25

mA

Streaming 1280x960 60fps

Notes: 1. Operating currents are measured at the following conditions:

VAA = VAA_PIX = VDD_IO = VDD_PLL = 2.8V

VDD = 1.8V

VDD_SLVS = 0.4V (LoVCM)

VDD_SLVS = 1.8V (HiVCM)

PLL Enabled and PIXCLK = 74.25 MHz

T_A= 25°C

CLOAD = 10pF Measured in dark

AR0132AT/D Rev. 9, 2/16 EN

49

AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Electrical Specifications

Table 23:

Operating Current in HiSPi Output and HDR Mode

Definition

Condition

Symbol

Min

Typ

Max

Unit

Digital Operating Current

Streaming 1280x960 45 fps

IDD

IDD_IO

IAA

–

115

100

65

15

7

130

150

75

mA

A

mA

I/O digital operating current Streaming 1280x960 45 fps

Analog operating current

Pixel Supply Current

PLL Supply Current

Streaming 1280x960 45 fps

IAA_PIX

IDD_PLL

IDD_SLVS

20

15

SLVS Supply Current

Current LoVCM Mode

8

15

Streaming 1280x960 45 fps

Current HiVCM Mode

–

16

25

mA

Streaming 1280x960 45 fps

Digital Operating Current

Streaming 720p 60 fps

IDD

IDD_IO

IAA

–

115

100

65

15

7

130

150

75

mA

A

mA

I/O digital operating current Streaming 720p 60 fps

Analog operating current

Pixel Supply Current

PLL Supply Current

Streaming 720p 60 fps

IAA_PIX

IDD_PLL

IDD_SLVS

20

15

SLVS Supply Current

Current LoVCM Mode

Streaming 720p 60 fps

8

15

Current HiVCM Mode

–

16

25

mA

Streaming 1280x960 60fps

Notes: 1. Operating currents are measured at the following conditions:

VAA=VAA_PIX=VDD_IO=VDD_PLL=2.8V

VDD=1.8V

VDD_SLVS = 0.4V (LoVCM)

VDD_SLVS = 1.8V (HiVCM)

PLL Enabled and PIXCLK=74.25MHz

T_A= 25°C

CLOAD = 10pF Measured in dark

Table 24:

Definition

Standby Current Consumption

Condition

Symbol

Min

–

Typ

30

Max

100

2500

100

4

Unit

Hard standby (clock off) Analog, 2.8V

Digital, 1.8V

–

ì A

mA

ì A

mA

–

85

Hard standby (clock on)

Soft standby (clock off)

Soft standby (clock on)

Analog, 2.8V

Digital, 1.8V

Analog, 2.8V

Digital, 1.8V

Analog, 2.8V

Digital, 1.8V

–

30

–

1.55

85

–

100

2500

100

4

–

85

–

30

–

1.55

Notes: 1. Analog – VAA + VAA_PIX + VDD_PLL

2. Digital – VDD + VDD_IO + VDD_SLVS

AR0132AT/D Rev. 9, 2/16 EN

50

AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Power-On Reset and Standby Timing

Figure 34: Power Supply Rejection Ratio

70

60

50

40

30

20

10

0

1000

10000

100000

Frequency (Hz)

1000000

HiSPi Electrical Specifications

The ON Semiconductor AR0132AT sensor supports both SLVS and HiVCM HiSPi modes.

Please refer to the High-Speed Serial Pixel (HiSPi) Interface Physical Layer Specification

v2.00.00 for electrical definitions, specifications, and timing information. The VDD_SLVS

supply in this datasheet corresponds to VDD_TX in the HiSPi Physical Layer Specifica-

tion. Similarly, VDD is equivalent to VDD_HiSPi as referenced in the specification.

Power-On Reset and Standby Timing

Power-Up Sequence

The recommended power-up sequence for the AR0132AT is shown in Figure 35. The

available power supplies (VDD_IO, VDD, VDD_SLVS, VDD_PLL, VAA, VAA_PIX) must have

the separation specified below.

1. Turn on VDD_PLL power supply.

2. After 0–10s, turn on VAA and VAA_PIX power supply.

3. After 0–10s, turn on VDD_IO power supply.

4. After the last power supply is stable, enable EXTCLK.

5. Assert RESET_BAR for at least 1ms.

6. Wait 850000 EXTCLKs (for internal initialization into software standby).

7. Configure PLL, output, and image settings to desired values.

8. Wait 1ms for the PLL to lock.

9. Set streaming mode (R0x301A[2] = 1).

AR0132AT/D Rev. 9, 2/16 EN

51

AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Power-On Reset and Standby Timing

Figure 35: Power Up

t0

VDD_PLL (2.8)

V^AA_PIX

VAA (2.8)

t1

t2

V^DD_IO (1.8/2.8)

VDD (1.8)

t3

V^DD_SLVS (0.4)

EXTCLK

t4

RESET_BAR

tx

t5

t6

Internal

Initialization

Software

Standby

PLL Lock

Streaming

Hard Reset

Table 25:

Power-Up Sequence

Definition

Symbol

Minimum

Typical

Maximum

Unit

VDD_PLL to VAA/VAA_PIX³

VAA/VAA_PIX to VDD_IO

VDD_IO to VDD

t0

t1

t2

t3

tx

t4

t5

t6

0

10

30¹

–

s

ms

0

VDD to VDD_SLVS

Xtal settle time

0

–

1²

Hard Reset

ms

Internal Initialization

PLL Lock Time

850000

1

–

EXTCLKs

ms

–

Notes: 1. Xtal settling time is component-dependent, usually taking about 10 – 100 ms.

2. Hard reset time is the minimum time required after power rails are settled. In a circuit where Hard

reset is held down by RC circuit, then the RC time must include the all power rail settle time and

Xtal settle time.

3. It is critical that VDD_PLL is not powered up after the other power supplies. It must be powered

before or at least at the same time as the others. If the case happens that VDD_PLL is powered after

other supplies then the sensor may have functionality issues and will experience high current draw

on this supply.

4. TA = -40 °C to 105 °C

AR0132AT/D Rev. 9, 2/16 EN

52

AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Power-On Reset and Standby Timing

Power-Down Sequence

The recommended power-down sequence for the AR0132AT is shown in Figure 36. The

available power supplies (VDD_IO, VDD, VDD_SLVS, VDD_PLL, VAA, VAA_PIX) must have

the separation specified below. Power may be removed from all supplies simultaneously,

and a sudden loss of power on all rails does not cause damage or affect the lifetime of the

device.

1. Disable streaming if output is active by setting standby R0x301A[2] = 0

2. The soft standby state is reached after the current row or frame, depending on config-

uration, has ended.

3. Turn off VDD_SLVS.

4. Turn off VDD.

5. Turn off VDD_IO

6. Turn off VAA/VAA_PIX.

7. Turn off VDD_PLL.

Figure 36: Power Down

V^DD_SLVS (0.4)

t 0

VDD (1.8)

t1

VDD_IO (1.8/2.8)

t2

V^AA_PIX

V^AA(2.8)

t3

V^DD_PLL (2.8)

EXTCLK

t4

Power Down until next Power up cycle

Table 26:

Power-Down Sequence

Definition

Symbol

Minimum

Typical

Maximum

Unit

VDD_SLVS to VDD

VDD to VDD_IO

t0

t1

t2

t3

t4

0

–

s

ms

VDD_IO to VAA/VAA_PIX

VAA/VAA_PIX to VDD_PLL

PwrDn until Next PwrUp Time

0

100

Notes: 1. t4 is required between power down and next power up time; all decoupling caps from regulators

must be completely discharged.

2. TA = -40 °C to 105 °C

AR0132AT/D Rev. 9, 2/16 EN

53

AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Package Dimensions (Case 503AF)

IBGA63 9x9

CASE 503AF

ISSUE O

DATE 30 DEC 2014

AR0132AT/D Rev. 9, 2/16 EN

54

AR0132AT: 1/3-Inch CMOS Digital Image Sensor

Package Dimensions (Case 503AF)

ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the

rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/

Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its

products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including

without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications

and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey

any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,

or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.

Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and

distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such

unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

This literature is subject to all applicable copyright laws and is not for resale in any manner.

AR0132AT/D Rev. 9, 2/16 EN

55

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AR0132AT6C00XPEAD3 AR0132AT6C00XPEAD3-S215-GEVK AR0132AT6M00XPEA0-DPBR

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型号：	AR0132AT
厂家：	ONSEMI
描述：	1/3-Inch CMOS Digital Image Sensor
文件：	总56页 (文件大小：1648K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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