AS0140AT2C00XUSM0-DRBR-E

DATA SHEET

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Features

1/4-Inch CMOS Image Sensor

and Signal Processor

 3.0 mm Pixel with onsemi DR−Pix Technol-

ogy

 Superior Low−light Performance

 45 fps at 1.0 MP, 60 fps at 720p

 Linear or High Dynamic Range Video

 Color Processing Optimized for HDR Video

Operation

AS0140AT

General Description

The onsemi AS0140AT is a 1.0 MP format digital image sensor and

image sensor processor for automotive viewing applications. The

device includes full auto−functions support (AWB and AE) and

ALTM (Adaptive Local Tone Mapping) to enhance HDR video. The

AS0140AT implements a high−sensitivity 3.0 mm pixel with

DR−Pixt technology, and advanced noise reduction, to enable

excellent low−light performance. It can be operated in interlaced

(NTSC or PAL) or progressive modes, and captures images in either

linear or high dynamic range modes. The AS0140AT may be operated

in video (master) mode or in single frame trigger mode, providing

flexibility for multi−camera systems.

 Color and Gamma Correction

 Auto Exposure, Auto White Balance,

50/60 Hz Auto Flicker Detection and Avoid-

ance

 Adaptive Local Tone Mapping (ALTM)

 Programmable Spatial Transform Engine

(STE)

 Pre−rendered Graphical Overlay

 Two−wire Serial Programming Interface

(CCIS)

Table 1. KEY PERFORMANCE PARAMETERS

 Interface to Low−cost Flash or EEPROM

through SPI Bus (to Configure and Load

Patches, etc.)

 High−level Host Command Interface

 Standalone Operation Supported

 Up to 5 GPIO

 Support for External LED or Xenon Flash

 Fail−safe IO

 Multi−camera Synchronization Support

 Integrated Video Encoder for NTSC/PAL

with Overlay Capability and 10−bit I−DAC

 Temperature Sensor

Parameter

Optical Format

Pixel Size and Type

Active Pixels

Typical Value

1/4

3.0 mm  3.0 mm

1280 (H)  800 (V) (Entire Array)

720 (H)  487 (V)

720 (H)  576 (V)

6−30 MHz

NTSC Output

PAL Output

Input Clock Range

Frame Rate (Note 1)

Color Filter Array

Shutter Type

60 fps at 720p

RGB Bayer

Electronic Rolling Shutter

Output Interface

Analog Composite, up to 16−bit Parallel Digital

Applications

 Surround, Rear and Front View Cameras

Output

Output Data Formats

YUV422 8−bit,10−bit, and 10 to 12−bit Tone−

mapped Bayer

 Blind Spot/Side Mirror Replacement Cam-

eras

Maximum Output

Clock Frequency

Parallel clock up to 84 MHz

 Automotive Viewing/Processing Fusion

Cameras

Supply Voltage

VDDIO:

VDD:

2.8 V Nominal

1.8 V Nominal

2.8 V Nominal

VAA:

VDDA_DAC: 3.3 V Nominal

Power Consumption

(Typical)

506 mW (Linear Mode NTSC)

527 mW (HDR Mode NTSC)

Package

8.5 mm  8.5 mm 130−pin BGA

Temperature

Operating Temperature −40C to 105C

1. Maximum frame rates depend on output interface and data format

configuration used.

 Semiconductor Components Industries, LLC, 2017

1

Publication Order Number:

March, 2023 − Rev. 1

AS0140AT/D

AS0140AT

ORDERING INFORMATION

Table 2. ORDERABLE PART NUMBERS

Part Number

Description

Orderable Product Attribute Description

AS0140AT2C00XUSM0−DPBR

0 CRA, RGB iEBGA Dry Pack with Protective Film, Double Side BBAR Glass, Engineering

Sample

AS0140AT2C00XUSM0−DRBR

AS0140AT2C00XUSM0−TPBR

AS0140AT2C00XUSM0−TRBR

0 CRA, RGB iEBGA Dry Pack w/o Protective Film, Double Side BBAR Glass, Engineering Sam-

ple

0 CRA, RGB iEBGA Tape and Reel with Protective Film, Double Side BBAR Glass, Engineering

Sample

0 CRA, RGB iEBGA Tape and Reel w/o Protective Film, Double Side BBAR Glass, Engineering

Sample

AS0140AT2C00XUSMH3−GEVB

MARS1−AS0140AT2−GEVB

RGB Headboard

RGB MARS Board

Function Overview

Figure 1 shows the typical configuration of the

AS0140AT in a camera system. On the host side, a two−wire

serial interface is used to control the operation of the

AS0140AT, and image data is transferred using the analog

or parallel interface between the AS0140AT and the host.

1280  800 Active Array

NTCS/PAL

Analog Display

Image Processor

Color and Gamma Correction

Auto Exposure

Auto White Balance

Adaptive Local Tone Mapping

Host

Figure 1. AS0140AT Connectivity

System Interfaces

Table 3 provides pin descriptions for the AS0140AT.

Figure 2 shows typical AS0140AT device connections.

All power supply rails must be decoupled from ground

using capacitors as close as possible to the package.

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2

AS0140AT

Digital

Power

Analog

Power

DAC Analog

Power

Regulator

Output

Digital I/O

Power

SCLK²

SDATA²

SADDR

EXTCLK

TEST1²

SPI_CS_BAR

SPI_SCLK

SPI_SDO

SPI_SDI

TEST2²

TEST3³

FRAME_VALID

LINE_VALID

PIXCLK_OUT

DOUT[15:0]

DAC_POS

TEST[8:4]

DAC_NEG

DAC_REF

FRAME_SYNC

DGND

AGND

GPIO[5:1]

Digital I/O

Power

Analog

Power

DAC Analog

Power

Digital

Power

Regulator

Output

4

5

Notes:

1. This typical configuration shows only one scenario out of multiple possible variations for this device.

2. onsemi recommends a 1.5 kW resistor value for the two−wire serial interface R . However, greater values may be used

PULL−UP

for slower two−wire serial transmission speed.

3. onsemi recommends a 10 kW resistor value for TEST3 to avoid potential power−up issues.

4. onsemi recommends that 0.1 mF and 10 mF decoupling capacitors for each power supply are mounted as close as possible to

the pin. Actual values and numbers may vary depending on layout and design consideration.

5. The decoupling capacitors for the regulator input and output should have a value of 1.0 mF. The capacitors should be ceramic

and need to have X5R or X7R dielectric.

Figure 2. Typical Device Configuration

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3

AS0140AT

Table 3. PIN DESCRIPTION

Pin Number

Pin Name

Type

Description

CLOCK AND RESET

L9

F1

EXTCLK

STANDBY

Input

Master Input Clock

Standby Mode Control, Active HIGH

B10

RESET_BAR

Master reset signal, active LOW. This signal has an internal

pull up.

B8

L12

H11

FRAME_SYNC

TRIGGER_OUT

TRIGGER

Input

Output

Input

This signal is used to synchronize to external sources or

multiple cameras together. This signal should be connected

to GND if not used.

If utilizing trigger modes, TRIGGER_OUT should be con-

nected to the TRIGGER pin; otherwise, this signal should

be left unconnected.

If utilizing trigger modes, TRIGGER_OUT should be con-

nected to the TRIGGER pin; otherwise, this signal should

be connected to GND.

REGISTER INTERFACE

B3

C12

A7

SCLK

SDATA

SADDR

Input

I/O

SCLK: Two−wire Serial Interface Clock (Host Interface)

Two−wire Serial Interface Data (Host Interface)

Input

Selects device address for the two−wire slave serial inter-

face. When connected to GND the device ID is 0x90. When

wired to VDDIO, a device ID of 0xBA is selected.

SPI INTERFACE

J1

SPI_SCLK

SPI_SDI

Output

Input

Clock Output for Interfacing to an External SPI Flash or

EEPROM Memory

A8

Data in from SPI flash or EEPROM memory. When no SPI

device is fitted, this signal is used to determine whether the

AS0140AT should auto−configure:

0: Do not auto−configure; Two−wire interface will be used to

configure the device (host−config mode)

1: Auto−configure.

This signal has an internal pullup resistor.

A4

SPI_SDO

Output

Data Out to SPI Flash or EEPROM Memory

A5

SPI_CS_BAR

Chip Select Out to SPI Flash or EEPROM Memory

PIXEL DATA OUTPUT

H1

B4

FRAME_VALID

LINE_VALID

PIXCLK_OUT

DOUT0

Output

Frame Valid Output (Synchronous to PIXCLK_OUT)

Line Valid Output (Synchronous to PIXCLK_OUT)

Pixel Clock Output

B5

E2

Pixel Data Output (Synchronous to PIXCLK_OUT)

M10

L8

DOUT1

DOUT2

E12

L10

L3

DOUT3

DOUT4

DOUT5

D2

M9

D12

J2

DOUT6

DOUT7

DOUT8

DOUT9

H2

E1

DOUT10

DOUT11

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AS0140AT

Table 3. PIN DESCRIPTION (continued)

Pin Number

Pin Name

Type

Description

PIXEL DATA OUTPUT

C2

DOUT12

DOUT13

DOUT14

DOUT15

Output

Pixel Data Output (Synchronous to PIXCLK_OUT)

A10

G1

F12

COMPOSITE VIDEO OUTPUT

M3

L7

DAC_REF

DAC_POS

Output

External Reference Resistor for Video DAC

Positive video DAC output in differential mode. Video DAC

output in single−ended mode. This interface is enabled by

default using NTSC/PAL signaling.

For applications where composite video output is not re-

quired, the video DAC can be placed in a power−down state

under software control.

L6

DAC_NEG

Output

Negative Video DAC Output in Differential Mode

GPIO

G2

GPIO_1

GPIO_2

GPIO_3

GPIO_4

GPIO_5

I/O

General Purpose Digital I/O

C1

D1

F2

A3

POWER

E10, F10, G10, H12, J12

AGND

DGND

Supply

Analog Ground

Digital Ground

K2, D4, E4, F4, G4, H4, J4,

L4, D5, E5, F5, G5, H5, J5,

D6, E6, F6, G6, H6, J6, B7,

D7, E7, F7, G7, H7, J7, D8,

E8, F8, G8, H8, J8, B9, D9,

E9, F9, G9, H9, J9, G12

C10, D10, D11, E11

H10, J10, K10, K12

VDDIO

VAA

Supply

I/O Supply Power

Analog Power

Digital Power

E3, F3, G3, H3, J3, K3, M4,

M5, M7

VDD

M6

VDDA_DAC

LDO_OP

Supply

Output

Video DAC Analog Power

A6

Output from on Chip 1.8 to 1.2 V Regulator

TEST PINS

F11

TEST1

TEST2

TEST3

TEST4

TEST5

TEST6

TEST7

TEST8

NC

Input

Must be Pulled Up via 1.5 kW to V for Normal Operation

DD

G11

A12

B6

Must be Pulled Up via 1.5 kW to V for Normal Operation

DD

Recommended Pull Up to V

DD

Must be Tied to GND for Normal Operation

K11

L2

L11

M8

A1, B1, K1, L1, M1, A2, B2,

M2, L5, A9, A11, B11, C11,

J11, M11, B12, M12

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AS0140AT

Table 4. PACKAGE PINOUT

1

2

3

4

5

6

7

8

9

10

11

12

A

B

NC

GPIO_5

SPI_

SDO

SPI_CS_

BAR

LDO_OP

SADDR

SPI_SDI

NC

DOUT13

NC

TEST3

NC

SCLK

LINE_

VALID

PIXCLK_

OUT

TEST4

DGND

FRAME_

SYNC

DGND

RESET_

BAR

NC

C

D

E

F

GPIO_2

GPIO_3

DOUT12

DOUT6

DOUT0

GPIO_4

GPIO_1

DOUT10

VDDIO

AGND

VAA

NC

SDATA

DOUT8

DOUT3

DOUT15

DGND

VDDIO

TEST1

TEST2

TRIGGER

DOUT11

STANDBY

DOUT14

VDD

G

H

FRAME_

VALID

AGND

J

SPI_SCL

K

DOUT9

VDD

DGND

VAA

NC

AGND

K

L

NC

DGND

TEST6

VDD

VAA

TEST5

TEST7

VAA

DOUT5

DGND

VDD

NC

DAC_

NEG

DAC_

POS

DOUT2

TEST8

EXTCLK

DOUT7

DOUT4

TRIGGER_

OUT

M

NC

DAC_

REF

VDD

VDDA_

DAC

VDD

DOUT1

NC

On−Chip Regulator

Power−Up Sequence

The AS0140AT has an on−chip regulator, the output from

the regulator is 1.2 V.

Powering up the AS0140AT requires voltages to be

applied in a particular order, as seen in Figure 3. The timing

requirements are shown in Table 5. The AS0140AT includes

a power−on reset feature that initiates a reset upon power up

of the AS0140AT.

dv/dt

VDDIO

dv/dt

t1

t9

VAA

dv/dt

t2

t8

VDDA_DAC

dv/dt

t7

t6

t3

VDD

t4

EXTCLK

SCLK

t5

SDATA

Figure 3. Power−Up and Power−Down Sequence

Table 5. POWER−UP AND POWER−DOWN SIGNAL TIMING

Symbol

Parameter

Delay from VDDIO to VAA

Delay from VDDIO to VDDA_DAC

Min

0

Typ

−

Max

50

Unit

ms

t1

t2

0

−

50

ms

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AS0140AT

Table 5. POWER−UP AND POWER−DOWN SIGNAL TIMING (continued)

Symbol

Parameter

Delay from VDDIO to VDD

Min

Typ

−

Max

50

−

Unit

t3

t4

0

t3 + 1

100

t7

ms

EXTCLK Activation

−

ms

t5

First Serial Command

−

EXTCLK Cycles

t6

EXTCLK Cutoff

−

ms

t7

Delay from VDD to VDDIO

Delay from VDDA_DAC to VDDIO

Delay from VAA to VDDIO

Power Supply Ramp Time (Slew Rate)

0

−

50

0.1

t8

0

−

ms

t9

0

−

ms

dv/dt

−

V/ms

2. It is critical that VAA is not powered up after VDD. It must be powered before or at least at the same time. If the case happens that VAA is

powered after VDD then sensor may have functionality issues and will experience high current draw on this supply.

Reset

Table 6 shows the output states when the part is in various

states.

The AS0140AT has three types of reset available:

 A hard reset is issued by toggling the RESET_BAR

signal

 A soft reset is issued by writing commands through the

two−wire serial interface

 An internal power−on reset

Table 6. OUTPUT STATES

Hardware States

Firmware States

Soft Standby Streaming

(Clock Running) (Clock Running) (Clock Running) Input

Reset State

Default State

Hard Standby

Idle

Name

Notes

EXTCLK

(Clock Running

or Stopped)

(Clock Running)

(Clock Running

or Stopped)

RESET_BAR

SCLK

(Asserted)

N/A

(Negated)

N/A

(Negated)

Input

(Clock Running

or Stopped)

(Clock Running

or Stopped)

(Clock Running

or Stopped)

(Clock Running Input. Must always be driven to

or Stopped)

a valid logic level.

SDATA

High−impedance High−impedance High−impedance High−impedance

Input/Output. A valid logic level

should be established by pull−

up.

SADDR

FRAME_SYNC

STANDBY

N/A

Input. Must always be driven to

a valid logic level.

Input. Must always be driven to

a valid logic level.

N/A

(Negated)

(Asserted)

(Negated)

Input. Must always be driven to

a valid logic level.

SPI_SCLK

SPI_SDI

High−impedance

Driven, Logic 0

Output

Internal Pull−up

Input. Internal pull−up perma-

nently enabled.

Enabled

SPI_SDO

High−impedance

Driven, Logic 0

Driven, Logic 1

Varied

Driven, Logic 0

Driven, Logic 1

Driven if Used

Driven, Logic 0

Driven, Logic 1

Driven if Used

Output

SPI_CS_BAR

FV_OUT,

LV_OUT,

PIXCLK_OUT,

DOUT[15:0]

Driven if Used

Output. Default state dependent

of configuration.

DAC_POS

DAC_NEG

Varied

N/A

Varied

N/A

Driven if Used

N/A

Driven if Used

N/A

Driven if Used

N/A

Driven if Used

N/A

Output. Default state dependent

on configuration. Tie to ground if

VDAC not used.

DAC_REF

Output. Requires reference re-

sistor. Tie to ground if VDAC not

used.

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AS0140AT

Table 6. OUTPUT STATES (continued)

Hardware States

Firmware States

Reset State

Default State

Hard Standby

Soft Standby

Streaming

Idle

Name

Notes

GPIO[5:2]

High−impedance

Input, then

High−impedance

Driven if Used

Input/Output. After reset, these

pins are sampled as inputs as

part of auto−configuration.

GPIO1

High−impedance High−impedance High−impedance High−impedance High−impedance High−impedance

TRIGGER_OUT

N/A

Output. Tie to TRRIGER if used;

otherwise leave NC.

TRIGGER

TEST[3:1]

TEST[8:4]

Input. Tie to TRRIGER_OUT if

used; otherwise tie to ground.

Input. A valid logic level should

be established by pull−up.

Input. Must always be driven to

GND.

Hard Reset

The AS0140AT enters reset state when the external

RESET_BAR is asserted LOW, as shown in Figure 4. All

the output signals will be in High−Z state.

t1

t4

t2

t3

EXTCLK

RESET_BAR

SDATA

All Outputs Data Active

Mode

Data Active

Reset

Internal Initialization Time

Enter Streaming Mode

Figure 4. Hard Reset Operation

Table 7. HARD RESET

Symbol

Parameter

Min

50

Typ

−

Max

−

Unit

t1

t2

t3

t4

RESET_BAR Pulse Width

EXTCLK Cycles

Active EXTCLK Required after RESET_BAR Asserted

10

−

Active EXTCLK Required before RESET_BAR De−asserted

First Two−wire Serial Interface Communication after RESET is HIGH

10

−

100

−

Soft Reset

A soft reset sequence to the AS0140AT can be activated

by writing to a register through a two−wire serial interface.

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8

AS0140AT

Hard Standby Mode

Exiting Standby Mode

The AS0140AT can enter hard standby mode by using

external STANDBY signal, as shown in Figure 5.

 De−assert STANDBY signal LOW.

Entering Standby Mode

 Assert STANDBY signal HIGH.

t1

t2

t3

EXTCLK

STANDBY

Mode

STANDBY Asserted

EXTCLK Disabled

EXTCLK Enabled

Figure 5. Hard Standby Operation

Table 8. HARD STANDBY SIGNAL TIMING

Symbol

Parameter

Min

−

Typ

−

Max

Unit

t1

t2

t3

Standby Entry Complete

2 Frames

Lines

Active EXTCLK Required after Going into STANDBY Mode

10

−

EXTCLKs

Active EXTCLK Required before STANDBY De−asserted

−

Multi−Camera Synchronization Support

The AS0140AT supports multi−camera synchronization

through the FRAME_SYNC pin.

The behavior will be different depending if the user is

using interlaced or progressive mode.

When using the interlaced modes, on the rising edge of

FRAME_SYNC this will cause the output to stop the current

frame (A) and during B the image output will be

indeterminate. On the falling edge of FRAME_SYNC this

will cause the re−synchronization to begin, this will continue

for a period (C), during C black fields will be output. The

resynchronized interlaced signal will be available at D.

During C if the user toggles the FRAME_SYNC input the

AS0140AT will ignore it, the user cannot re−synchronize

again until at D.

FRAME_SYNC

CVBS Output

A

B

C

D

(NTSC/PAL)

Figure 6. Frame Sync Behavior with Interlaced Mode

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AS0140AT

When using progressive mode, the host (or controlling

The AS0140AT supports two different trigger modes

when using progressive output. The first mode supported is

‘single−shot’; this is when the trigger pulse will cause one

frame to be output from the AS0140AT (see Figure 7).

entity) ‘broadcasts’ a sync−pulse to all cameras within the

system that triggers capture. The AS0140AT will propagate

the signal to the TRIGGER_OUT pin, and subsequently to

the attached sensor’s TRIGGER pin.

FRAME_SYNC

TRIGGER_OUT

FV_OUT

Figure 7. Single−Shot Mode

The second mode supported is called ‘continuous’, this is

when a trigger pulse will cause the part to continuously

output frames, see Figure 8. This mode would be especially

useful for applications which have multiple sensors and

need to have their video streams synchronized (for example,

surround view or panoramic view applications).

FRAME_SYNC

TRIGGER_OUT

FV_OUT

NOTE: This diagram is not to scale.

Figure 8. Continuous Mode

When two or more cameras have a signal applied to the

FRAME_SYNC input at the same time, the respective

FRAME_VALID signals would be synchronized within 5

PIXCLK_OUT cycles. This assumes that all cameras have

the same configuration settings and that the exposure time

is the same.

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AS0140AT

Image Flow Processor

parameters. For normal operation of the AS0140AT, streams

of raw image data are fed into the color pipeline. The user

also has the option to select a number of test patterns to be

input instead of sensor data. The IFP is broken down into

different sections, as outlined in Figure 9.

Image and color processing in the AS0140AT is

implemented as an image flow processor (IFP) coded in

hardware logic. During normal operation, the embedded

microcontroller will automatically adjust the operating

NTSC/PAL

Encode

DAC

Scaler

YUV

Filters

Color

Kill

Overlay

RGB2YUV

Interlace

Gamma

Crop

STE

Aperture

Correction

Color

Correction

Color

Interpolation

ALTM

Black Level

Subtraction

Digital Gain

Control

PGA

Defect Cor-

rection

Noise Re-

duction

RX

Decom

Panding

Linear or Companded Data

Figure 9. AS0140AT IFP

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AS0140AT

Test Patterns

and issue a Change−Config request; to exit this mode, set

R0xC88F to 0x00, and issue a Change−Config request.

NTSC and PAL test patterns can only be selected when the

device is configured for interlaced operation.

The AS0140AT has a number of test patterns that are

available when using the progressive NTSC and PAL

modes. The test patterns can be selected by programming

variables. To enter test pattern mode, set R0xC88F to 0x02

Progressive Test Patterns:

Figure 10. Progressive Test Patterns

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AS0140AT

NTSC Test Patterns:

Figure 11. NTSC Test Patterns

PAL Test Patterns:

Figure 12. PAL Test Patterns

Each NTSC/PAL test pattern consists of seven or eight

color bars (white, yellow, cyan, green, magenta, red, blue

and optionally black). The Y, Cb and Cr values for each bar

are detailed in Table 9.

For the NTSC SMPTE test pattern it is also required to

generate −I, +Q, −4 black and +4 black.

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AS0140AT

Table 9. NTSC/PAL TEST PATTERN VALUES

Nominal

Range

White

100%

White

75%

Yellow

162

44

Cyan

131

156

44

Green

112

72

Magenta

84

Red

65

Blue

35

Black

16

−I

16

−Q

16

−4 Black

7

+4 Black

25

Y

16 to 235

235

128

180

128

Cb 16 to 240

Cr 16 to 240

184

100

212

114

128

156

97

171

148

128

142

58

198

128

Figure 13. Test Pattern

Defect Correction

Positional Gain Adjustments

Image stream processing commences with the defect

correction function immediately after data decompanding.

To obtain defect free images, the pixels marked defective

during sensor readout and the pixels determined defective

by the defect correction algorithms are replaced with values

derived from the non−defective neighboring pixels. This

image processing technique is called defect correction.

Lenses tend to produce images whose brightness is

significantly attenuated near the edges. There are also other

factors causing fixed pattern signal gradients in images

captured by image sensors. The cumulative result of all these

factors is known as image shading. The AS0140AT has an

embedded shading correction module that can be

programmed to counter the shading effects on each

individual R, Gb, Gr, and B color signal.

AdaCD (Adaptive Color Difference)

Automotive applications require good performance in

extremely low light, even at high temperature conditions. In

these stringent conditions the image sensor is prone to higher

noise levels, and so efficient noise reduction techniques are

required to circumvent this sensor limitation and deliver

a high quality image to the user.

The Correction Function:

The correction functions can then be applied to each pixel

value to equalize the response across the image as follows:

P_corrected(row, col) + P_sensor(row, col) @ f (row, col)

(eq. 1)

where P are the pixel values and f is the color dependent

correction functions for each color channel.

Black Level Subtraction and Digital Gain

Adaptive Local Tone Mapping

After noise reduction, the pixel data goes through black

level subtraction and multiplication of all pixel values by

a programmable digital gain. Independent color channel

digital gain can be adjusted with registers. Black level

subtraction (to compensate for sensor data pedestal) is

a single value applied to all color channels. If the black level

subtraction produces a negative result for a particular pixel,

the value of this pixel is set to 0.

Real world scenes often have very high dynamic range

(HDR) that far exceeds the electrical dynamic range of the

imager. Dynamic range is defined as the luminance ratio

between the brightest and the darkest object in a scene. In

recent years many technologies have been developed to

capture the full dynamic range of real world scenes. For

example, the multiple exposure method is widely adopted

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AS0140AT

for capturing high dynamic range images, which combines

Color Correction and Aperture Correction

a series of low dynamic range images of the same scene

taken under different exposure times into a single HDR

image.

To achieve good color fidelity of the IFP output,

interpolated RGB values of all pixels are subjected to color

correction. The IFP multiplies each vector of three pixel

colors by a 3  3 color correction matrix. The three

components of the resulting color vector are all sums of three

10−bit numbers. The color correction matrix can be either

programmed by the user or automatically selected by the

auto white balance (AWB) algorithm implemented in the

IFP. Color correction should ideally produce output colors

that are corrected for the spectral sensitivity and color

crosstalk characteristics of the image sensor. The optimal

values of the color correction matrix elements depend on

those sensor characteristics and on the spectrum of light

incident on the sensor. The color correction variables can be

adjusted through register settings.

Traditionally this would have been derived from two sets

of CCM, one for Warm light like Tungsten and the other for

Daylight (the part would interpolate between the two

matrices). This is not an optimal solution for cameras used

in a Cool White Fluorescent (CWF) environment. A better

solution is to provide three CCMs, which would include

a matrix for CWF (interpolation now between three

matrices). The AS0140AT offers this feature which will give

the user improved color fidelity when under CWF type

lighting.

Even though the new digital imaging technology enables

the capture of the full dynamic range, low dynamic range

display devices are the limiting factor. Today’s typical LCD

monitor has contrast ratio around 1,000:1; however, it is not

typical for an HDR image (the contrast ratio for an HDR

image is around 250,000:1). Therefore, in order to

reproduce HDR images on a low dynamic range display

device, the captured high dynamic range must be

compressed to the available range of the display device. This

is commonly called tone mapping.

Tone mapping methods can be classified into global tone

mapping and local tone mapping. Global tone mapping

methods apply the same mapping function to all pixels.

While global tone mapping methods provide

computationally simple and easy to use solutions, they often

cause loss of contrast and detail. A local tone mapping is thus

necessary in addition to global tone mapping for the

reproduction of visually more appealing images that also

reveal scene details that are important for automotive safety

and surveillance applications. Local tone mapping methods

use a spatially variable mapping function determined by the

neighborhood of a pixel, which allows it to increase the local

contrast and the visibility of some details of the image. Local

methods usually yield more pleasing results because they

exploit the fact that human vision is more sensitive to local

contrast.

To increase image sharpness, a programmable 2D

aperture correction (sharpening filter) is applied to

color−corrected image data. The gain and threshold for 2D

correction can be defined through register settings.

onsemi’s ALTM solution significantly improves the

performance over global tone mapping. ALTM is directly

applied to the Bayer domain to compress the dynamic range

from 20−bit to 12−bit. This allows the regular color pipeline

to be used for HDR image rendering.

Gamma Correction

The gamma correction curve is implemented as

a piecewise linear function with 33 knee points, taking

12−bit arguments and mapping them to 10−bit output. The

abscissas of the knee points are fixed at 0, 8, 16, 24, 32, 40,

48, 56, 64, 80, 96, 112, 128, 160, 192, 224, 256, 320, 384,

448, 512, 640, 768, 896, 1024, 1280, 1536, 1792, 2048,

2560, 3072, 3584, and 4096. The 10−bit ordinates are

programmable through variables.

Color Interpolation

In the raw data stream fed by the external sensor to the IFP,

each pixel is represented by a 20− or 12−bit integer number,

which can be considered proportional to the pixel’s response

to a one−color light stimulus, red, green, or blue, depending

on the pixel’s position under the color filter array. Initial data

processing steps, up to and including ALTM, preserve the

one−color−per−pixel nature of the data stream, but after

ALTM it must be converted to a three−colors−per−pixel

stream appropriate for standard color processing. The

conversion is done by an edge−sensitive color interpolation

module. The module pads the incomplete color information

available for each pixel with information extracted from an

appropriate set of neighboring pixels. The algorithm used to

select this set and extract the information seeks the best

compromise between preserving edges and filtering out

high frequency noise in flat field areas. The edge threshold

can be set through register settings.

Color Kill

To remove high− or low−light color artifacts, a color kill

circuit is included. It affects only pixels whose luminance

exceeds a certain preprogrammed threshold. The U and V

values of those pixels are attenuated proportionally to the

difference between their luminance and the threshold.

YUV Color Filter

As an optional processing step, noise suppression by

one−dimensional low−pass filtering of Y and/or UV signals

is possible. A 3− or 5−tap filter can be selected for each

signal.

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15

AS0140AT

Camera Control and Auto Functions

Auto exposure is implemented by a firmware algorithm

that is running on the embedded microcontroller that

analyzes image statistics collected by the exposure

measurement engine, makes a decision, and programs the

sensor and color pipeline to achieve the desired exposure.

The measurement engine subdivides the image into 25

windows organized as a 5  5 grid.

Auto Exposure

The auto exposure algorithm optimizes scene exposure to

minimize clipping and saturation in critical areas of the

image. This is achieved by controlling exposure time and

analog gains of the external sensor as well as digital gains

applied to the image.

W 0,0

W 1,0

W 0,1

W 1,1

W 0,2

W 1,2

W 0,3

W 1,3

W 0,4

W 1,4

W 2,0

W 3,0

W 4,0

W 2,1

W 3,1

W 4,1

W 2,2

W 3,2

W 4,2

W 2,3

W 3,3

W 4,3

W 2,4

W 3,4

W 4,4

Figure 14. 5 y 5 Grid

AE Track Driver

displays the current AWB position in color temperature, the

range of which will be defined when programming the CCM

matrixes.

The region of interest can be controlled through the

combination of an inclusion window and an exclusion

window.

Other algorithm features include the rejection of fast

fluctuations in illumination (time averaging), control of

speed of response, and control of the sensitivity to small

changes. While the default settings are adequate in most

situations, the user can program target brightness,

measurement window, and other parameters described

above.

The driver changes AE parameters (integration time,

gains, and so on) to drive scene brightness to the

programmable target.

To avoid unwanted reaction of AE on small fluctuations

of scene brightness or momentary scene changes, the AE

track driver uses a temporal filter for luma and a threshold

around the AE luma target. The driver changes AE

parameters only if the filtered luma is larger than the AE

target step and pushes the luma beyond the threshold.

Exposure and White Balance Control

The Sensor Manager firmware component is responsible

for controlling the application of ‘exposure’ and ‘white

balance’ within the system. This effectively means that all

control of integration times and gains (whether for exposure

or white balance) is delegated to the Sensor Manager. The

Auto Exposure (AE) and Auto White Balance (AWB)

algorithms use services provided by the Sensor Manager to

apply exposure and/or white balance changes.

Dual Band IRCF

For some applications a day/night filter would be

switched in/out, this option is an additional cost to the

camera system. The AS0140AT supports the use of dual

band IRCF, which removes the need for the switching

day/night filter. Tuning support is provided for this usage

case. Refer to the AS0140AT developer guide for details.

Auto White Balance

The AS0140AT has a built−in AWB algorithm designed

to compensate for the effects of changing spectra of the

scene illumination on the quality of the color rendition. The

algorithm consists of two major parts: a measurement

engine performing statistical analysis of the image and

a driver performing the selection of the optimal color

correction matrix and IFP digital gain. While default

settings of these algorithms are adequate in most situations,

the user can reprogram base color correction matrices, place

limits on color channel gains, and control the speed of both

matrix and gain adjustments. The AS0140AT ATAWB

Exposure and White Balance Modes

The AS0140AT supports auto and manual exposure and

white balance modes. In addition, it will operate within

synchronized multi−camera systems. In this use case, one

camera within the system will be the ‘master’, and the others

‘slaves’. The master is used to calculate the appropriate

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16

AS0140AT

Flicker Avoidance

exposure and white balance. This is then applied to all slaves

concurrently under host control.

Flicker occurs when the integration time is not an integer

multiple of the period of the light intensity. The AS0140AT

can be programmed to avoid flicker for 50 or 60 Hz. For

integration times below the light intensity period (10 ms for

50 Hz environment), flicker cannot be avoided. The

AS0140AT supports an indoor AE mode, that will ensure

flicker−free operation.

Auto Mode

In Auto Exposure mode the AE algorithm is responsible

for calculating the appropriate exposure to keep the desired

scene brightness, and for applying the exposure to the

underlying hardware. In Auto White Balance mode the

AWB algorithm is responsible for calculating the color

temperature of the scene and applying the appropriate red

and blue gains to compensate.

Flicker Detection

The AS0140AT supports flicker detection, the algorithm

is designed only to detect a 50 Hz or 60 Hz flicker source.

Triggered Auto Mode

The Triggered Auto Exposure and Triggered Auto White

Balance modes are intended for the multi−camera use cases,

where a host is controlling the exposure and white balance

of a number of cameras. The idea is that one camera is in

triggered−auto mode (the master), and the others in

host−controlled mode (slaves). The master camera must

calculate the exposure and gains, the host then copies this to

the slaves, and all changes are then applied at the same time.

Output Formatting

The pixel output data in AS0140AT will be transmitted as

an 8/10 bit word over one or two clocks.

Uncompressed YCbCr Data Ordering

The AS0140AT supports swapping YCbCr mode, as

illustrated in Table 10.

Table 10. YCbCr OUTPUT DATA ORDERING

Manual Mode

Mode

Data Sequence

Cr

Manual mode is intended to allow simple manual

exposure and white balance control by the host. The host

needs to set the CAM_AET_EXPOSURE_TIME_MS,

Default (No Swap)

Swapped CrCb

Swapped YC

Cb

Y

i

Y

i

i+1

Cr

Y

i

Cb

i

i+1

CAM_AET_EXPOSURE_GAIN

and

CAM_AWB_

Y

i

Cbi

Cri

Y

i+1

Y

i+1

Cr

i

COLOR_TEMPERATURE controls, the camera will

calculate the appropriate integration times and gains.

Swapped CrCb, YC

Y

i

Cb

i

Host Controlled

The Host Controlled mode is intended to give the host full

control over exposure and gains.

The data ordering for the YCbCr output modes for

AS0140AT are shown in Table 11.

Table 11. YCbCr OUTPUT MODES (cam_port_parallel_msb_align=0x1)

Mode

Byte

Pixel i

Pixel i+1

Cr

Notes

YCbCr_422_8_8

Odd (DOUT[15:8])

Even (DOUT[15:8])

Odd (DOUT[15:6])

Even (DOUT[15:6])

Single (DOUT[15:0])

Cb

Data Range of 0−255 (Y = 16−235 and C = 16−240)

i

Y

i

Y

i+1

YCbCr_422_10_10

YCbCr_422_16

Cb

Cr

Data Range of 0−1023 (Y = 64−940 and C = 64−960)

Data Range of 0−255 (Y = 16−235 and C = 16−240)

i

Y

i

Y

i+1

Cb _Y

Cr _Y

i i+1

i

Table 12. YCbCr OUTPUT MODES (cam_port_parallel_msb_align=0x0)

Mode

Byte

Pixel i

Pixel i+1

Cr

Notes

YCbCr_422_8_8

Odd (DOUT[7:0])

Even (DOUT[7:0])

Odd (DOUT[9:0])

Even (DOUT[9:0])

Single (DOUT[15:0])

Cb

Data Range of 0−255 (Y = 16−235 and C = 16−240)

i

Y

i

Y

i+1

YCbCr_422_10_10

YCbCr_422_16

Cb

Cr

Data Range of 0−1023 (Y = 64−940 and C = 64−960)

Data Range of 0−255 (Y = 16−235 and C = 16−240)

i

Y

i

Y

i+1

Cb _Y

Cr _Y

i i+1

i

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17

AS0140AT

Pixel Clock

Frame Valid

Line Valid

Porch

0−255 Cycles

00

Data[7:0]

Cr

Y

Cb

Y

Cr

Y

Cb

Y

Cr

Y

Cb

Y

Cr

Y Cb Y Cr

Data[15:8]

HBlank

Image

HBlank

Image

HBlank

Pixel Clock

Frame Valid

Line Valid

Porch

0−255 Cycles

00

Data[7:0]

Cr

Y

Cb

Y

Cr

Y

Cb

Y

Cr

Y

Cb

Y

Cr

Y Cb Y Cr

Data[15:8]

HBlank

Image

HBlank

Image

HBlank

Active Video

Pixel Clock

Frame Valid

Line Valid

Porch

0−255 Cycles

00

Data[7:0]

Y

Cb Y Cr

Data[15:8]

Image

VBlank

Pixel Clock

Frame Valid

Line Valid

Porch

0−255 Cycles

00

Cr

Data[7:0]

Y

Cb Y Cr

Data[15:8]

VBlank

Image

Notes:

1. Cb Y Cr Y by default.

2. cam_port_parallel_msb_align=0x1

Figure 15. 8−bit YCrCr Output (YCbCr_422_8_8)

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18

AS0140AT

Pixel Clock

Frame Valid

Line Valid

Porch

0−255 Cycles

00

Data[5:0]

Cr

Y

Cb

Y

Cr

Y

Cb

Y

Cr

Y

Cb

Y

Cr

Y Cb Y Cr

Data[15:6]

HBlank

Image

HBlank

Image

HBlank

Pixel Clock

Frame Valid

Line Valid

Data[5:0]

Porch

0−255 Cycles

00

Cr

Y

Cb

Y

Cr

Y

Cb

Y

Cr

Y

Cb

Y

Cr

Y Cb Y Cr

Data[15:6]

HBlank

Image

HBlank

Image

HBlank

Active Video

Pixel Clock

Frame Valid

Line Valid

Data[5:0]

Porch

0−255 Cycles

00

Data[15:6]

Y

Cb Y Cr

Image

VBlank

Pixel Clock

Frame Valid

Line Valid

Data[5:0]

Porch

0−255 Cycles

00

Cr

Y

Cb Y Cr

Data[15:6]

VBlank

Image

Notes:

1. Cb Y Cr Y by default.

2. cam_port_parallel_msb_align=0x1

Figure 16. 10−bit YCrCr Output (YCbCr_422_10_10)

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19

AS0140AT

Pixel Clock

Frame Valid

Line Valid

Data[7:0]

Porch

0−255 Cycles

Y

Y Y Y Y

Cr

Cb Cr Cb Cr

Data[15:8]

HBlank

Image

HBlank

Image

HBlank

Pixel Clock

Frame Valid

Line Valid

Data[7:0]

Porch

0−255 Cycles

Y

Y Y Y Y

Cr

Data[15:8]

Cb Cr Cb Cr

HBlank

Image

HBlank

Image

HBlank

Active Video

Pixel Clock

Frame Valid

Line Valid

Data[7:0]

Porch

0−255 Cycles

Y

Y Y Y

Cb Cr CbCr

Data[15:8]

Image

VBlank

Pixel Clock

Frame Valid

Line Valid

Data[7:0]

Porch

0−255 Cycles

Y

Y Y Y

Cr

Data[15:8]

Cb Cr CbCr

Image

VBlank

Figure 17. 16−bit YCrCr Output (YCbCr_422_16)

Progressive STE can output any of the YCbCr modes in

Figures 15 to 17.

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20

AS0140AT

Pixel Clock

Frame Valid

Line Valid

Data[15:8]

00

80 10 80 10 80 10 80 10 FF 00 00 80 Cb

Y

Cr

Y

Cb

Y

Cr

Y

FF 00 00 9D 80 10 80 10

80 10 80 10 FF 00 00 80 Cb

Y

Cr

Y

Cb

Y

Cr

Y

FF 00 00 9D 80 10 80 10

Data[7:0]

Blanking

HBlank

SAV

Image

EAV

Blanking

SAV

Image

EAV

Blanking

HBlank

Cb

Y

Cr

Y

80 10

Pixel Clock

Frame Valid

Line Valid

Data[15:8]

00

80 10 80 10 80 10 80 10 FF 00 00 80 Cb

Y

Cr

Y

Cb

Y

Cr

Y

FF 00 00 B6 80 10 80 10

80 10 80 10 FF 00 00 A8 80 10 80 10

80 10 80 10 FF 00 00 B5 80 10 80 10

Data[7:0]

Blanking

HBlank

SAV

Image

EAV Blank

Blanking

SAV Blank

VBlank

EAV Blank

Blanking

HBlank

Field 1

Pixel Clock

Frame Valid

Line Valid

Data[15:8]

00

80 10

80 10 80 10 80 10 FF 00 00 C7 Cb

Y

Cr

Y

Cb

Y

Cr

Y

FF 00 00 DA 80 10 80 10

80 10 80 10 FF 00 00 C7 Cb

Y

Cr

Y

Cb

Y

Cr

Y

FF 00 00 DA 80 10 80 10

Data[7:0]

Blanking

HBlank

SAV

Image

EAV

Blanking

SAV

Image

EAV

Blanking

HBlank

Pixel Clock

Frame Valid

Line Valid

Data[15:8]

00

80 10 80 10 80 10 80 10 FF 00 00 C7 Cb

Y

Cr

Y

Cb

Y

Cr

Y

FF 00 00 F1 80 10 80 10

80 10 80 10 FF 00 00 EC 80 10 80 10

80 10 80 10 FF 00 00 F1 80 10 80 10

Data[7:0]

Blanking

HBlank

SAV

Image

EAV Blank

Blanking

SAV Blank

VBlank

EAV Blank

Blanking

HBlank

Field 2

Figure 18. Typical CCIR656 Output

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21

AS0140AT

Figure 19. Typical CVBS Output (NTSC/PAL)

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22

AS0140AT

Bayer Modes

Bayer output modes are only available in progressive

output mode before STE. The data ordering for the ALTM

Bayer output modes for AS0140AT are shown in Table 13.

Table 13. ALTM BAYER OUTPUT MODES

Mode

Byte

Single

D15

D14

D13

D12

0

D11

0

D10

0

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

ALTM_Bayer_10

ALTM_Bayer_12

0

D11

D10

Tables 13 and 14 show LSB aligned data; it is possible

using register setting to obtain MSB aligned data.

The data ordering for the Bayer output modes for

AS0140AT are shown in Table 14.

Table 14. BAYER OUTPUT MODES

Mode

Byte

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Notes

Bayer_12

Single

0

D11

D10

D8

D7

D6

D5

D4

D3

D2

D1

D0

RAW Bayer Data

Sensor Embedded Data

Barrel distortion is caused by a reduction in object

The AS0140AT is capable of passing sensor embedded

data in Bayer output mode only.

The AS0140AT Statistics are available through the serial

interface. Refer to the developer guide for details.

magnification the further away from the optical axis.

For the image to appear natural to the driver, the

AS0140AT corrects this barrel distortion and reprocesses

the image so that the resulting distortion is much smaller.

This is called distortion correction. Distortion correction is

the ability to digitally correct the lens barrel distortion and

to provide a natural view of objects. In addition, with barrel

distortion one can adjust the perspective view to enhance the

visibility by virtually elevating the point of viewing objects.

Spatial Transform Engine (STE)

A spatial transform is defined as a transform in which

some pixels are in different positions within the input and

output pictures. Examples include zoom, lens distortion

correction, turn, rotate, roaming and projection. STE is

a fully programmable engine which can perform spatial

transforms and eliminates the need for an expensive DSP for

image correction.

Perspective View

A backup camera has to be able to virtually adjust the

vertical perspective as if the camera were placed

immediately behind the vehicle pointed directly down, as

illustrated in Figure 20. The vertical perspective adjustment

may be employed temporarily to assist with parking

conditions, or it may be enabled permanently by loading

new parameters.

Lens Distortion Correction

Automotive backup cameras typically feature a wide

FOV lens so that a single camera mounted above the center

of the rear bumper can present the driver with a view of all

potential obstacles immediately behind the full width of the

vehicle. Lenses with a wide field of view typically exhibit at

least a noticeable amount of barrel distortion.

Perspective

Adjustment

Angle

Figure 20. Vertical Perspective Adjustment

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23

AS0140AT

Pan, Tilt, Zoom and Rotate

Using the STE it is possible to implement image

transforms like Pan, Tilt, Zoom, and Rotate.

Figure 21. Uncorrected Image

Figure 22. Zoomed

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24

AS0140AT

Figure 23. Zoom and Look Left

Figure 24. Zoom and Look Right

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25

AS0140AT

Multi−Panel

STE supports multi−panel views, these can be 2 or 3

panels. This feature is ideally suited for applications where

viewing at a junction is required.

Figure 25. Multi−Panel

Overlay Capability

 Blend factors may be changed dynamically to achieve

smooth transitions

Figure 26 highlights the graphical overlay data flow of the

AS0140AT. The images are separated to fit into 4 kB blocks

of memory after compression.

 Up to seven overlays may be blended simultaneously

 Overlay size up to 720  576 pixels rendered

The overlay engine is controlled through host commands

that allow a bitmap to be written piecemeal to memory

buffer through the two−wire serial interface, and through

a DMA channel direct from SPI Flash memory. Multiple

encoding passes may be required to fit an image into a 4 kB

block of memory; alternatively, the image can be divided

into two or more blocks to make the image fit. Every graphic

image may be positioned in an x/y direction and overlap with

other graphic images.

The host may load an image at any time. Under control of

DMA assist, data are transferred to the off−screen buffer in

compressed form. This assures that no display data are

corrupted during the replenishment of the seven active

overlay buffers.

 Selectable readout: rotating order is user programmable

 Dynamic movement through predefined overlay images

 Palette of 32 colors out of 16 million with 16 colors per

bitmap

 Each color has a YCbCr (8−8−8 bit) and 8 bits for the

Alpha value (Transparency).

 Each layer has a built in fader which when enabled

scales the Alpha value for each pixel.

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26

AS0140AT

Overlay Buffers: 4 kB Each

NVM

Decompress

Blend and Overlay

Bitmaps − Compressed

Off−screen

Buffer

Note: These images are not actually rendered,

but show conceptual objects and object blending.

Figure 26. Overlay Data Flow

Serial memory Partition

The contents of Flash/EEPROM memory partition locally

into three blocks (see Figure 27):

 Firmware extensions or software patches; in addition to

the on−chip firmware, extensions reside in this block of

memory

 Memory for overlay data and descriptors

These blocks are not necessarily contiguous.

 Memory for register settings, which may be loaded at

boot−up

Fixed−Size

Overlays − RLE

Fixed−Size

Overlays − RLE

Flash

Partitioning

12−byte Header

Overlay

Data

RLE Encoded

Data 4 kB

Lens Shading

Correction

Parameter

Alternate

Register Setting

Figure 27. Memory Partitioning

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27

AS0140AT

Overlay Adjustment

 The calibration statistics engine supports a windowed

8−bin luma histogram, either row−wise (vertical) or

column−wise (horizontal).

To ensure a correct position of the overlay to compensate

for assembly deviation, the overlay can be adjusted with

assistance from the calibration statistics engine:

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28

AS0140AT

 The example calibration statistics function of the

firmware can be used to perform an automatic

successive approximation search of a cross−hair target

within the scene.

 On the first frame, the firmware performs a coarse

horizontal search, followed by a coarse vertical search

in the second frame.

 In subsequent frames, the firmware reduces the

region−of−interest of the search to the histogram bins

containing the greatest accumulator values, thereby

refining the search.

 The resultant X, Y location of the cross−hair target can

be used to assign a calibration value of offset selected

overlay graphic image positions within the output

image.

 The calibration statistics also supports a manual mode,

which allows the host to access the raw accumulator

values directly.

Composite Video Output

The external pin GPIO[3] can be used to configure the

device for default NTSC or PAL operation. This and other

video configuration settings are available as register settings

accessible through the serial interface.

Single−Ended and Differential Composite Output

The composite output can be operated in a single−ended

or differential mode by simply changing the external resistor

configuration. For single−ended termination, see Figure 28.

The differential schematic is shown in Figure 29.

3.3 V

L2

L3

1.5 mH

VDDA_DAC

DAC_POS

Out

75 W

DAC_NEG

AS0140

37.5 W

DAC_REF

3.74 kW

GND

Gnd

Note: Only DAC Signals Shown.

Figure 28. Single−ended Termination

The DAC is differential, but it may be used to produce

single−ended signals provided that the unused (DAC_NEG)

performance of the DAC will be degraded. Termination

straight into ground causes all of the power dissipation to

occur on the chip, which is undesirable. If a one component

saving was absolutely critical, termination straight to

ground is a possibility.

output is terminated into

a resistance to ground

approximately equal to the load on the DAC_POS output.

Without this termination, the internal bias circuits will not be

kept in their proper operating regions and the dynamic

3.3 V

L2

L3

1.5 mH

VDDA_DAC

DAC_POS

Out p

75 W

DAC_NEG

AS0140

75 W

DAC_REF

3.74 kW

GND

L102

L103

Out n

1.5 mH

Note: Only DAC Signals Shown.

Figure 29. Differential Connection

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29

AS0140AT

If the user is not using the analog output then Figure 30

shows how the signals should be connected.

3.3 V

VDDA_DAC

DAC_POS

DAC_NEG

AS0140

GND

Note: Only DAC Signals Shown.

Figure 30. No DAC

Slave Two−Wire Serial Interface (CCIS)

Table 15. TWO−WIRE INTERFACE ID ADDRESS

The two−wire slave serial interface bus enables read/write

access to control and status registers within the AS0140AT.

The interface protocol uses a master/slave model in which

a master controls one or more slave devices. The sensor acts

as a slave device. The master generates a clock (SCLK) that

is an input to the sensor and used to synchronize transfers.

Data is transferred between the master and the slave on a

bidirectional signal (SDATA). SCLK and SDATA are pulled

up to VDDIO off−chip by a pull−up resistor of 1.5 kW or

greater.

SWITCHING

SADDR

Two−Wire Interface Address ID

0

1

0x90

0xBA

Start Condition

A start condition is defined as a HIGH−to−LOW

transition on SDATA while SCLK is HIGH.

At the end of a transfer, the master can generate a start

condition without previously generating a stop condition;

this is known as a “repeated start” or “restart” condition.

Protocol

Data transfers on the two−wire serial interface bus are

performed by a sequence of low−level protocol elements, as

follows:

Data Transfer

Data is transferred serially, 8 bits at a time, with the MSB

transmitted first. Each byte of data is followed by an

acknowledge bit or a no−acknowledge bit. This data transfer

mechanism is used for the slave address/data direction byte

and for message bytes. One data bit is transferred during

each SCLK clock period. SDATA can change when SCLK is

low and must be stable while SCLK is HIGH.

 A start or restart condition

 A slave address/data direction byte

 A 16−bit register address

 An acknowledge or a no−acknowledge bit

 Data bytes

 A stop condition

The bus is idle when both SCLK and SDATA are HIGH.

Control of the bus is initiated with a start condition, and the

bus is released with a stop condition. Only the master can

generate the start and stop conditions.

The SADDR pin is used to select between two different

addresses in case of conflict with another device. If SADDR

is LOW, the slave address is 0x90; if SADDR is HIGH, the

slave address is 0xBA. See Table x14 below. The user can

change the slave address by changing a register value.

Slave Address/Data Direction Byte

Bits [7:1] of this byte represent the device slave address

and bit [0] indicates the data transfer direction. A “0” in bit

[0] indicates a write, and a “1” indicates a read. The default

slave addresses used by the AS0140AT are 0x90 (write

address) and 0x91 (read address). Alternate slave addresses

of 0xBA (write address) and 0xBB (read address) can be

selected by asserting the SADDR input signal.

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30

AS0140AT

Message Byte

for a READ or a WRITE, where a “0” indicates a WRITE

and a “1” indicates a READ. If the address matches the

address of the slave device, the slave device acknowledges

receipt of the address by generating an acknowledge bit on

the bus.

Message bytes are used for sending register addresses and

register write data to the slave device and for retrieving

register read data. The protocol used is outside the scope of

the two−wire serial interface specification.

If the request was a WRITE, the master then transfers the

16−bit register address to which a WRITE will take place.

This transfer takes place as two 8−bit sequences and the

slave sends an acknowledge bit after each sequence to

indicate that the byte has been received. The master will then

transfer the 16−bit data, as two 8−bit sequences and the slave

sends an acknowledge bit after each sequence to indicate

that the byte has been received. The master stops writing by

generating a (re)start or stop condition. If the request was a

READ, the master sends the 8−bit write slave address/data

direction byte and 16−bit register address, just as in the write

request. The master then generates a (re)start condition and

the 8−bit read slave address/data direction byte, and clocks

out the register data, 8 bits at a time. The master generates

an acknowledge bit after each 8−bit transfer. The data

transfer is stopped when the master sends a no−acknowledge

bit.

Acknowledge Bit

Each 8−bit data transfer is followed by an acknowledge bit

or a no−acknowledge bit in the SCLK clock period following

the data transfer. The transmitter (which is the master when

writing, or the slave when reading) releases SDATA. The

receiver indicates an acknowledge bit by driving SDATA

LOW. As for data transfers, SDATA can change when SCLK

is LOW and must be stable while SCLK is HIGH.

No−Acknowledge Bit

The no−acknowledge bit is generated when the receiver

does not drive SDATA low during the SCLK clock period

following a data transfer. A no−acknowledge bit is used to

terminate a read sequence.

Stop Condition

A stop condition is defined as a LOW−to−HIGH transition

on SDATA while SCLK is HIGH.

Single READ from Random Location

Typical Operation

Figure 31 shows the typical READ cycle of the host to the

AS0140AT. The first two bytes sent by the host are an

internal 16−bit register address. The following 2−byte

READ cycle sends the contents of the registers to host.

A typical READ or WRITE sequence begins by the

master generating a start condition on the bus. After the start

condition, the master sends the 8−bit slave address/data

direction byte. The last bit indicates whether the request is

Previous Reg Address, N

Reg Address, M

M+1

P

Slave Ad-

dress

Reg

Address[7:0]

Slave Ad-

dress

Read Da-

1 A

Read

Data[7:0]

S

0 A

A

A Sr

A

Address[15:8]

ta[15:8]

S = Start Condition

P = Stop Condition

Sr = Restart Condition

A = Acknowledge

A = No−acknowledge

Slave to Master

Master to Slave

Figure 31. Single READ from Random Location

Single READ from Current Location

Figure 32 shows the single READ cycle without writing

the address. The internal address will use the previous

address value written to the register.

Previous Reg Address, N

Reg Address, N+1

N+2

Slave Ad-

dress

Read

Data[15:8]

Read

Data[7:0]

Slave Ad-

dress

Read

Data[15:8]

Read

Data[7:0]

S

1 A

A

A P

S

1 A

A

A P

Figure 32. Single READ from Current Location

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31

AS0140AT

Sequential READ, Start from Random Location

has been transferred, the master generates an acknowledge

bit and continues to perform byte READs until “L” bytes

have been read.

This sequence (Figure 33) starts in the same way as the

single READ from random location (Figure 31). Instead of

generating a no−acknowledge bit after the first byte of data

Previous Reg Address, N

Reg Address, M

M+1

S

Slave Address 0 A Reg Address[15:8]

A

Reg Address[7:0] A Sr Slave Address 1 A

Read Data

M+L

A

M+1

A

M+2

M+3

M+L−2

M+L−1

Read

Data[7:0]

Read

Data[15:8]

Read

A

P

Data[15:8]

Data[7:0]

Data[15:8]

Data[7:0]

Data[15:8]

Data[7:0]

Figure 33. Sequential READ from Random Location

Sequential READ, Start from Current Location

has been transferred, the master generates an acknowledge

bit and continues to perform byte reads until “L” bytes have

been read.

This sequence (Figure 34) starts in the same way as the

single READ from current location (Figure 32). Instead of

generating a no−acknowledge bit after the first byte of data

Previous Reg Address, N

N+1

N+2

N+L−1

N+L

P

Read

Data[15:8]

Read

Data[15:8]

Read

Data[15:8]

Read

S

Slave Address 1 A

A

Data[15:8]

Data[7:0]

Figure 34. Sequential READ, Start from Current Location

Single WRITE to Random Location

Figure 35 shows the typical WRITE cycle from the host

to the AS0140AT.The first 2 bytes indicate a 16−bit address

of the internal registers with most−significant byte first.

The following 2 bytes indicate the 16−bit data.

Previous Reg Address, N

Reg Address, M

Write Data

M+1

P

A

S

Slave Address

0 A

Reg Address[15:8]

A

Reg Address[7:0]

A

Figure 35. Single WRITE to Random Location

Sequential WRITE, Start at Random Location

has been transferred, the master generates an acknowledge

bit and continues to perform byte writes until “L” bytes have

been written. The WRITE is terminated by the master

generating a stop condition.

This sequence (Figure 36) starts in the same way as the

single WRITE to random location (Figure 33). Instead of

generating a no−acknowledge bit after the first byte of data

Previous Reg Address, N

Reg Address, M

Write Data A

M+1

S

Slave Address

M+1

0 A

Reg Address[15:8]

M+2

A

Reg Address[7:0]

A

M+3

M+L−2

M+L−1

M+L

P

Write

Data[7:0]

Write

Data[15:8]

Write

Data[7:0]

Write

Data[15:8]

Write

A

Data[15:8]

Data[7:0]

Figure 36. Sequential WRITE, Start at Random Location

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32

AS0140AT

Device Configuration

In the Flash−Config mode, the firmware interrogates the

device to determine if it contains valid configuration

records:

 If no records are detected, then the firmware enters the

Auto−Config mode.

 If records are detected, the firmware processes them.

By default, when all Flash records are processed the

firmware switches to the Host−Config mode. However,

the records encoded into the Flash can optionally be

used to instruct the firmware to proceed to auto−config,

or to start streaming (via a Change−Config).

In the Host−Config mode, the firmware performs no

configuration, and remains idle waiting for configuration

and commands from the host. The System Configuration

phase is effectively complete and the AS0140AT will take

no actions until the host issues commands.

After power is applied and the device is out of reset (either

the power on reset, hard or soft reset), it will enter a boot

sequence to configure its operating mode. There are

essentially three configuration modes: Flash/EEPROM−

Config, Auto−Config, and Host−Config.

The AS0140AT firmware supports

Configuration phase at start−up. This consists of three

sub−phases of execution:

a

System

Flash detection, then one of:

1. Flash−Config

2. Auto−Config

3. Host−Config

The System Configuration phase is entered immediately

following power−up or reset. Then the firmware performs

Flash Detection.

Flash Detection attempts to detect the presence of an SPI

Flash or EEPROM device:

The Auto−Config mode uses the GPIO [5..2] pins to

configure the operation of the device, such as video format

and pedestal (see Table 17). After Auto−Config completes

the firmware switches to the Change−Config mode.

 If no device is detected, the firmware then samples the

SPI_SDI pin state to determine

 The next mode:

Supported SPI Devices

 If SPI_SDI is low, then it enters the Host−Config

Table 16 lists supported EEPROM/Flash devices.

Devices not compatible will require a firmware patch.

Contact onsemi for additional support.

mode

 If SPI_SDI is high, then it enters the Auto−Config

mode

 If a device is detected, the firmware switches to the

Flash−Config mode.

Table 16. SPI FLASH DEVICES

Manufacturer

Device

AT26DF081A

AT25DF161

LE25FW806

M25P05A

M25P16

Type

Flash

Size

1 MB

2 MB

1 MB

64 kB

2 MB

512 B

256 B

128 B

128 kB

1 kB

Auto−detected

ManuID

0x1f4501

0x1f4602

0x622662

0x202010

0x202015

0x20ffff

Atmel

Yes

No

Atmel

Flash

Sanyo (Note 3)

Flash

ST

Flash

ST

Flash

ST

M95040

EEPROM

ST

M95020

No

0x20ffff

ST

M95010

No

0x20ffff

M95M01

No

0x20ffff

Microchip

M25AA080

M25LC080

No

0x29ffff

Microchip

1 kB

No

0x29ffff

3. Has been obsoleted.

Table 17. GPIO BIT DESCRIPTIONS IN AUTO−CONFIG

GPIO[5]

Normal

GPIO[4]

GPIO[3]

GPIO[2]

No Pedestal

Pedestal

Low (“0”)

High (“1”)

Normal

NTSC

PAL

Vertical Flip

Horizontal Mirror

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33

AS0140AT

Host Command Interface

executed by on chip firmware and the results are reported

back. EEPROM or Flash memory is also available to store

commands for later execution.

The AS0140AT has a mechanism to write higher level

commands, the Host Command Interface (HCI). Once

a command has been written through the HCI, it will be

Figure 37. Interface Structure

Command Flow

Synchronous Command Flow

The host issues a command by writing (through the two

wire interface) to the Command Register. All commands are

encoded with bit 15 set, which automatically generates the

‘host command’ (doorbell) interrupt to the microprocessor.

Assuming initial conditions, the host first writes the

command parameters (if any) to the Parameters Pool (in the

Command Handler’s shared−variable page), then writes the

command to Command Register. The firmware’s interrupt

handler is invoked, which immediately copies the

Command Register contents. The interrupt handler then

signals the Command Handler task to process the command.

If the host wishes to determine the outcome of the

command, it must poll the Command Register waiting for

the doorbell bit to become cleared. This indicates that the

firmware completed processing the command. The contents

of the Command Register indicate the command’s result

status. If the command generated response parameters, the

host can now retrieve these from the Parameters Pool.

The host must not write to the Parameters Pool, nor issue

another command, until the previous command completes.

This is true even if the host does not care about the result of

the previous command. It is strongly recommended that the

host tests that the doorbell bit is clear before issuing

a command.

The typical ‘flow’ for synchronous commands is:

1. The host issues a ‘request’ command to perform

an operation.

2. The registered command handler is invoked,

validates the command parameters, then performs

the operation. The handler returns the command

result status to indicate the result of the operation.

3. The host retrieves the command result value, and

any associated command response parameters.

Asynchronous Command Flow

The typical ‘flow’ for asynchronous commands is:

1. The host issues a ‘request’ command to start an

operation.

2. The registered command handler is invoked,

validates and copies the command parameters,

then signals a separate task to perform the

operation. The handler returns the ENOERR return

value to indicate the command was acceptable and

is in progress.

3. The host retrieves the command return value – if it

is not ENOERR the host knows that the command

was not accepted and is not in progress.

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34

AS0140AT

4. Subsequently, the host issues an appropriate ‘get

status’ command to both poll whether the

Start−Up Host Command Lock−Out

The AS0140AT firmware implements an internal Host

Command ‘lock’. At start−up, the firmware obtains this

lock, which prevents the Host from successfully issuing a

host command. All host commands will be rejected with

EBUSY until the lock is freed.

The firmware releases the Host Command lock when it

completes its start−up configuration processing. The time to

do this is dependent upon the configuration mechanism. It

is recommended that the Host poll the device with the

System Manager Get State command until ENOERR is

returned.

command has completed, and if so, retrieve any

associated response parameters.

5. The registered command handler is invoked,

determines the state of the command (via shared

variables with the processing task), and returns

either ‘EBUSY’ to indicate the command is still in

progress, or it returns the result status of the

command.

6. The host must re−issue the ‘get status’ command

until it does not receive the EBUSY response.

Asynchronous commands exist to allow the Host to issue

multiple commands to the various subsystems without

having to wait for each command to complete. This prevents

the host command interface from being blocked by

a long−running command. Therefore, each asynchronous

command has a “Get Status” (or similar) command to allow

the Host to determine when the asynchronous command

completes.

Once the host can send serial commands it should perform

the following sequence.

1. POLL command_register[15] until it clears

(This is called the doorbell bit).

2. Continuously issue the SYSMGR_GET_STATE

command (0x8101) until the result status is not

EBUSY.

Below is some pseudocode that a host could use to

implement the above sequence:

def systemWaitReadyFollowingReset(numRetries=10):

"""API function: waits for the system to be ready following reset (or powerup)

- first wait for the doorbell bit to clear - this indicates that the device can

accept host commands.

- then wait until the system has completed its configuration phase; the system is

ready when the SYSMGR_GET_STATE command does not return EBUSY.

- note the time for the system to be ready is dependent upon the active system

configuration mode.

- numRetries is the number of retries before timing-out

- returns result status code

"""

# Wait for doorbell bit to clear (indicates device can receive host commands)

retries = numRetries

while (0 != retries):

if (reg.COMMAND_REGISTER.DOORBELL.uncached_value == 0): break # ready to receive

commands retries -= 1

if (0 == retries):

# device failed to respond in time

return printError(ResultStatus.EIO, 'systemWaitReadyFollowingReset failed

(doorbell failed to clear)')

# Wait for the System Manager to complete the System Configuration phase

retries = numRetries

while (0 != retries):

res, currentState = sysmgrGetState()

if (ResultStatus.ENOERR == res): break # we're done

if (ResultStatus.EBUSY != res):

ꢀꢀreturn printError(res, 'systemWaitReadyFollowingReset failed

(sysmgrGetState failed)')

ꢀꢀretries -= 1

if (0 == retries):

# device failed to respond in time

return printError(ResultStatus.EAGAIN, 'systemWaitReadyFollowingReset failed

device busy)')

return res

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35

AS0140AT

Multitasking

Command Parameters

The AS0140AT firmware is multitasking; therefore note

that it is possible for an internally requested command to be

in−progress when the Host issues a command. In these

circumstances, the Host command is immediately rejected

with EBUSY. The Host should reissue the command after

a short interval.

Command parameters are written to the Parameters Pool

shared−variables by the host prior to invoking the command.

Similarly, any Command Response parameters are also

written back to the Parameters Pool by the firmware.

Result Status Codes

Table 18 shows the result status codes that are written by

the Command Handler to the Host Command register, in

response to a command.

Host Commands

Overview

The AS0140AT supports a number of functional modules

or processing subsystems. Each module or subsystem

exposes commands to the host to control and configure its

operation.

Table 18. RESULT STATUS CODES

Value

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

Mnemonic

ENOERR

ENOENT

EINTR

Typical Interpretation − Each Command may Re−interpret

No Error – Command was Successful

No Such Entity

Operation Interrupted

EIO

I/O Failure

E2BIG

Too Big

EBADF

Bad File/Handle

EAGAIN

ENOMEM

EACCES

EBUSY

Would−block, Try Again

Not Enough Memory/Resource

Permission Denied

Entity Busy, Cannot Support Operation

Entity Exists

EEXIST

ENODEV

EINVAL

Device Not Found

Invalid Argument

ENOSPC

ERANGE

ENOSYS

EALREADY

No Space/Resource to Complete

Parameter Out−of−Range

Operation Not Supported

Already Requested/Exists

NOTE: Any unrecognized host commands will be immediately rejected by the Command Handler, with result status code ENOSYS.

Summary of Host Commands

 Patch Loader

 Miscellaneous

 Calibration Stats

Tables 19 through 30 show summaries of the host

commands. The commands are divided into the following

sections:

Following is a summary of the Host Interface commands.

The description gives a quick orientation. The “Type”

column shows if it is an asynchronous or synchronous

command. For a complete list of all commands including

parameters, consult the Host Command Interface

Specification document.

 System Manager

 Overlay

 GPIO

 Flash Manager

 STE

 Sequencer

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AS0140AT

Table 19. SYSTEM MANAGER HOST COMMAND

System Manager Host Command

Set State

Value

0x8100

0x8101

0x8102

Type

Description

Asynchronous

Synchronous

Request the System Enter a New State

Get the Current State of the System

Configures the Power State of the System

Get State

Config Power Management

Table 20. OVERLAY HOST COMMANDS

Overlay Host Command

Enable Overlay

Get Overlay State

Set Calibration

Set Bitmap Property

Get Bitmap Property

Set String Property

Load Buffer

Value

Type

Description

Enable or Disable the Overlay Subsystem

Retrieves the State of the Overlay Subsystem

Set the Calibration Offset

0x8200

0x8201

0x8202

0x8203

0x8204

0x8205

0x8206

0x8207

0x8208

0x8209

0x820A

0x820B

0x820C

0x820D

0x820E

Synchronous

Asynchronous

Synchronous

Asynchronous

Set a Property of a Bitmap

Get a Property of a Bitmap

Set a Property of a Character String

Load an Overlay Buffer with a Bitmap (from Flash)

Retrieve Status of an Active Load Buffer Operation

Write Directly to an Overlay Buffer

Read Directly from an Overlay Buffer

Enable or Disable an Overlay Layer

Retrieve the Status of an Overlay Layer

Set the Character String

Load Status

Write Buffer

Read Buffer

Enable Layer

Get Layer Status

Set String

Get String

Get the Current Character String

Load String

Load a Character String (from Flash)

Table 21. STE MANAGER HOST COMMANDS

STE Manager Host Command

Value

Type

Description

Config

0x8310

Synchronous

Configure using the Default NTSC or PAL Configuration

Stored in ROM

Load Config

0x8311

Asynchronous

Load a Configuration from SPI NVM to the Configuration

Cache

Load Status

Write Config

0x8312

0x8313

Synchronous

Get Status of a Load Config Request

Write a Configuration (via CCIS) to the Configuration

Cache

Table 22. GPIO HOST COMMANDS

GPIO Host Command

Set GPIO Property

Value

0x8400

0x8401

0x8402

0x8403

0x8404

Type

Description

Set a Property of One or More GPIO Pins

Retrieve a Property of a GPIO Pin

Set the State of a GPO Pin or Pins

Get the State of a GPI Pin or Pins

Synchronous

Get GPIO Property

Set GPIO State

Get GPIO State

Set GPI Association

Associate a GPI Pin State with a Command Sequence

Stored in SPI NVM

Get GPI Association

0x8405

Synchronous

Retrieve a GPIO Pin Association

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AS0140AT

Table 23. FLASH MANAGER HOST COMMANDS

Flash Manager Host Command

Get Lock

Value

0x8500

0x8501

0x8502

0x8503

Type

Description

Asynchronous

Synchronous

Request the Flash Manager Access Lock

Retrieve the Status of the Access Lock Request

Release the Flash Manager Access Lock

Lock Status

Release Lock

Config

Configure the Flash Manager and Underlying SPI NVM

Subsystem

Read

Write

0x8504

0x8505

0x8506

0x8507

0x8508

0x8509

0x850A

Asynchronous

Synchronous

Read Data from the SPI NVM

Write Data to the SPI NVM

Erase Block

Erase Device

Query Device

Status

Erase a Block of Data from the SPI NVM

Erase the SPI NVM Device

Query Device−specific Information

Obtain Status of Current Asynchronous Operation

Configure the Attached SPI NVM Device

Config Device

Table 24. SEQUENCER HOST COMMANDS

Sequencer Host Command

Set GPIO Property

Refresh

Value

0x8400

0x8606

Type

Description

Synchronous

Asynchronous

Set a Property of One or More GPIO Pins

Refresh the Automatic Image Processing Algorithm Con-

figuration

Refresh Status

0x8607

Synchronous

Retrieve the Status of the Last Refresh Operation

Table 25. PATCH LOADER HOST COMMANDS

Patch Loader Host Command

Value

0x8700

0x8701

Type

Description

Load Patch

Status

Asynchronous

Synchronous

Load a Patch from SPI NVM and Automatically Apply

Get Status of an Active Load Patch or Apply Patch Re-

quest

Table 26. MISCELLANEOUS HOST COMMANDS

Miscellaneous Host Command

Invoke Command Seq

Value

0x8900

0x8901

0x8902

Type

Description

Synchronous

Invoke a Sequence of Commands Stored in SPI NVM

Configures the Command Sequence Processor

Wait for a System Event to be Signalled

Config Command Seq Processor

Wait for Event

Table 27. CALIBRATION STATS HOST COMMANDS

Calibration Stats Host Command

Calib Stats Control

Value

0x8B00

0x8B01

Type

Description

Start Statistics Gathering

Read the Results Back

Asynchronous

Synchronous

Calib Stats Read

Table 28. EVENT MONITOR HOST COMMANDS

Event Monitor Host Command

Value

Type

Description

Event Monitor Set Association

0x8C00

Synchronous

Associate a System Event with a Command Sequence

Stored in NVM

Event Monitor Get Association

0x8C01

Synchronous

Retrieve an Event Association

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AS0140AT

Table 29. CCI MANAGER HOST COMMANDS

CCI Manager Host Command

Get Lock

Value

Type

Description

0x8D00

0x8D01

0x8D02

0x8D03

Asynchronous

Synchronous

Request the CCI Manager Access Lock

Retrieve the Status of the Access Lock Request

Release the CCI Manager Access Lock

Lock Status

Release Lock

Config

Configure the CCI Manager and Underlying CCI Subsys-

tem

Set Device

Read

0x8D04

0x8D05

0x8D06

0x8D07

0x8D08

Synchronous

Asynchronous

Synchronous

Set the Target CCI Device Address

Read One or More Bytes from a 16−bit Address

Write One or More Bytes to a 16−bit Address

Read−Modify−Write 16−bit Data to a 16−bit Address

Obtain Status of Current Asynchronous Operation

Write

Write Bitfield

CCI Status

Table 30. SENSOR MANAGER HOST COMMANDS

Sensor Manager Host Command

Discover Sensor

Value

0x8E00

0x8E01

Type

Description

Discover Sensor

Synchronous

Initialize Sensor

Initialize Attached Aensor

Usage Modes

the register and firmware data being transferred −

somewhere between 1 kB to 16 MB. The two−wire bus is

adequate since only high−level commands are used.

The AS0140AT can be configured by a serial EEPROM

or Flash through the SPI Interface.

How a camera based on the AS0140AT will be configured

depends on what features are used. A back−up camera with

dynamic input from the steering system will require a mC

with a system bus interface. Flash sizes vary depending on

Serial

EEPROM/Flash

AS0140AT

SPI

Figure 38. Flash Mode

Serial

EEPROM/Flash

8/16 bit mC

AS0140AT

System Bus

Two−wire

SPI

Figure 39. Host Mode with Flash

8/16 bit mC

AS0140AT

System Bus

Two−wire

Figure 40. Host Mode

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39

AS0140AT

Electrical Specifications

Table 31. ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Min

−0.3

−50

Max

4

Unit

V

DDIO

I/O Power (2.8V)

V

Analog Power (2.8V)

Video Analog DAC Power (3.3V)

Digital Power (1.8V)

DC Input Voltage

4

V

AA

DDA_DAC

V

4

V

DD

2.4

V

IN

V

+ 0.3

V

DDIO

V

OUT

DC Output Voltage

+ 0.3

V

T

ST

Storage Temperature

150

C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

Table 32. ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

Symbol

Parameter

Condition

Min

2.3

2.5

3

Typ

2.8

3.3

1.8

−

Max

3.1

Unit

V

DDIO

IO Power

V

Analog Power

3.1

V

AA

DDA_DAC

V

DAC Analog power

3.6

V

DD

Digital Power

1.7

−40

1.98

105

V

T

A

Functional Operating Temperature

C

(Ambient – T )

A

T

ST

Storage Temperature

−50

−

150

C

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

www.onsemi.com

40

AS0140AT

Table 33. AC ELECTRICAL CHARACTERISTICS

(Default Setup Conditions: f

= 27 MHz, V

= V = 2.8 V, V

= 3.3 V, V = 1.8 V, T = 25C unless otherwise stated)

EXTCLK

DDIO

AA

DDA_DAC

DD

Min

6

A

Symbol

Parameter

Condition

Typ

Max

Unit

MHz

%

f

External Clock Frequency (Note 4)

External Input Clock Duty Cycle

External Input Clock Jitter

−

50

−

30

EXTCLK

D

40

−

60

EXTCLK

EXTCLK_JITTER

t

500

ps

t

Pixel Clock Output Jitter

−

2.5

−

ns

PIXCLK_JITTER

f

Pixel Clock Frequency (One−clock/Pixel)

Pixel Clock Frequency (Two−clocks/Pixel)

Pixel Clock Rise Time (10−90%)

Pixel Clock Fall Time (10−90%)

PIXCLK to Data Valid

6

74.125

MHz

ns

PIXCLK

6

−

84

5

t

C

= 35 pF

−

2.5

1

RPIXCLK

LOAD

t

−

5

ns

FPIXCLK

t

−

5

ns

PD

t

PIXCLK to FV HIGH

−

1

5

ns

PFH

t

PIXCLK to LV HIGH

−

1

5

ns

PLH

t

PIXCLK to FV LOW

−

1

5

ns

PFL

t

PIXCLK to LV LOW

−

1

5

ns

PLL

4. V /V restrictions apply.

IH IL

Table 34. DC ELECTRICAL CHARACTERISTICS

Symbol

Parameter

Condition

Min

Max

Unit

V

IH

Input HIGH Voltage (Note 5)

V * 0.8

DDIO

–

V

Input LOW Voltage (Note 5)

Input Leakage Current (Note 6)

Output HIGH Voltage

–

V

* 0.2

V

mA

V

IL

IN

DDIO

I

V

IN

= 0 V or V = V

DDIO

10

IN

−

DDIO

–

V

OH

V

* 0.8

–

V

OL

Output LOW Voltage

* 0.2

V

DDIO

5. V and V have min/max limitations specified by absolute ratings.

IH

IL

6. Excludes pins that have internal PU resistors.

Table 35. VIDEO DAC ELECTRICAL CHARACTERISTICS

(Default Setup Conditions: f

= 27 MHz, V

= V = 2.8 V, V

= 3.3 V, V = 1.8 V, T = 25C unless otherwise stated)

EXTCLK

DDIO

AA

DDA_DAC

DD

Min

−

A

Symbol

Parameter

Typ

Max

−

Unit

LSB

pF

DNL

INL

Differential Non−linearity

Integral Non−linearity

Load Capacitance

Offset Error

1

3

−

C

−

10

1

LOAD

OER

−1

−2

−5

−

% FS

DGER

GER

Gain Error

−

2

Absolute Gain Error

−

5

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41

AS0140AT

T_FRAME_SYNC

T_RESYNC

FRAME_SYNC

Active

Video

CVBS Output

(NTSC/PAL)

Re−sync Time

Figure 41. Frame_Sync (Interlaced Operation) Diagram

Table 36. FRAME_SYNC (INTERLACED OPERATION) PARAMETERS

Parameter

T_FRAME_SYNC

T_RESYNC

Name

Conditions

Min

−

Typ

−

Max

3

Unit

T_FRAME_SYNC

T_RESYNC

−

EXTCLK Cycles

NTSC

PAL

−

100

120

−

ms

T_RESYNC

−

Table 37. NTSC AND PAL SIGNAL PARAMETERS

(Default Setup Conditions: f

= 27 MHz, V

= V = 2.8 V, V

= 3.3 V, V = 1.8 V, T = 25C unless otherwise stated)

DDA_DAC DD A

EXTCLK

DDIO

AA

Parameter

NTSC

PAL

Unit

Number of Lines per Frame

Line Frequency

Field Frequency

Sync Level

525

625

15734.264

59.94

40

15625

50

Hz

43

IRE

Burst Level

40

43

Black Level

7.5

0

White Level

100

7. IRE ꢀ 7.14 mV.

8. DAC_REF = 3.74 kOhm; Load = 37.5 Ohm.

A

D

E

B

C

J

K

F

H

G

H

Figure 42. Video Timing

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42

AS0140AT

Table 38. VIDEO TIMING: SPECIFICATION FROM REC. ITU−R BT.470

Signal

H Period

NTSC 27 MHz

63.556

PAL 27 MHz

64.00

Unit

ms

A

B

C

D

E

F

Hsync to Burst

Burst

4.71 to 5.71

2.23 to 3.11

9.20 to 10.30

52.655 0.20

1.27 to 2.22

4.70 0.10

 0.25

5.60 0.10

2.25 0.23

10.20 0.30

52 + 0, −0.3

1.5 + 0.3, −0.0

4.70 0.20

0.20 0.10

Hsync to Signal

Video Signal

Front

G

H

Hsync Period

Sync Rising/Falling Edge

L

I

J

K

Figure 43. Equalizing Pulse

Table 39. EQUALIZING PULSE: SPECIFICATION FROM REC. ITU−R BT.470

Signal

H/2 Period

NTSC 27 MHz

31.778

PAL 27 MHz

32.00

Unit

ms

I

J

K

L

Pulse Width

2.30 0.10

 0.25

2.35 0.10

0.25 0.05

3.0 2.0

ms

Pulse Rising/Falling Edge

Signal to Pulse

ms

1.50 0.10

ms

www.onsemi.com

43

AS0140AT

M

O

N

P

Figure 44. V Pulse

Table 40. V PULSE: SPECIFICATION FROM REC. ITU−R BT.470

Signal

H/2 Period

NTSC 27 MHz

31.778

PAL 27 MHz

32.00

Unit

ms

M

N

O

P

Pulse Width

27.10 (Nominal)

4.70 0.10

 0.25

27.30 0.10

4.70 0.10

0.25 0.05

ms

V Pulse Interval

Pulse Rising/Falling Edge

ms

Table 41. STANDBY CURRENT CONSUMPTION

(Default Setup Conditions: f

= 27 MHz, V

= V = 2.8 V, V

= 3.3 V, V = 1.8 V, T = 25C unless otherwise stated)

DDA_DAC DD A

EXTCLK

DDIO

AA

Parameter

Conditions

EXTCLK off

EXTCLK on

Min

Typ

1.3

2.1

Max

5.0

Unit

mA

Hard Standby with STANDBY pin High

9. VAA & VDD supplies only.

−

8.0

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44

AS0140AT

Table 42. OPERATING CURRENT CONSUMPTION

(Default Setup Conditions: f

= 27 MHz, V

not included in measurement, V = 2.8 V, V

= 3.3 V, V = 1.8 V,

EXTCLK

DDIO

AA

DDA_DAC

DD

T = 25C, HDR Mode unless otherwise stated)

A

Symbol

VDDIO = 2.8 V

VAA = 2.8 V

Conditons

Min

TBD

−

Typ

2.8

3.3

1.8

32

Max

TBD

38

Unit

V

VDDA_DAC = 3.3 V

VDD = 1.8 V

V

IAA

NTSC HDR Mode

mA

mW

NTSC Linear Mode

−

32

38

PAL

−

29

35

STE Progressive YCbCr_422_10_10

STE Progressive YCbCr_422_16

STE Progressive YCbCr_422_8_8

NTSC HDR Mode

−

41

49

−

31

37

−

41

49

IDDA_DAC

−

19

26

NTSC Linear Mode

−

19

26

PAL

−

19

26

STE Progressive YCbCr_422_10_10

STE Progressive YCbCr_422_16

STE Progressive YCbCr_422_8_8

NTSC HDR Mode

−

0

−

0

−

0

−

IDD

−

209

197

202

191

231

191

527

506

505

456

504

456

237

228

230

217

264

217

619

603

598

528

579

528

NTSC Linear Mode

−

PAL

−

STE Progressive YCbCr_422_10_10

STE Progressive YCbCr_422_16

STE Progressive YCbCr_422_8_8

NTSC HDR Mode

−

Total Power Consumption

−

NTSC Linear Mode

−

PAL

−

STE Progressive YCbCr_422_10_10

STE Progressive YCbCr_422_16

STE Progressive YCbCr_422_8_8

−

Table 43. INRUSH CURRENT

Supply

VAA

Voltage (V)

Maximum Current (mA)

2.8

3.3

1.8

2.8

509

471

519

502

VDDA_DAC

VDD

VDDIO

10.Based on maximum external LDO drive of 500 mA.

11. 25C.

www.onsemi.com

45

AS0140AT

Two−Wire Serial Register Interface

The electrical characteristics of the two−wire serial

register interface (SCLK, SDATA) are shown in Figure 45

and Table 44.

S

DATA

t

LOW

BUF

t

f

SU;DAT

t

r

t

f

t

r

HD;STA

S

CLK

t

SU;STO

t

SU;STA

HD;STA

t

HIGH

HD;DAT

S

Sr

P

S

Figure 45. Two−Wire Serial Bus Timing Parameters

Table 44. TWO−WIRE SERIAL BUS CHARACTERISTICS (CCIS)

(Default Setup Conditions: f

= 27 MHz, V

= V = 2.8 V, V

= 3.3 V, V = 1.8 V, T = 25C, unless otherwise stated)

DDA_DAC DD A

EXTCLK

DDIO

AA

Standard−Mode

Fast−Mode

Min

0

Max

100

−

Max

400

−

Parameter

Symbol

Unit

KHz

f

S

CLK

Clock Frequency

0

SCL

ms

t

Hold Time (Repeated) START Condition, After This Peri-

od, the First Clock Pulse is Generated

4.0

0.6

HD;STA

ms

t

LOW Period of the S

Clock

4.7

4.0

4.7

−

1.3

0.6

0

−

LOW

CLK

HIGH Period of the S

t

CLK

HIGH

t

Set-up Time for a Repeated START Condition

SU;STA

0

3.45

(Note 14)

0.9

(Note 14)

Data Hold Time

HD;DAT

(Note 13)

ns

Data Set−up Time

250

−

100

−

t

SU;DAT

20 + 0.1Cb

(Note 15)

Rise Time of Both S

and S

Signals (10−90%)

t

r

−

1000

300

DATA

CLK

20 + 0.1Cb

(Note 15)

ns

Fall Time of Both S

and S

Signals (10−90%)

t

f

−

300

DATA

CLK

ms

Set-up Time for STOP Condition

4.0

4.7

−

0.6

1.3

−

t

SU;STO

t

Bus Free Time between a STOP and START Condition

Capacitive Load for Each Bus Line

BUF

pF

kW

Cb

400

3.3

30

4.7

400

3.3

30

4.7

C

Serial Interface Input Pin Capacitance

−

IN_SI

S

DATA

S

DATA

Max Load Capacitance

−

C

LOAD_SD

Pull−up Resistor

1.5

R

SD

12.All values referred to V

= 0.9 V

and V

= 0.1 V

levels. EXTCLK = 27 MHz.

IHmin

DDIO

ILmax

DDIO

13.A device must internally provide a hold time of at least 300 ns for the S

signal to bridge the undefined region of the falling edge of S

.

DATA

CLK

14.The maximum t

has only to be met if the device does not stretch the LOW period (t

) of the t

signal.

HD;DAT

LOW

15.Cb = total capacitance of one bus line in pF.

DR−Pix is a trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other

countries.

www.onsemi.com

46

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

IBGA130 8.5x8.5

CASE 503BK

ISSUE C

DATE 14 FEB 2020

GENERIC

MARKING DIAGRAM*

XXXX = Specific Device Code

= Year

Y

ZZZ = Lot Traceability

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “G”, may

or may not be present. Some products may

not follow the Generic Marking.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON15627G

IBGA130 8.5X8.5

PAGE 1 OF 1

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

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, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates

and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.

A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any

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provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may

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


型号：	AS0140AT2C00XUSM0-DRBR-E
厂家：	ONSEMI
描述：	CMOS 图像传感器，单处理器，1 MP，1/4" 时钟传感器换能器图像传感器
文件：	总48页 (文件大小：1320K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AS0140AT2C00XUSM0-DRBR-E [ONSEMI]

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