AX-SFUS-API-1-01-TX30

AX-SFUS, AX-SFUS-API

Ultra-Low Power,

AT Command / API Controlled,

Sigfox⁾Compliant

Transceiver IC for Up-Link

and Down-Link

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OVERVIEW

Circuit Description

• 8 GPIO pins

AX−SFUS and AX−SFUS−API are ultra−low power

single chip solutions for a node on the Sigfox network with

both up− and down−link functionality. The AX−SFUS chip

is delivered fully ready for operation and contains all the

necessary firmware to transmit and receive data from the

Sigfox network in the US (SIGFOX RCZ2 region). It

connects to the customer product using a logic level RS232

UART. AT commands are used to send frames and configure

radio parameters.

♦ 2 GPIO pins with selectable voltage measure

functionality, differential (1 V or 10 V range) or

single ended (1 V range) with 10 bit resolution

♦ 2 GPIO pins with selectable sigma delta DAC

output functionality

♦ 2 GPIO pins with selectable output clock

♦ 3 GPIO pins selectable as SPI master interface

♦ RX/TX switching Control

The AX−SFUS−API variant is intended for customers

wishing to write their own application software based on the

AX−SF−LIB−1−GEVK library.

Power Consumption**

• Ultra−low Power Consumption:

♦ Charge required to send a Sigfox OOB packet at

24 dBm output power: 0.28 C

♦ Deepsleep mode current: 100 nA

♦ Sleep mode current: 1.3 mA

♦ Standby mode current: 0.5 mA

♦ Continuous radio RX−mode at 905.2 MHz :

34 mA

Features

Functionality and Ecosystem

• Sigfox up−link and down−link functionality controlled

by AT commands or API

• The AX−SFUS and AX−SF−API ICs are part of a

whole development and product ecosystem available

from ON Semiconductor for any Sigfox requirement.

Other parts of the ecosystem include

♦ Continuous radio TX−mode at 902.2 MHz

230 mA @ 24 dBm

♦ Ready to go development kit

High Performance Narrow−band Sigfox RF Transceiver

• Receiver

DVK−SFEU−[API]−1−GEVK including a 2 year

Sigfox subscription

♦ Carrier frequency 905.2 MHz

♦ Data−rate 600 bps FSK

®

♦ Sigfox Ready certified reference design for the

AX−SFUS and AX−SFUS−API ICs

♦ Sensitivity

−128 dBm @ 600 bps, 905.2 MHz, GFSK

♦ 0 dBm maximum input power

General Features

• QFN40 5 mm x 7 mm package

• Supply range 2.7 V* − 3.6 V

• −40°C to 85°C

• Temperature sensor

• Supply voltage measurements

• Transmitter

♦ Carrier frequency 902.2 MHz

♦ Data−rate 600 bps PSK

♦ High efficiency, high linearity integrated power

amplifier

♦ Maximum output power 24 dBm

*Includes the RF frontend module, circuit as in Figure 5. The

AX−SFUS chip alone is operational from 1.8 V to 3.6 V, a supply

voltage below 2.0 V is considered an extreme condition.

**Includes the RF frontend module, circuit as in Figure 5.

Applications

Sigfox networks up−link and down−link.

1

Publication Order Number:

July, 2017 − Rev. 3

AX−SFUS/D

AX−SFUS, AX−SFUS−API

BLOCK DIAGRAM

AX−SFUS / AX−SFUS−API

CLKP

CLKN

CAL

FILT

TCXO

interface

RF synthesis

ANTP1

PA

Transmit

Receive

Communication

controller

ANTP

ANTN

LNA

UARTRX

UARTTX

UART

DAC

ADC

GPIO[9:4,1:0]

GPIO

CPU

RADIO_LED

CPU_LED

TX_LED

RX_LED

TX_EN

dedicated

status

outputs

RX_EN

Program

memory

(FLASH)

power mode control

RAM

Sigfox identity (ID, PAC)

Sigfox compliant

application

(AX−SFUS only)

Figure 1. Functional Block Diagram of the AX−SFUS / AX−SFUS−API

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2

AX−SFUS, AX−SFUS−API

Table 1. PIN FUNCTION DESCRIPTIONS

Symbol

VDD_ANA

Pin(s)

1

Type

Description

P

Analog power output, decouple to neighboring GND

Ground, decouple to neighboring VDD_ANA

Differential receive input

GND

2

P

ANTP

ANTN

ANTP1

GND

3

A

4

A

Differential receive input

5

N

Single ended transmit output

6

P

Ground, decouple to neighboring VDD_ANA

Analog power output, decouple to neighboring GND

Ground

VDD_ANA

GND

7

8

P

FILT

9

A

Synthesizer filter

L2

10

11

12

13

14

15

16

17

A

Must be connected to pin L1

L1

A

Must be connected to pin L2

NC

N

Do not connect

GPIO8

GPIO7

GPIO6

GPIO5

GPIO4

I/O/PU

General purpose IO

General purpose IO, selectable SPI functionality (MISO)

General purpose IO, selectable SPI functionality (MOSI)

General purpose IO, selectable SPI functionality (SCK)

General purpose IO, selectable SD DAC functionality, selectable dock

functionality

CPU_LED

RADIO_LED

VTCXO

18

19

20

21

22

23

24

25

26

27

O

CPU activity indicator

Radio activity indicator

TCXO power

O

GPIO9

I/O/PU

O

General purpose IO, wakeup from deep sleep

UART transmit

UARTTX

UARTRX

RX_LED

TX_LED

NC

I/PU

O

UART receive

Receive activity indicator

Transmit activity indicator

Do not connect

O

PD

I/PU

RESET_N

Optional reset pin. Internal pull−up resistor is permanently enabled,

nevertheless it is recommended to connect this pin to VDD_IO if it is not used.

GND

28

29

30

P

Ground

VDD_IO

GPIO0

Unregulated power supply

I/O/A/PU

General purpose IO, selectable ADC functionality, selectable SD DAC

functionality, selectable clock functionality

GPIO1

TX_EN

NC

31

32

33

34

35

36

37

38

39

I/O/A/PU

General purpose IO, selectable ADC functionality

Transmitter Enable (to frontend)

Do not connect

O

N

O

P

A

N

A

NC

Do not connect

RX_EN

VDD_IO

CAL

Receiver Enable (to frontend)

Unregulated power supply

Connect to FILT as shown in the application diagram

Do not connect

NC

CLKN

TCXO interface

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3

AX−SFUS, AX−SFUS−API

Table 1. PIN FUNCTION DESCRIPTIONS

Symbol

CLKP

Pin(s)

40

Type

A

Description

TCXO interface

GND

Center pad

P

Ground on center pad of QFN, must be connected

A = analog input

Table 2.

I = digital input signal

O = digital output signal

PU = pull−up

I/O = digital input/output signal

N = not to be connected

P = power or ground

PD = pull−down

Possible GPIO Modes

0, 1, Z, U, A, T

0, 1, Z, U, A

0, 1, Z, U, T

0, 1, Z, U

GPIO0

GPIO1

GPIO4

GPIO5

GPIO6

0, 1, Z, U

All digital inputs are Schmitt trigger inputs, digital input

and output levels are LVCMOS/LVTTL compatible. Pins

GPIO[3:0] must not be driven above VDD_IO, all other

digital inputs are 5 V tolerant. All GPIO pins and UARTRX

start up as input with pull−up. For explanations on how to

use the GPIO pins, see chapter “AT Commands”.

GPIO7

GPIO8

GPIO9

0, 1, Z, U

0 = pin drives

1 = not to be connected

Z = pin is high impedance input

U = pin is input with pull−up

A = pin is analog input

T = pin is driven by clock or DAC

Pinout Drawing

40

39

38

37

36

35

34

33

32

31

30

29

1

2

3

4

5

6

7

8

28

27

26

25

24

23

22

21

VDD_ANA

GND

RESET_N

NC

ANTP

TXLED

RXLED

ANTN

AX−SFEU / AX−SFEU−API

QFN40

ANTP1

GND

UARTRX

UARTTX

GPIO9

VDD_ANA

GND

9

10

11

12

13

14

15

16

17

18

19

20

Figure 2. Pinout Drawing (Top View)

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4

AX−SFUS, AX−SFUS−API

SPECIFICATIONS

Table 3. ABSOLUTE MAXIMUM RATINGS

Symbol

VDD_IO

IDD

Description

Condition

Min

Max

5.5

Units

V

Supply voltage

Supply current

−0.5

200

800

10

mA

P

tot

P

i

Total power consumption

mW

dBm

Absolute maximum input power at receiver input

ANTP and ANTN

pins in RX mode

I

DC current into any pin except ANTP, ANTN, ANTP1

DC current into pins ANTP, ANTN, ANTP1

Output Current

−10

10

100

40

mA

V

I1

−100

I2

O

V

Input voltage ANTP, ANTN, ANTP1 pins

Input voltage digital pins

−0.5

−2000

−40

5.5

ia

5.5

V

Electrostatic handling

HBM

2000

85

V

es

T

Operating temperature

°C

amb

T

Storage temperature

−65

150

stg

T

Junction Temperature

j

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

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AX−SFUS, AX−SFUS−API

DC Characteristics

Table 4. SUPPLIES

Conditions for all current and charge values unless otherwise specified are for the hardware configuration described in the AX−SFUS

Application Note: Sigfox Compliant Reference Design.

Symbol

Description

Condition

Min

−40

1.8*

Typ

27

Max

85

Units

°C

T

Operational ambient temperature

AMB

VDD

I/O and voltage regulator supply

voltage AX−SFUS chip only

3.0

3.6

V

IO

VDD

I/O and voltage regulator supply

voltage AX−SFUS with RF frontend

module as in Figure 5

2.7

3.3

3.6

V

IO_mod

VDD

I/O voltage ramp for reset activation;

Note 1

Ramp starts at VDD_IO ≤ 0.1 V

0.1

3.3

V/ms

IO_R1

IO_R2

I/O voltage ramp for reset activation;

Note 1

Ramp starts at 0.1 V < VDD_IO < 0.7 V

I

Deep sleep mode current; Note 3

Sleep mode current; Note 3

AT$P=2

AT$P=1

350

1.6

0.5

nA

mA

DS

SLP

Standby mode current

Notes 2, 3

mA

STDBY

I

Current consumption continuous

RX; Note 3

AT$TM=3,255

34

mA

C

RX_CONT

Q

Charge to send a Sigfox out of band

message, 24 dBm; Note 3

AT$S0

0.25

0.22

0.28

0.73

SFX_OOB_24

SFX_BIT_24

SFX_BITDL_24

SFX_LFR_24

Charge to send a bit, 24 dBm;

Note 3

AT$SB=0

C

Charge to send a bit with downlink

receive, 24 dBm; Note 3

AT$SB=0,1

C

Charge to send the longest possible

Sigfox frame (12 byte) , 24 dBm;

Note 3

AT$SF=00112233445566778899aabb

C

Q

Charge to send the longest possible

Sigfox frame (12 byte) with downlink

receive, 24 dBm; Note 3

AT$SF=00112233445566778899aabb,1

Pout=24 dBm; average

0.84

230

C

SFX_LFRDL_24

I

Modulated Transmitter Current;

Note 3

mA

TXMOD24AVG

*The device is operational from 1.8 V to 3.6 V. However, a supply voltage below 2.0 V is considered an extreme condition and operation can

lead to reduced output power and increased spurious emission.

1. If VDD_IO ramps cannot be guaranteed, an external reset circuit is recommended, see the AX8052 Application Note: Power On Reset

2. Internal 20 MHz oscillator, voltage conditioning and supervisory circuit running.

3. Includes Front End Module, TCXO.

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6

AX−SFUS, AX−SFUS−API

Typical Current Waveform

Typical Current Waveform − Maximum Length Frame with Downlink Receive, Pout = 24 dBm

250

200

150

100

50

0

10

20

30

40

Time [s]

Figure 3. Typical Current Waveform for a Maximum Length Frame with Downlink Receive at 24 dBm Output Power

Battery Life Examples

Scenario:

• Four maximum length frames with downlink receive

• 2 AAA Alkaline batteries in series

• One OOB frame transmitter per day at Pout=24 dBm

per day at Pout=24 dBm

• Device in Sleep

• Neglecting battery self discharge

2 AAA alkaline capacity

Sleep charge per day

OOB frame transmission

Frame transmission with downlink

Total Charge consumption

Battery life

1500 mAh * 3600 s/h

5400 C

1.6 mA * 86400 s

0.14 C/day

0.25 C/day

3.36 C/day

3.75 C/day

3.9 Years

4 * 0.84 C/day

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AX−SFUS, AX−SFUS−API

Table 5. LOGIC

Symbol

Description

Condition

Min

Typ

Max

Units

Digital Inputs

V

Schmitt trigger low to high threshold point

Schmitt trigger high to low threshold point

Input voltage, low

VDD_IO = 3.3 V

1.55

1.25

V

T+

T−

0.8

V

IL

Input voltage, high

2.0

−0.5

−10

V

IH

Input voltage range, GPIO[3:0]

Input voltage range, GPIO[9:4], UARTRX

Input leakage current

VDD_IO

5.5

V

IPA

IPBC

V

I

L

10

mA

kW

R

Programmable Pull−Up Resistance

65

PU

Digital Outputs

I

Output Current, high

Ports GPIO[9:0], UARTTX, TXLED, RXLED,

TXLED, CPULED

V

= 2.4 V

= 0.4 V

8

mA

OH

OL

OZ

OH

Output Current, low

GPIO[9:0], UARTTX, TXLED, RXLED, TXLED,

CPULED

V

OL

Tri−state output leakage current

−10

10

AC Characteristics

Table 6. TCXO REFERENCE INPUT

Symbol

Description

Condition

Min

Typ

48

Max

Units

f

TCXO frequency

A passive network between the TCXO output

and the pins CLKP and CLKN is required.

MHz

TCXO

For detailed TCXO network recommendations

depending on the TCXO output swing refer to

the AX5043 Application Note: Use with a

TCXO Reference Clock.

For TCXO recommendations see the

AX−SFUS Application Note: Sigfox Compliant

Reference Design

Table 7. TRANSMITTER

Conditions for transmitter specifications unless otherwise specified with the antenna network from AX−SFUS Application Note: Sigfox

Compliant Reference Design and at 902.2 MHz.

Symbol

SBR

Description

Condition

Min

Typ

100

24

Max

Units

bps

Signal bit rate

PTX

dTX

Highest Transmitter output power

AT$CW=902200000,1,24

dBm

dB

Transmitter power variation vs.

temperature

−40°C to +85°C

0.5

temp

dTX

Transmitter power variation vs. VDD_IO

1.8 to 3.6 V

0.5

−51

−63

−84

dB

Vdd

nd

PTX

Emission @ 2 harmonic

dBc

harm2

harm3

harm4

rd

Emission @ 3 harmonic

th

Emission @ 4 harmonic

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8

AX−SFUS, AX−SFUS−API

* RBW 1 MHz

* VBW 3 MHz

Marker 1 [T1 ]

−34.50 dBm

1.801282051 GHz

Ref −20 dBm

Att 5 dB

FCCP15H1

* SWT 10 s

Marker 2 [T1 ]

−20

FCCP15H0

−78.31 dBm

2.706730769 GHz

Marker 3 [T1 ]

A

−30

−40

−50

−60

−70

−80

−90

−100

1

1 AV *

CLRWR

−59.62 dBm

3.612179487 GHz

Marker 4 [T1 ]

−67.47 dBm

4.509615385 GHz

3

4

2

3DB

−110

−120

Center 3.5 GHz

500 MHz/

Span 5 GHz

Figure 4. Typical Spectrum with Harmonics at 24 dBm Output Power

Table 8. RECEIVER

Conditions for transmitter specifications unless otherwise specified with the antenna network from AX−SFUS Application Note: Sigfox

Compliant Reference Design and at 869.525 MHz.

Symbol

SBR

IS

Description

Signal bit rate

Condition

Min

Typ

600

Max

Units

bps

AT$SB=x,1, AT$SF=x,1,

AT$TM=3,x PER < 0.1

−128

dBm

BER868

BLK

Blocking at 10 MHz

offset

Channel/Blocker @ PER = 0.1, wanted signal

level is +3 dB above the typical sensitivity, the

blocker signal is CW

78

dB

905

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AX−SFUS, AX−SFUS−API

Table 9. ADC / TEMPERATURE SENSOR

Symbol

Description

Condition

Min

Typ

10

1

Max

Units

Bits

V

ADCRES

ADC resolution

V

ADC reference voltage

Input capacitance

Differential nonlinearity

Integral nonlinearity

Offset

0.95

1.05

2.5

ADCREF

Z

pF

ADC00

DNL

1

LSB

%

INL

OFF

3

GAIN_ERR

Gain error

0.8

ADC in Differential Mode

Absolute voltages & common mode voltage in

V

0

VDD_IO

V

ABS_DIFF

differential mode at each input

V

Gain x1

−500

−50

500

50

mV

Full swing input for differential signals

FS_DIFF01

Gain x10

FS_DIFF10

ADC in Single Ended Mode

V

Mid code input voltage in single ended mode

Input voltage in single ended mode

0.5

V

MID_SE

IN_SE00

FS_SE01

0

VDD_IO

1

Full swing input for single ended signals

Gain x1

Temperature Sensor

T

Temperature range

Temperature error

AT$T?

−40

−2

85

2

°C

RNG

T

ERR_CAL

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10

AX−SFUS, AX−SFUS−API

COMMAND INTERFACE

General Information

mode can be activated with AT$P=2. To wake−up from

Deep Sleep mode, GPIO9 is pulled to GND.

The chapter “Command Interface” is a documentation of

the AT−Command set for devices which do not have an

API−interface. To see whether the device is capable of

receiving AT−Commands, please refer to chapter “Part

Numbers”. If the device has been shipped with the

API−Interface, please refer to the SW manual and

“apiexample” code delivered with AX−SF−LIB−1−GEVK

for an introduction on how to setup a project and how to use

the API−Interface.

When using Deep Sleep mode, keep two things in mind:

Everything is turned off, timers are not running at all and all

settings will be lost (use AT$WR to save settings to flash

before entering Deep Sleep mode). Out−of−band messages

will therefore not be sent. The pins states are frozen in Deep

Sleep mode. The user must ensure that this will not result in

condition which would draw a lot of current.

AT Commands

Serial Parameters: 9600, 8, N, 1

Numerical Syntax

The AX−SFUS uses the UART (pins UARTTX,

UARTRX) to communicate with a host and uses a bitrate of

9600 baud, no parity, 8 data bits and one stop bit.

hexdigit ::= [0−9A−Fa−f]

hexnum ::= “0x” hexdigit+

decnum ::= “0” | [1−9] [0−9]*

octnum ::= “0” [0−7]+

binnum ::= “0b” [01]+

Power Modes

bit

::= [01]

optnum ::= “−1”

frame

uint

::= (hexdigit hexdigit)+

::= hexnum | decnum | octnum | binnum

uint_opt ::= uint | optnum

Command Syntax

A command starts with ‘AT’ (everything is case

sensitive!), continues with the actual command followed by

parameters (if any) and ends with any kind of whitespace

(space, tab, newline etc.)

If incorrect syntax is detected (“parsing error”) all input

is ignored up until the next whitespace character.

Also note that any number can be entered in any format

(Hexadecimal, Decimal, Octal and binary) by adding the

corresponding prefix (‘0x’, ‘0’, ‘0b’). The only exception is

the ‘Send Frame’ command (AT$SF) which expects a list of

hexadecimal digits without any prefix.

Standby

After Power−Up and after finishing a SIGFOX

transmission, AX−SFUS enters Standby mode. In Standby

mode, AX−SFUS listens on the UART for commands from

the host. Also, OOB frames are transmitted whenever the

OOB timer fires. To conserve power, the AX−SFUS can be

put into Sleep or turned off (Deep Sleep) completely.

Return Codes

A successful command execution is indicated by sending

‘OK’. If a command returns a value (e.g. by querying a

register) only the value is returned.

Sleep

Examples

The command AT$P=1 is used to put the AX−SFUS into

Sleep mode. In this mode, only the wakeup timer for

out−of−band messages is still running. To wake the

AX−SFUS up from Sleep mode toggle the serial UARTRX

pin, e.g. by sending a break (break is an RS232 framing

violation, i.e. at least 10 bit durations low). When an Out of

Band (OOB) message is due, AX−SFUS automatically

wakes up to transmit the message, and then returns to Sleep

mode.

Bold text is sent to AX−SFUS.

AT$I=0

AXSEM AT Command Interface

Here, we execute command ‘I’ to query some general

information.

AT$SF=aabb1234

OK

This sends a Sigfox frame containing { 0x00 : 0x11 : 0x22

: 0x33 : 0x44 }, then waits for a downlink response telegram,

which in this example contains { 0xAA : 0xBB : 0xCC :

0xDD }.

Deep Sleep

In Deep Sleep mode, the AX−Sigfox is completely turned

off and only draws negligible leakage current. Deep Sleep

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AX−SFUS, AX−SFUS−API

AT$CB=0011223344,1

OK

RX=AA BB CC DD

The ‘CB’ command sends out a continuous pattern of bits,

in this case 0xAA = 0b10101010.

AT$P=1

OK

This sends a Sigfox frame containing { 0xAA : 0xBB : 0x12

This transitions the device into sleep mode. Out−of−band

transmissions will still be triggered. The UART is powered

down. The device can be woken up by a low level on the

UART signal, i.e. by sending break.

: 0x34 } without waiting for a response telegram.

AT$CB=0xAA,1

OK

Table 10. COMMANDS

Command

Name

Description

AT

Dummy Command

Just returns ‘OK’ and does nothing else. Can be used to check

communication.

AT$SB=bit[,bit]

AT$SF=frame[,bit]

AT$SO

Send Bit

Send a bit status (0 or 1). Optional bit flag indicates if AX−SFUS

should receive a downlink frame.

Send Frame

Send payload data, 1 to 12 bytes. Optional bit flag indicates if

AX−SFUS should receive a downlink frame.

Manually send out of band

message

Send the out−of−band message.

AT$TR?

Get the transmit repeat

Get transmit range

Get transmit repeat

Get Register

Returns the number of transmit repeats. Default: 2

Returns the allowed range of transmit repeats.

Sets the transmit repeat.

AT$TR=?

AT$TR=uint

ATSuint?

Query a specific configuration register’s value. See chapter

“Registers” for a list of registers.

ATSuint=uint

ATSuint=?

Set Register

Change a configuration register.

Get Register Range

Set TX Frequency

Get TX Frequency

Set RX Frequency

Get RX Frequency

Continuous Wave

Returns the allowed range of transmit repeats.

Set the output carrier macro channel for Sigfox frames.

Get the currently chosen TX frequency.

AT$IF=uint

AT$IF?

AT$DR=uint

AT$DR?

Set the reception carrier macro channel for Sigfox frames.

Get the currently chosen RX frequency.

AT$CW=uint,bit[,uint_opt]

To run emission tests for Sigfox certification it is necessary to send a

continuous wave, i.e. just the base frequency without any modula-

tion. Parameters:

Name

Range

Description

Frequency

800000000− Continuous wave frequency in Hz.

999999999, 0 Use 902200000 for Sigfox or 0 to

keep previous frequency.

Mode

0, 1

24

Enable or disable carrier wave.

dBm of signal | Default: 24

Power

AT$CB=uint_opt,bit

Test Mode: TX constant byte

For emission testing it is useful to send a specific bit pattern. The

first parameter specifies the byte to send. Use ‘−1’ for a

(pseudo−)random pattern. Parameters:

Name

Range

Decsription

Pattern

0−255, −1

Byte to send. Use ‘−1’ for a

(pseudo−)random pattern.

Mode

0, 1

Enable or disable pattern test mode.

AT$RC

AT$T?

Reset FCC Macrochannel

Get Temperature

This command resets the FCC Macrochannel. Subsequent transmit

operations (AT$SO, AT$SB, AT$SF) may pause up to 20 s to ensure

FCC compliance

th

Measure internal temperature and return it in 1/10 of a degree

Celsius.

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AX−SFUS, AX−SFUS−API

Table 10. COMMANDS

Command

Name

Description

AT$V?

Get Voltages

Return current voltage and voltage measured during the last

transmission in mV.

AT$I=uint

Information

Display various product information:

0: Software Name & Version

Example Response: AX−Sigfox 1.1.1−FCC

1: Contact Details

Example Response: support@axsem.com

2: Silicon revision lower byte

Example Response: 8F

3: Silicon revision upper byte

Example Response: 51

4: Major Firmware Version

Example Response: 1

5: Minor Firmware Version

Example Response: 1

7: Firmware Variant (Frequency Band etc. (EU/US))

Example Response: FCC

9: SIGFOX Library Version

Example Response: UDL1−1.8.7

10: Device ID

Example Response: 00012345

11: PAC

Example Response: 0123456789ABCDEF

AT$P=uint

Set Power Mode

To conserve power, the AX−SFUS can be put to sleep manually.

Depending on power mode, you will be responsible for waking up the

AX−SFUS again!

0: software reset (settings will be reset to values in flash)

1: sleep (send a break to wake up)

2: deep sleep (toggle GPIO9 or RESET_N pin to wake up;

the AX−SFUS is not running and all settings will be reset!)

AT$WR

AT:Pn?

Save Config

Write all settings to flash (RX/TX frequencies, registers) so they

survive reset/deep sleep or loss of power.

Use AT$P=0 to reset the AX−SFUS and load settings from flash.

Get GPIO Pin

Return the setting of the GPIO Pin n; n can range from 0 to 9.

A character string is returned describing the mode of the pin,

followed by the actual value. If the pin is configured as analog pin,

then the voltage (range 0…1 V) is returned. The mode characters

have the following meaning:

Mode

Description

0

1

Pin drives low

Pin drives high

Z

U

A

T

Pin is high impedance input

Pin is input with pull−up

Pin is analog input (GPIO pin 0…3 only)

Pin is driven by clock or DAC (GPIO pin 0 and 4 only)

The default mode after exiting reset is U on all GPIO pins.

AT:Pn=?

Get GPIO Pin Range

Print a list of possible modes for a pin. The table below lists the

response.

P0

P1

P4

P5

P6

P7

P8

P9

Modes

0, 1, Z, U, A, T

0, 1, Z, U, A

0, 1, Z, U, T

0, 1, Z, U

AT:Pn=mode

Set GPIO Pin

Set the GPIO pin mode.

For a list of the modes see the command AT:Pn?

www.onsemi.com

13

AX−SFUS, AX−SFUS−API

Table 10. COMMANDS

Command

Name

Get GPIO Pin Analog Voltage

Description

AT:ADC Pn[−Pn[ (1V|10V)]]?

Measure the voltage applied to a GPIO pin. The command also

allows measurement of the voltage difference across two GPIO pins.

In differential mode, the full scale range may also be specified as 1 V

or 10 V. Note however that the pin input voltages must not exceed

the range 0..VDD_IO. The command returns the result as fraction of

the full scale range (1 V if none is specified). The GPIO pins

referenced should be initialized to analog mode before issuing this

command.

AT:SPI[(A|B|C|D)]=bytes

SPI Transaction

This command clocks out bytes on the SPI port. The clock frequency is

312.5 kHz. The command returns the bytes read on MISO during out-

put. Optionally the clocking mode may be specified (default is A):

Mode

Clock Inversion

Clock Phase

A

B

C

D

normal

inverted

normal

alternate

normal

alternate

Note that SEL, if needed, is not generated by this command,

and must instead be driven using standard GPIO commands

(AT:Pn=0|1).

AT:CLK=freq,reffreq

Set Clock Generator

Output a square wave on the pin(s) set to T mode. The frequency of

the square wave is (freq / 2 ) × reffreq. Possible values for reffreq

are 20000000, 10000000, 5000000, 2500000, 1250000, 625000,

16

312500, 156250. Possible values if freq are 0…65535.

AT:CLK=OFF

AT:CLK?

Turn off Clock Generator

Get Clock Generator

Switch off the clock generator

Return the settings of the clock generator. Two numbers are

returned, freq and reffreq.

AT:DAC=value

Set SD DAC

Output a SD DAC value on the pin(s) set to T mode. Parameter

value may be in the range −32768…32767. The average output

17

voltage is (1/2 + value / 2 ) × VDD.

An external low pass filter is needed to get smooth output voltages.

The modulation frequency is 20 MHz. A possible low pass filter

choice is a simple RC low pass filter with R = 10 kW and C = 1 mF.

AT:DAC=OFF

AT:DAC?

Turn off SD DAC

Get SD DAC

Switch off the DAC

Return the DAC value

www.onsemi.com

14

AX−SFUS, AX−SFUS−API

Table 10. COMMANDS

Command

Name

Activates the Sigfox Testmode

Description

AT$TM=mode,config

Available test modes:

0. TX BPSK

Send only BPSK with Synchro Bit + Synchro frame +

PN sequence: No hopping centered on the TX_frequency.

Config bits 0 to 6 define the number of repetitions. Bit 7 of config

defines if a delay is applied of not in the loop

1. TX Protocol:

Tx mode with full protocol with Sigfox key: Send Sigfox protocol

frames with initiate downlink flag = True. Config defines the

number of repetitions.

2. RX Protocol:

This mode tests the complete downlink protocol in Downlink only.

Config defines the number of repetitions.

3. RX GFSK:

RX mode with known pattern with SB + SF + Pattern on

RX_frequency (internal comparison with received frame ⇔ known

pattern = AA AA B2 27 1F 20 41 84 32 68 C5 BA AE 79 E7 F6 DD

9B. Config defines the number of repetitions. Config defines the

number of repetitions.

4. RX Sensitivity:

Does uplink + downlink frame with Sigfox key and specific timings.

This test is specific to SIGFOX’s test equipments & softwares.

5. TX Synthesis:

Does one uplink frame on each Sigfox channel to measure

frequency synthesis step

AT$SE

Starts AT$TM−3,255 indefinitely Convenience command for sensitivity tests

AT$SL[=frame]

Send local loop

Sends a local loop frame with optional payload of 1 to 12 bytes.

Default payload: 0x84, 0x32, 0x68, 0xC5, 0xBA, 0x53, 0xAE, 0x79,

0xE7, 0xF6, 0xDD, 0x9B.

AT$RL

Receive local loop

Starts listening for a local loop.

Table 11. REGISTERS

Number

Name

Description

Default

Range

Units

300

Out Of Band

Period

AX−SFUS sends periodic static

messages to indicate that they are

alive. Set to 0 to disable.

24

0−24

hours

400

410

Macrochannel

Mask

The mask of Macrochannels to use.

<000001FF>

<00000000>

<00000000>,1

Encryption Key

Configuration

Set to zero for normal operation. Set

to one for use with the SIGFOX

Network Emulator Kit (SNEK)

0

0−1

0: private key

1: public key

www.onsemi.com

15

AX−SFUS, AX−SFUS−API

APPLICATION INFORMATION

Typical Application Diagrams

Typical AX−SFUS / AX−SFUS−API Application Diagram

Figure 5. Typical Application Diagram

For detailed application configuration and BOM see the

AX−SFUS Application Note: Sigfox Compliant Reference

Design.

www.onsemi.com

16

AX−SFUS, AX−SFUS−API

QFN40 Soldering Profile

Preheat

Reflow

Cooling

t

P

T

P

L

T

t

L

T

sMAX

T

sMIN

t

s

25°C

T

°

25 C to Peak

Time

Figure 6. QFN40 Soldering Profile

Table 12.

Profile Feature

Pb−Free Process

Average Ramp−Up Rate

Preheat Preheat

3°C/s max.

Temperature Min

T

150°C

200°C

sMIN

Temperature Max

T

sMAX

Time (T

to T

)

t

s

60 – 180 sec

8 min max.

sMIN

sMAX

Time 25°C to Peak Temperature

Reflow Phase

T

°

25 C to Peak

Liquidus Temperature

Time over Liquidus Temperature

Peak Temperature

T

217°C

L

t

60 – 150 s

260°C

L

p

Time within 5°C of actual Peak Temperature

Cooling Phase

T

p

20 – 40 s

Ramp−down rate

6°C/s max.

1. All temperatures refer to the top side of the package, measured on the the package body surface.

www.onsemi.com

17

AX−SFUS, AX−SFUS−API

QFN40 Recommended Pad Layout

1. PCB land and solder masking recommendations

are shown in Figure 7.

A = Clearance from PCB thermal pad to solder mask opening, 0.0635 mm minimum

B = Clearance from edge of PCB thermal pad to PCB land, 0.2 mm minimum

C = Clearance from PCB land edge to solder mask opening to be as tight as possible

to ensure that some solder mask remains between PCB pads.

D = PCB land length = QFN solder pad length + 0.1 mm

E = PCB land width = QFN solder pad width + 0.1 mm

Figure 7. PCB Land and Solder Mask Recommendations

2. Thermal vias should be used on the PCB thermal

3. For the PCB thermal pad, solder paste should be

printed on the PCB by designing a stencil with an

array of smaller openings that sum to 50% of the

QFN exposed pad area. Solder paste should be

applied through an array of squares (or circles) as

shown in Figure 8.

4. The aperture opening for the signal pads should be

between 50−80% of the QFN pad area as shown in

Figure 9.

pad (middle ground pad) to improve thermal

conductivity from the device to a copper ground

plane area on the reverse side of the printed circuit

board. The number of vias depends on the package

thermal requirements, as determined by thermal

simulation or actual testing.

3. Increasing the number of vias through the printed

circuit board will improve the thermal

conductivity to the reverse side ground plane and

external heat sink. In general, adding more metal

through the PC board under the IC will improve

operational heat transfer, but will require careful

attention to uniform heating of the board during

assembly.

5. Optionally, for better solder paste release, the

aperture walls should be trapezoidal and the

corners rounded.

6. The fine pitch of the IC leads requires accurate

alignment of the stencil and the printed circuit

board. The stencil and printed circuit assembly

should be aligned to within + 1 mil prior to

application of the solder paste.

Assembly Process

Stencil Design & Solder Paste Application

1. Stainless steel stencils are recommended for solder

paste application.

7. No−clean flux is recommended since flux from

underneath the thermal pad will be difficult to

clean if water−soluble flux is used.

2. A stencil thickness of 0.125 – 0.150 mm

(5 – 6 mils) is recommended for screening.

Figure 8. Solder Paste Application on Exposed Pad

www.onsemi.com

18

AX−SFUS, AX−SFUS−API

Minimum 50% coverage

62% coverage

Maximum 80% coverage

Figure 9. Solder Paste Application on Pins

Life Support Applications

and agree to fully indemnify ON Semiconductor for any

damages resulting from such improper use or sale.

This product is not designed for use in life support

appliances, devices, or in systems where malfunction of this

product can reasonably be expected to result in personal

injury. ON Semiconductor customers using or selling this

product for use in such applications do so at their own risk

Device Information

The following device information can be queried using

the AT−Commands AT$I=4, AT$I=5 for the APP version

and AT$I=2, AT$I=3 for the chip version.

Table 13. DEVICE VERSIONS

APP Version

Chip Version

[0]

[1]

[0]

[1]

Product

AX−SFUS

Part Number

1

AX−SFUS−1−01−XXXX

0x01

0x8F

0x51

1

AX−SFUS−API

AX−SFUS−API−1−01−XXXX

1. TB05 for Reel 500, TX30 for Reel 3000 reel

Sigfox and Sigfox Ready are registered trademarks of Sigfox SARL.

www.onsemi.com

19

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

QFN40 7x5, 0.5P

CASE 485EG

ISSUE B

DATE 26 APR 2017

1

40

SCALE 2:1

NOTES:

L

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

D

A B

2. CONTROLLING DIMENSIONS: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.25 AND 0.30mm FROM TERMINAL

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

PIN ONE

REFERENCE

L1

DETAIL A

ALTERNATE TERMINAL

CONSTRUCTIONS

E

MILLIMETERS

DIM MIN

MAX

1.00

0.05

2X

0.15 C

A

A1

A3

b

0.80

0.00

0.20 REF

0.18

7.00 BSC

EXPOSED Cu

MOLD CMPD

2X

0.30

5.50

0.15

C

TOP VIEW

D

D2

5.30

E

E2

e

L

L1

(A3)

DETAIL B

0.10

0.08

C

DETAIL B

A

ALTERNATE

CONSTRUCTION

A1

SEATING

PLANE

NOTE 4

C

L

SIDE VIEW

D2

GENERIC

MARKING DIAGRAM*

40X

DETAIL A

9

XXXXXXXXXXXX

AWLYYWW

21

40X b

E2

0.10

C

A B

XXX = Specific Device Code

0.05

NOTE 3

1

A

= Assembly Location

29

40

WL = Wafer Lot

YY = Year

WW = Work Week

e

e/2

BOTTOM VIEW

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “ G”,

may or may not be present. Some products

may not follow the Generic Marking.

RECOMMENDED

SOLDERING FOOTPRINT*

7.30

5.60

40X

0.60

PACKAGE

OUTLINE

1

3.60

5.30

40X

0.32

0.50

PITCH

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON04197G

QFN40 7X5, 0.5P

PAGE 1 OF 1

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

www.onsemi.com

onsemi,

, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates

and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.

A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any

products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the

information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use

of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products

and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information

provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may

vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license

under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems

or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should

Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

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Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

ADDITIONAL INFORMATION

TECHNICAL PUBLICATIONS:

Technical Library: www.onsemi.com/design/resources/technical−documentation

onsemi Website: www.onsemi.com

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For additional information, please contact your local Sales Representative at

www.onsemi.com/support/sales




型号：	AX-SFUS-API-1-01-TX30
厂家：	ONSEMI
描述：	射频收发器 SoC，Sigfox™ 验证的 RCZ2，超低功耗，带 API 库射频外围集成电路
文件：	总21页 (文件大小：274K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AX-SFUS-API-1-01-TX30 [ONSEMI]

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