CAT1021LE-28
更新时间:2024-09-18 16:58:53
品牌:ONSEMI
描述:1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDIP8, LEAD AND HALOGEN FREE, PLASTIC, DIP-8
CAT1021LE-28 概述
1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDIP8, LEAD AND HALOGEN FREE, PLASTIC, DIP-8 电源管理电路
CAT1021LE-28 规格参数
是否无铅: | 不含铅 | 是否Rohs认证: | 符合 |
生命周期: | Obsolete | 零件包装代码: | DIP |
包装说明: | DIP, | 针数: | 8 |
Reach Compliance Code: | compliant | ECCN代码: | EAR99 |
HTS代码: | 8542.39.00.01 | 风险等级: | 5.07 |
可调阈值: | NO | 模拟集成电路 - 其他类型: | POWER SUPPLY MANAGEMENT CIRCUIT |
JESD-30 代码: | R-PDIP-T8 | JESD-609代码: | e3 |
长度: | 9.59 mm | 信道数量: | 1 |
功能数量: | 1 | 端子数量: | 8 |
最高工作温度: | 125 °C | 最低工作温度: | -40 °C |
封装主体材料: | PLASTIC/EPOXY | 封装代码: | DIP |
封装形状: | RECTANGULAR | 封装形式: | IN-LINE |
峰值回流温度(摄氏度): | 260 | 认证状态: | Not Qualified |
座面最大高度: | 4.57 mm | 最大供电电压 (Vsup): | 5.5 V |
最小供电电压 (Vsup): | 3 V | 标称供电电压 (Vsup): | 3.3 V |
表面贴装: | NO | 技术: | CMOS |
温度等级: | AUTOMOTIVE | 端子面层: | MATTE TIN |
端子形式: | THROUGH-HOLE | 端子节距: | 2.54 mm |
端子位置: | DUAL | 处于峰值回流温度下的最长时间: | 40 |
宽度: | 7.62 mm | Base Number Matches: | 1 |
CAT1021LE-28 数据手册
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PDF下载CAT1021, CAT1022,
CAT1023
Supervisory Circuits with
I2C Serial 2k-bit CMOS
EEPROM, Manual Reset and
Watchdog Timer
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Description
The CAT1021, CAT1022 and CAT1023 are complete memory and
supervisory solutions for microcontroller−based systems. A 2k−bit
serial EEPROM memory and a system power supervisor with
brown−out protection are integrated together in low power CMOS
PDIP−8
CASE 646AA
TSSOP−8
CASE 948S
2
technology. Memory interface is via a 400 kHz I C bus.
The CAT1021 and CAT1023 provide a precision VCC sense circuit
and two open drain outputs: one (RESET) drives high and the other
(RESET) drives low whenever VCC falls below the reset threshold
voltage. The CAT1022 has only a RESET output and does not have a
Write Protect input. The CAT1021 also has a Write Protect input
(WP). Write operations are disabled if WP is connected to a logic high.
All supervisors have a 1.6 second watchdog timer circuit that resets
a system to a known state if software or a hardware glitch halts or
“hangs” the system. For the CAT1021 and CAT1022, the watchdog
timer monitors the SDA signal. The CAT1023 has a separate watchdog
timer interrupt input pin, WDI.
The power supply monitor and reset circuit protect memory and
system controllers during power up/down and against brownout
conditions. Five reset threshold voltages support 5 V, 3.3 V and 3 V
systems. If power supply voltages are out of tolerance reset signals
become active, preventing the system microcontroller, ASIC or
peripherals from operating. Reset signals become inactive typically
200 ms after the supply voltage exceeds the reset threshold level. With
both active high and low reset signals, interface to microcontrollers
and other ICs is simple. In addition, the RESET pin or a separate input,
MR, can be used as an input for push−button manual reset capability.
SOIC−8
CASE 751BD
MSOP−8
CASE 846AD
TDFN−8
CASE 511AL
ORDERING INFORMATION
For Ordering Information details, see page 13.
The on−chip, 2k−bit EEPROM memory features a 16−byte page. In addition, hardware data protection is provided by a VCC
sense circuit that prevents writes to memory whenever VCC falls below the reset threshold or until VCC reaches the reset
threshold during power up.
Available packages include an 8−pin PDIP and surface mount 8−pin SO, 8−pin TSSOP, 8−pin TDFN and 8−pin MSOP
packages. The TDFN package thickness is 0.8 mm maximum. TDFN footprint options are 3 x 3 mm.
Features
• Precision Power Supply Voltage Monitor
• Built−in Inadvertent Write Protection
♦ WP Pin (CAT1021)
♦ 5 V, 3.3 V and 3 V Systems
♦ Five Threshold Voltage Options
• 1,000,000 Program/Erase Cycles
• Manual Reset Input
• Watchdog Timer
• Active High or Low Reset
♦ Valid Reset Guaranteed at VCC = 1 V
• 100 Year Data Retention
• Industrial and Extended Temperature Ranges
2
• 400 kHz I C Bus
• 8−pin DIP, SOIC, TSSOP, MSOP or TDFN (3 x 3 mm
• 2.7 V to 5.5 V Operation
Foot−print) Packages
• Low Power CMOS Technology
• 16−Byte Page Write Buffer
♦ TDFN Max Height is 0.8 mm
• These Devices are Pb−Free, Halogen Free/BFR Free
and are RoHS Compliant
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
November, 2011 − Rev. 18
CAT1021/D
CAT1021, CAT1022, CAT1023
Table 1. THRESHOLD VOLTAGE OPTION
Part Dash
Number
Minimum
Threshold
Maximum
Threshold
−45
−42
−30
−28
−25
4.50
4.25
3.00
2.85
2.55
4.75
4.50
3.15
3.00
2.70
BLOCK DIAGRAM
EXTERNAL LOAD
SENSEAMPS
SHIFT REGISTERS
D
OUT
ACK
V
V
CC
SS
WORDADDRESS
BUFFERS
COLUMN
DECODERS
START/STOP
SDA
LOGIC
2kbit
EEPROM
XDEC
CONTROL
LOGIC
WP
( AT1021)
C
DATA IN STORAGE
HIGHVOLTAGE/
TIMING CONTROL
RESET Controller
STATE COUNTERS
SCL
Precision
SLAVE
ADDRESS
MR
Vcc Monitor
COMPARATORS
WDI
(CAT1023)
RESET
(CAT1021/23)
RESET
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2
CAT1021, CAT1022, CAT1023
PIN CONFIGURATION
DIP Package (L)
SOIC Package (W)
TSSOP Package (Y)
MSOP Package (Z)
(Bottom View)
TDFN Package: 3 mm x 3 mm
0.8mm maximum height − (ZD4)
MR
V
8
7
6
5
1
2
3
4
CC
MR
RESET
WP
1
2
3
4
8
7
6
5
V
CC
RESET
WP
RESET
RESET
CAT1021
CAT1022
CAT1023
CAT1021
CAT1022
CAT1023
SCL
SDA
SCL
SDA
V
SS
V
SS
MR
V
CC
8
7
6
5
1
2
3
4
MR
RESET
NC
1
2
3
4
8
7
6
5
V
CC
RESET
NC
NC
NC
SCL
SDA
SCL
SDA
V
SS
V
SS
MR
RESET
RESET
1
2
3
4
8
7
6
5
V
CC
MR
V
CC
8
7
6
5
1
2
3
4
WDI
RESET
RESET
WDI
SCL
SDA
SCL
SDA
V
SS
V
SS
PIN DESCRIPTION
RESET/RESET: RESET OUTPUT
(RESET CAT1021/23 Only)
WDI (CAT1023 Only): WATCHDOG TIMER
INTERRUPT
These are open drain pins and RESET can be used as a
manual reset trigger input. By forcing a reset condition on
the pin the device will initiate and maintain a reset condition.
The RESET pin must be connected through a pull−down
resistor, and the RESET pin must be connected through a
pull−up resistor.
Watchdog Timer Interrupt Input is used to reset the
watchdog timer. If a transition from high to low or low to
high does not occur every 1.6 seconds, the RESET outputs
will be driven active.
Table 2. PIN FUNCTION
SDA: SERIAL DATA ADDRESS
Pin Name
NC
Function
The bidirectional serial data/address pin is used to transfer
all data into and out of the device. The SDA pin is an open
drain output and can be wire−ORed with other open drain or
open collector outputs.
No Connect
RESET
Active Low Reset Input/Output
Ground
V
SS
SCL: SERIAL CLOCK
Serial clock input.
SDA
SCL
Serial Data/Address
Clock Input
MR: MANUAL RESET INPUT
RESET
Active High Reset Output (CAT1021/23)
Power Supply
Manual Reset input is a debounced input that can be
connected to an external source for Manual Reset. Pulling
the MR input low will generate a Reset condition. Reset
outputs are active while MR input is low and for the reset
timeout period after MR returns to high. The input has an
internal pull up resistor.
V
CC
WP
MR
Write Protect (CAT1021 Only)
Manual Reset Input
WDI
Watchdog Timer Interrupt (CAT1023)
WP (CAT1021 Only): WRITE PROTECT INPUT
When WP input is tied to VSS or left unconnected write
operations to the entire array are allowed. When tied to VCC,
the entire array is protected. This input has an internal pull
down resistor.
Table 3. OPERATING TEMPERATURE RANGE
Industrial
Extended
−40°C to 85°C
−40°C to 125°C
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3
CAT1021, CAT1022, CAT1023
Table 4. CAT102X FAMILY OVERVIEW
Device
Manual Reset
Input Pin
Watchdog
Watchdog
Monitor Pin
Write
Protection
Pin
Independent
Auxiliary Voltage
Sense
RESET:
Active High
and LOW
EEPROM
CAT1021
CAT1022
CAT1023
CAT1024
CAT1025
CAT1026
CAT1027
n
n
n
n
n
n
n
n
SDA
SDA
WDI
n
n
2k
2k
2k
2k
2k
2k
2k
n
n
n
n
n
n
n
WDI
NOTE: For supervisory circuits with embedded 16k EEPROM, please refer to the CAT1161, CAT1162 and CAT1163 data sheets.
SPECIFICATIONS
Table 5. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
°C
°C
V
Temperature Under Bias
Storage Temperature
–55 to +125
–65 to +150
Voltage on any Pin with Respect to Ground (Note 1)
with Respect to Ground
−2.0 to V + 2.0
CC
V
CC
−2.0 to 7.0
1.0
V
Package Power Dissipation Capability (T = 25°C)
W
A
Lead Soldering Temperature (10 s)
Output Short Circuit Current (Note 2)
300
°C
mA
100
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum
DC voltage on output pins is V +0.5 V, which may overshoot to V +2.0 V for periods of less than 20 ns.
CC
CC
2. Output shorted for no more than one second. No more than one output shorted at a time.
Table 6. D.C. OPERATING CHARACTERISTICS
V
CC
= 2.7 V to 5.5 V and over the recommended temperature conditions unless otherwise specified.
Symbol
Parameter
Input Leakage Current
Test Conditions
Min
−2
Typ
Max
10
10
3
Units
mA
I
LI
V
V
= GND to V
= GND to V
IN
CC
CC
I
LO
Output Leakage Current
−10
mA
IN
I
Power Supply Current (Write)
f
= 400 kHz
= 5.5 V
mA
CC1
SCL
V
CC
I
Power Supply Current (Read)
Standby Current
f
= 400 kHz
= 5.5 V
1
60
mA
CC2
SCL
CC
V
I
V
V
= 5.5 V
= GND to V
mA
SB
CC
IN
CC
V
(Note 3)
(Note 3)
Input Low Voltage
Input High Voltage
−0.5
0.3 x V
V
V
V
IL
CC
V
IH
0.7 x V
V
CC
+ 0.5
CC
V
OL
Output Low Voltage
(SDA, RESET)
I
= 3 mA
CC
0.4
OL
V
= 2.7 V
V
OH
Output High Voltage
(RESET)
I
= −0.4 mA
CC
V − 0.75
CC
V
OH
V
= 2.7 V
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CAT1021, CAT1022, CAT1023
Table 6. D.C. OPERATING CHARACTERISTICS
V
CC
= 2.7 V to 5.5 V and over the recommended temperature conditions unless otherwise specified.
Symbol
Parameter
Reset Threshold
Test Conditions
Min
Typ
Max
Units
V
TH
CAT102x−45
4.50
4.75
V
(V = 5.0 V)
CC
CAT102x−42
CC
4.25
3.00
2.85
2.55
4.50
3.15
3.00
2.70
(V = 5.0 V)
CAT102x−30
(V = 3.3 V)
CC
CAT102x−28
(V = 3.3 V)
CC
CAT102x−25
(V = 3.0 V)
CC
V
Reset Output Valid V Voltage
1.00
15
V
RVALID
CC
V
(Note 4)
Reset Threshold Hysteresis
mV
RT
3. V min and V max are reference values only and are not tested.
IL
IH
4. This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested.
Table 7. CAPACITANCE
T = 25°C, f = 1.0 MHz, V = 5 V
A
CC
Symbol
(Note 5)
Test
Test Conditions
= 0 V
OUT
Max
8
Units
pF
C
Output Capacitance
Input Capacitance
V
V
OUT
C
(Note 5)
= 0 V
IN
6
pF
IN
Table 8. AC CHARACTERISTICS
V
CC
= 2.7 V to 5.5 V and over the recommended temperature conditions, unless otherwise specified.
Memory Read & Write Cycle (Note 6)
Symbol
Parameter
Min
Max
400
100
Units
kHz
ns
f
Clock Frequency
SCL
t
SP
Input Filter Spike Suppression (SDA, SCL)
Clock Low Period
t
1.3
0.6
ms
LOW
t
Clock High Period
ms
HIGH
t
(Note 5)
SDA and SCL Rise Time
300
300
ns
R
t (Note 5)
SDA and SCL Fall Time
ns
F
t
Start Condition Hold Time
0.6
0.6
0
ms
HD; STA
t
Start Condition Setup Time (for a Repeated Start)
Data Input Hold Time
ms
SU; STA
HD; DAT
t
ns
t
Data Input Setup Time
100
0.6
ns
SU; DAT
SU; STO
t
Stop Condition Setup Time
ms
t
SCL Low to Data Out Valid
900
5
ns
AA
t
Data Out Hold Time
50
ns
DH
t
(Note 5)
(Note 7)
Time the Bus must be Free Before a New Transmission Can Start
Write Cycle Time (Byte or Page)
1.3
ms
BUF
t
ms
WC
5. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
6. Test Conditions according to “AC Test Conditions” table.
7. The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the
write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.
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CAT1021, CAT1022, CAT1023
Table 9. RESET CIRCUIT AC CHARACTERISTICS
Symbol
Parameter
Test Conditions
Note 2
Min
Typ
Max
270
5
Units
ms
ms
t
Power−Up Reset Timeout
130
200
PURST
t
V
TH
V
CC
to RESET output Delay
Glitch Reject Pulse Width
Note 3
RDP
t
Notes 4 and 5
Note 1
30
ns
GLITCH
MR Glitch
Manual Reset Glitch Immunity
MR Pulse Width
100
ns
t
Note 1
5
ms
MRW
t
MR Input to RESET Output Delay
Watchdog Timeout
Note 1
1
ms
MRD
t
Note 1
1.0
1.6
2.1
sec
WD
Table 10. POWER−UP TIMING (Notes 5 and 6)
Symbol
Parameter
Power−Up to Read Operation
Power−Up to Write Operation
Test Conditions
Min
Typ
Max
270
270
Units
ms
t
PUR
t
ms
PUW
Table 11. AC TEST CONDITIONS
Parameter
Test Conditions
Input Pulse Voltages
0.2 x V to 0.8 x V
CC
CC
Input Rise and Fall Times
Input Reference Voltages
Output Reference Voltages
Output Load
10 ns
0.3 x V , 0.7 x V
CC
CC
0.5 x V
CC
Current Source: I = 3 mA; C = 100 pF
OL
L
Table 12. RELIABILITY CHARACTERISTICS
Symbol
(Note 5)
Parameter
Endurance
Reference Test Method
Min
1,000,000
100
Max
Units
N
MIL−STD−883, Test Method 1033
MIL−STD−883, Test Method 1008
MIL−STD−883, Test Method 3015
JEDEC Standard 17
Cycles/Byte
Years
END
T
(Note 5)
(Note 5)
Data Retention
DR
V
ESD Susceptibility
2000
Volts
ZAP
I
(Notes 5 & 7) Latch−Up
100
mA
LTH
1. Test Conditions according to “AC Test Conditions” table.
2. Power−up, Input Reference Voltage V = V , Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
CC
TH
3. Power−Down, Input Reference Voltage V = V , Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
CC
TH
4. V Glitch Reference Voltage = V
; Based on characterization data
CC
THmin
5. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
6. t
and t
are the delays required from the time V is stable until the specified memory operation can be initiated.
PUR
PUW CC
7. Latch−up protection is provided for stresses up to 100 mA on input and output pins from −1 V to V + 1 V.
CC
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CAT1021, CAT1022, CAT1023
DEVICE OPERATON
Reset Controller Description
Hardware Data Protection
The CAT1021/22/23 precision RESET controllers ensure
correct system operation during brownout and power
up/down conditions. They are configured with open drain
RESET outputs.
During power−up, the RESET outputs remain active until
VCC reaches the VTH threshold and will continue driving the
outputs for approximately 200 ms (tPURST) after reaching
VTH. After the tPURST timeout interval, the device will cease
to drive the reset outputs. At this point the reset outputs will
be pulled up or down by their respective pull up/down
resistors.
During power−down, the RESET outputs will be active
when VCC falls below VTH. The RESET output will be valid
so long as VCC is >1.0 V (VRVALID). The device is designed
to ignore the fast negative going VCC transient pulses
(glitches).
The CAT1021/22/23 supervisors have been designed to
solve many of the data corruption issues that have long been
associated with serial EEPROMs. Data corruption occurs
when incorrect data is stored in a memory location which is
assumed to hold correct data.
Whenever the device is in a Reset condition, the
embedded EEPROM is disabled for all operations,
including write operations. If the Reset output(s) are active,
in progress communications to the EEPROM are aborted
and no new communications are allowed. In this condition
an internal write cycle to the memory can not be started, but
an in progress internal nonvolatile memory write cycle can
not be aborted. An internal write cycle initiated before the
Reset condition can be successfully finished if there is
enough time (5ms) before VCC reaches the minimum value
of 2V.
Reset output timing is shown in Figure 1.
In addition, the CAT1021 includes a Write Protection
Input which when tied to VCC will disable any write
operations to the device.
Manual Reset Operation
The RESET pin can operate as reset output and manual
reset input. The input is edge triggered; that is, the RESET
input will initiate a reset timeout after detecting a high to low
transition.
Watchdog Timer
The Watchdog Timer provides an independent protection
for microcontrollers. During
a
system failure,
When RESET I/O is driven to the active state, the 200 ms
timer will begin to time the reset interval. If external reset is
shorter than 200 ms, Reset outputs will remain active at least
200 ms.
The CAT1021/22/23 also have a separate manual reset
input. Driving the MR input low by connecting a pushbutton
(normally open) from MR pin to GND will generate a reset
condition. The input has an internal pull up resistor.
Reset remains asserted while MR is low and for the Reset
Timeout period after MR input has gone high.
Glitches shorter than 100 ns on MR input will not generate
a reset pulse. No external debouncing circuits are required.
Manual reset operation using MR input is shown in Figure 2.
CAT1021/22/23 devices will provide a reset signal after a
time−out interval of 1.6 seconds for a lack of activity. The
CAT1023 is designed with the Watchdog timer feature on
the WDI pin. The CAT1021 and CAT1022 monitor the SDA
line. If WDI or SDA does not toggle within a 1.6 second
interval, the reset condition will be generated on the reset
outputs. The watchdog timer is cleared by any transition on
a monitored line.
As long as reset signal is asserted, the watchdog timer will
not count and will stay cleared.
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RV
L D
T
T
CAT1021, CAT1022, CAT1023
tGLITCH
VTH
V
tRPD
tPUR
VCC
tRPD
tPUR
RESEꢀT
RESET
Figure 1. RESET Output Timing
tMRW
MR
tMRD
tPURST
RESET
RESET
Figure 2. MR Operation and Timing
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8TH B
T
ACK
CAT1021, CAT1022, CAT1023
EMBEDDED EEPROM OPERATON
The CAT1021/22/23 feature a 2−kbit embedded serial
EEPROM that supports the I C Bus data transmission
2. During a data transfer, the data line must remain
stable whenever the clock line is high. Any
2
protocol. This Inter−Integrated Circuit Bus protocol defines
any device that sends data to the bus to be a transmitter and
any device receiving data to be a receiver. The transfer is
controlled by the Master device which generates the serial
clock and all START and STOP conditions for bus access.
Both the Master device and Slave device can operate as
either transmitter or receiver, but the Master device controls
which mode is activated.
changes in the data line while the clock line is high
will be interpreted as a START or STOP condition.
Start Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of SDA
when SCL is HIGH. The CAT1021/22/23 monitor the SDA
and SCL lines and will not respond until this condition is
met.
I2C Bus Protocol
The features of the I C bus protocol are defined as
Stop Condition
2
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
follows:
1. Data transfer may be initiated only when the bus is
not busy.
DEVICE ADDRESSING
The Master begins a transmission by sending a START
condition. The Master sends the address of the particular
slave device it is requesting. The four most significant bits
of the 8−bit slave address are programmable in metal and the
default is 1010.
The last bit of the slave address specifies whether a Read
or Write operation is to be performed. When this bit is set to
1, a Read operation is selected, and when set to 0, a Write
operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT1021/22/23 monitors the bus and
responds with an acknowledge (on the SDA line) when its
address matches the transmitted slave address. The
CAT1021/22/23 then perform a Read or Write operation
depending on the R/W bit.
t
t
t
F
HIGH
R
t
t
LOW
LOW
SCL
t
t
HD:DAT
SU:STA
t
t
t
t
HD:STA
SU:DAT
SU:STO
SDA IN
BUF
t
AA
t
DH
SDA OUT
Figure 3. Bus Timing
SCL
SDA
BYTE n
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 4. Write Cycle Timing
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CAT1021, CAT1022, CAT1023
ACKNOWLEDGE
After a successful data transfer, each receiving device is
When a device begins a READ mode it transmits 8 bits of
data, releases the SDA line and monitors the line for an
acknowledge. Once it receives this acknowledge, the device
will continue to transmit data. If no acknowledge is sent by
the Master, the device terminates data transmission and
waits for a STOP condition.
required to generate an acknowledge. The acknowledging
device pulls down the SDA line during the ninth clock cycle,
signaling that it received the 8 bits of data.
All devices respond with an acknowledge after receiving
a START condition and its slave address. If the device has
been selected along with a write operation, it responds with
an acknowledge after receiving each 8−bit byte.
WRITE OPERATIONS
Byte Write
Master device transmits the data to be written into the
addressed memory location. The device acknowledges once
more and the Master generates the STOP condition. At this
time, the device begins an internal programming cycle to
non−volatile memory. While the cycle is in progress, the
device will not respond to any request from the Master
device.
In the Byte Write mode, the Master device sends the
START condition and the slave address information (with
the R/W bit set to zero) to the Slave device. After the Slave
generates an acknowledge, the Master sends a 8−bit address
that is to be written into the address pointers of the device.
After receiving another acknowledge from the Slave, the
SDA
SCL
START BIT
STOP BIT
Figure 5. Start/Stop Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 6. Acknowledge Timing
Default Configuration
1
0
1
0
0
0
0
R/W
Figure 7. Slave Address Bits
http://onsemi.com
10
CAT1021, CAT1022, CAT1023
Page Write
The CAT1021/22/23 writes up to 16 bytes of data in a
single write cycle, using the Page Write operation. The page
write operation is initiated in the same manner as the byte
write operation, however instead of terminating after the
initial byte is transmitted, the Master is allowed to send up
to 15 additional bytes. After each byte has been transmitted,
the CAT1021/22/23 will respond with an acknowledge and
internally increment the lower order address bits by one. The
high order bits remain unchanged.
If the Master transmits more than 16 bytes before sending
the STOP condition, the address counter ‘wraps around,’
and previously transmitted data will be overwritten.
When all 16 bytes are received, and the STOP condition
has been sent by the Master, the internal programming cycle
begins. At this point, all received data is written to the
CAT1021/22/23 in a single write cycle.
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS
DATA
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
Figure 8. Byte Write Timing
S
T
A
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
R
DATAꢁn
DATA nꢀ+ꢀ1
DATA n+15
T
S
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 9. Page Write Timing
Acknowledge Polling
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is issued
to indicate the end of the host’s write opration, the
CAT1021/22/23 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves issuing
the start condition followed by the slave address for a write
operation. If the device is still busy with the write operation,
no ACK will be returned. If a write operation has completed,
an ACK will be returned and the host can then proceed with
the next read or write operation.
WRITE PROTECTION PIN (WP)
The Write Protection feature (CAT1021 only) allows the
user to protect against inadvertent memory array
programming. If the WP pin is tied to VCC, the entire
memory array is protected and becomes read only. The
CAT1021 will accept both slave and byte addresses, but the
memory location accessed is protected from programming
by the device’s failure to send an acknowledge after the first
byte of data is received.
READ OPERATIONS
The READ operation for the CAT1021/22/23 is initiated
in the same manner as the write operation with one
exception, the R/W bit is set to one. Three different READ
operations are possible: Immediate/Current Address
READ, Selective/Random READ and Sequential READ.
http://onsemi.com
11
CAT1021, CAT1022, CAT1023
S
T
A
R
T
S
T
O
P
BUS ꢀACTIVITꢀY:
MASTER
SLꢀAVE
ADDRESS
SDꢀA LINE
S
P
A
C
K
N
O
DATA
A
C
K
SCꢀL
8
9
SDꢀAꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂ8TH BIꢀT
DATA OUꢀT
NO ACK
STOP
Figure 10. Immediate Address Read Timing
Immediate/Current Address Read
sends the START condition and the slave address again, this
time with the R/W bit set to one. The CAT1021/22/23 then
responds with its acknowledge and sends the 8−bit byte
requested. The master device does not send an acknowledge
but will generate a STOP condition.
The CAT1021/22/23 address counter contains the address
of the last byte accessed, incremented by one. In other
words, if the last READ or WRITE access was to address N,
the READ immediately following would access data from
address N + 1. For N = E = 255, the counter will wrap around
to zero and continue to clock out valid data. After the
CAT1021/22/23 receives its slave address information (with
the R/W bit set to one), it issues an acknowledge, then
transmits the 8−bit byte requested. The master device does
not send an acknowledge, but will generate a STOP
condition.
Sequential Read
The Sequential READ operation can be initiated by either
the Immediate Address READ or Selective READ
operations. After the CAT1021/22/23 sends the inital 8− bit
byte requested, the Master will responds with an
acknowledge which tells the device it requires more data.
The CAT1021/22/23 will continue to output an 8− bit byte
for each acknowledge, thus sending the STOP condition.
The data being transmitted from the CAT1021/22/23 is
sent sequentially with the data from address N followed by
data from address N + 1. The READ operation address
counter increments all of the CAT1021/22/23 address bits so
that the entire memory array can be read during one
operation.
Selective/Random Read
Selective/Random READ operations allow the Master
device to select at random any memory location for a READ
operation. The Master device first performs a ‘dummy’
write operation by sending the START condition, slave
address and byte addresses of the location it wishes to read.
After the CAT1021/22/23 acknowledges, the Master device
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
SLAVE
ADDRESS
SDA LINE
S
S
P
A
C
K
A
C
K
A
C
K
N
O
DATA n
A
C
K
Figure 11. Selective Read Timing
http://onsemi.com
12
CAT1021, CAT1022, CAT1023
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
Figure 12. Sequential Read Timing
ORDERING INFORMATION
Orderable Part Numbers − CAT1021 Series
(See Notes 1 − 5)
Device
Reset Threshold
4.50 V − 4.75 V
4.25 V − 4.50 V
3.00 V − 3.15 V
2.85 V − 3.00 V
2.55 V − 2.70 V
4.50 V − 4.75 V
4.25 V − 4.50 V
3.00 V − 3.15 V
2.85 V − 3.00 V
2.55 V − 2.70 V
4.50 V − 4.75 V
4.25 V − 4.50 V
3.00 V − 3.15 V
2.85 V − 3.00 V
2.55 V − 2.70 V
4.50 V − 4.75 V
4.25 V − 4.50 V
3.00 V − 3.15 V
2.85 V − 3.00 V
2.55 V − 2.70 V
4.50 V − 4.75 V
4.25 V − 4.50 V
3.00 V − 3.15 V
2.85 V − 3.00 V
2.55 V − 2.70 V
Package
Shipping
CAT1021LI−45−G
CAT1021LI−42−G
CAT1021LI−30−G
PDIP
CAT1021LI−28−G
CAT1021LI−25−G
CAT1021WI−45−GT3
CAT1021WI−42−GT3
CAT1021WI−30−GT3
CAT1021WI−28−GT3
CAT1021WI−25−GT3
CAT1021YI−45−GT3
CAT1021YI−42−GT3
CAT1021YI−30−GT3
CAT1021YI−28−GT3
CAT1021YI−25−GT3
CAT1021ZI−45−GT3
CAT1021ZI−42−GT3
CAT1021ZI−30−GT3
CAT1021ZI−28−GT3
CAT1021ZI−25−GT3
CAT1021ZD4I−45T3*
CAT1021ZD4I−42T3*
CAT1021ZD4I−30T3*
CAT1021ZD4I−28T3*
CAT1021ZD4I−25T3*
SOIC
TSSOP
MSOP
TDFN
3000 Tape & Reel
1. All packages are RoHS−compliant (Lead−free, Halogen−free).
2. The standard lead finish is NiPdAu.
3. For additional package and temperature options, please contact your nearest
ON Semiconductor Sales office.
4. TDFN not available in NiPdAu (–G) version.
5. For detailed information and a breakdown of device nomenclature and numbering
systems, please see the ON Semiconductor Device Nomenclature document,
TND310/D, available at www.onsemi.com
http://onsemi.com
13
CAT1021, CAT1022, CAT1023
Orderable Part Numbers − CAT1022 Series
(See Notes 1 − 5)
Device
Reset Threshold
4.50 V − 4.75 V
4.25 V − 4.50 V
3.00 V − 3.15 V
2.85 V − 3.00 V
2.55 V − 2.70 V
4.50 V − 4.75 V
4.25 V − 4.50 V
3.00 V − 3.15 V
2.85 V − 3.00 V
2.55 V − 2.70 V
4.50 V − 4.75 V
4.25 V − 4.50 V
3.00 V − 3.15 V
2.85 V − 3.00 V
2.55 V − 2.70 V
4.50 V − 4.75 V
4.25 V − 4.50 V
3.00 V − 3.15 V
2.85 V − 3.00 V
2.55 V − 2.70 V
4.50 V − 4.75 V
4.25 V − 4.50 V
3.00 V − 3.15 V
2.85 V − 3.00 V
2.55 V − 2.70 V
Package
Shipping
CAT1022LI−45−G
CAT1022LI−42−G
CAT1022LI−30−G
PDIP
CAT1022LI−28−G
CAT1022LI−25−G
CAT1022WI−45−GT3
CAT1022WI−42−GT3
CAT1022WI−30−GT3
CAT1022WI−28−GT3
CAT1022WI−25−GT3
CAT1022YI−45−GT3
CAT1022YI−42−GT3
CAT1022YI−30−GT3
CAT1022YI−28−GT3
CAT1022YI−25−GT3
CAT1022ZI−45−GT3
CAT1022ZI−42−GT3
CAT1022ZI−30−GT3
CAT1022ZI−28−GT3
CAT1022ZI−25−GT3
CAT1022ZD4I−45T3*
CAT1022ZD4I−42T3*
CAT1022ZD4I−30T3*
CAT1022ZD4I−28T3*
CAT1022ZD4I−25T3*
SOIC
TSSOP
MSOP
TDFN
3000 Tape & Reel
1. All packages are RoHS−compliant (Lead−free, Halogen−free).
2. The standard lead finish is NiPdAu.
3. For additional package and temperature options, please contact your nearest
ON Semiconductor Sales office.
4. TDFN not available in NiPdAu (–G) version.
5. For detailed information and a breakdown of device nomenclature and numbering
systems, please see the ON Semiconductor Device Nomenclature document,
TND310/D, available at www.onsemi.com
http://onsemi.com
14
CAT1021, CAT1022, CAT1023
Orderable Part Numbers − CAT1023 Series
(See Notes 1 − 5)
Device
Reset Threshold
4.50 V − 4.75 V
4.25 V − 4.50 V
3.00 V − 3.15 V
2.85 V − 3.00 V
2.55 V − 2.70 V
4.50 V − 4.75 V
4.25 V − 4.50 V
3.00 V − 3.15 V
2.85 V − 3.00 V
2.55 V − 2.70 V
4.50 V − 4.75 V
4.25 V − 4.50 V
3.00 V − 3.15 V
2.85 V − 3.00 V
2.55 V − 2.70 V
4.50 V − 4.75 V
4.25 V − 4.50 V
3.00 V − 3.15 V
2.85 V − 3.00 V
2.55 V − 2.70 V
4.50 V − 4.75 V
4.25 V − 4.50 V
3.00 V − 3.15 V
2.85 V − 3.00 V
2.55 V − 2.70 V
Package
Shipping
CAT1023LI−45−G
CAT1023LI−42−G
CAT1023LI−30−G
PDIP
CAT1023LI−28−G
CAT1023LI−25−G
CAT1023WI−45−GT3
CAT1023WI−42−GT3
CAT1023WI−30−GT3
CAT1023WI−28−GT3
CAT1023WI−25−GT3
CAT1023YI−45−GT3
CAT1023YI−42−GT3
CAT1023YI−30−GT3
CAT1023YI−28−GT3
CAT1023YI−25−GT3
CAT1023ZI−45−GT3
CAT1023ZI−42−GT3
CAT1023ZI−30−GT3
CAT1023ZI−28−GT3
CAT1023ZI−25−GT3
CAT1023ZD4I−45T3*
CAT1023ZD4I−42T3*
CAT1023ZD4I−30T3*
CAT1023ZD4I−28T3*
CAT1023ZD4I−25T3*
SOIC
TSSOP
MSOP
TDFN
3000 Tape & Reel
1. All packages are RoHS−compliant (Lead−free, Halogen−free).
2. The standard lead finish is NiPdAu.
3. For additional package and temperature options, please contact your nearest
ON Semiconductor Sales office.
4. TDFN not available in NiPdAu (–G) version.
5. For detailed information and a breakdown of device nomenclature and numbering
systems, please see the ON Semiconductor Device Nomenclature document,
TND310/D, available at www.onsemi.com
http://onsemi.com
15
CAT1021, CAT1022, CAT1023
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
SYMBOL
MIN
NOM
MAX
1.35
A
1.75
A1
b
0.10
0.33
0.19
0.25
0.51
0.25
c
E1
E
D
E
E1
e
4.80
5.80
3.80
5.00
6.20
4.00
1.27 BSC
h
0.25
0.40
0º
0.50
1.27
8º
L
PIN # 1
IDENTIFICATION
θ
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
http://onsemi.com
16
CAT1021, CAT1022, CAT1023
PDIP−8, 300 mils
CASE 646AA−01
ISSUE A
SYMBOL
MIN
NOM
MAX
A
5.33
A1
A2
b
0.38
2.92
0.36
3.30
0.46
1.52
0.25
9.27
4.95
0.56
1.78
0.36
10.16
b2
c
1.14
0.20
9.02
E1
D
E
E1
e
7.62
6.10
7.87
6.35
8.25
7.11
2.54 BSC
7.87
2.92
10.92
3.80
eB
L
PIN # 1
IDENTIFICATION
3.30
D
TOP VIEW
E
A2
A1
A
c
b2
L
eB
e
b
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.
http://onsemi.com
17
CAT1021, CAT1022, CAT1023
MSOP 8, 3x3
CASE 846AD−01
ISSUE O
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
1.10
0.15
0.95
0.38
0.23
3.10
5.00
3.10
0.05
0.75
0.22
0.13
2.90
4.80
2.90
0.10
0.85
c
D
3.00
4.90
E
E1
E
E1
e
3.00
0.65 BSC
0.60
L
0.40
0.80
L1
L2
θ
0.95 REF
0.25 BSC
0º
6º
TOP VIEW
D
A2
A
DETAIL A
A1
e
b
c
SIDE VIEW
END VIEW
q
L2
Notes:
L
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-187.
L1
DETAIL A
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18
CAT1021, CAT1022, CAT1023
TDFN8, 3x3
CASE 511AL−01
ISSUE A
D
A
e
b
L
E
E2
PIN#1 ID
PIN#1 INDEX AREA
A1
D2
TOP VIEW
SIDE VIEW
BOTTOM VIEW
SYMBOL
MIN
0.70
0.00
NOM
MAX
0.80
0.05
A
A1
A3
b
0.75
0.02
0.20 REF
0.30
0.23
2.90
2.20
2.90
1.40
0.37
3.10
2.50
3.10
1.80
A
A3
D
3.00
D2
E
−−−
A1
3.00
FRONT VIEW
E2
e
−−−
0.65 TYP
0.30
L
0.20
0.40
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MO-229.
http://onsemi.com
19
CAT1021, CAT1022, CAT1023
TSSOP−8
CASE 948S−01
ISSUE C
8x K REF
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T U
S
0.20 (0.008) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
8
5
4
2X L/2
B
−U−
J
J1
L
1
PIN 1
IDENT
K1
K
S
0.20 (0.008) T U
A
SECTION N−N
−V−
MILLIMETERS
INCHES
MIN
0.114
DIM MIN
MAX
MAX
0.122
0.177
0.043
0.006
0.028
A
B
2.90
4.30
---
3.10
−W−
4.50 0.169
1.10 ---
C
C
0.076 (0.003)
D
0.05
0.50
0.15 0.002
0.70 0.020
F
DETAIL E
SEATING
D
−T−
G
G
J
0.65 BSC
0.026 BSC
PLANE
0.09
0.09
0.19
0.19
0.20 0.004
0.16 0.004
0.30 0.007
0.25 0.007
0.008
0.006
0.012
0.010
J1
K
0.25 (0.010)
N
K1
L
6.40 BSC
0.252 BSC
0
M
M
0
8
8
_
_
_
_
N
F
DETAIL E
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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CAT1021/D
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