CAT1026UE-25 [ONSEMI]
2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8, TSSOP-8;
| 型号： | CAT1026UE-25 |
| 厂家： | 
ONSEMI |
| 描述： | 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8, TSSOP-8 光电二极管 |
| 文件： | 总19页 (文件大小：192K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT1026, CAT1027
Dual Voltage Supervisory
Circuits with I2C Serial
2k-bit CMOS EEPROM
Description
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The CAT1026 and CAT1027 are complete memory and supervisory
solutions for microcontroller−based systems. A 2k−bit serial
EEPROM memory and a system power supervisor with brown−out
protection are integrated together in low power CMOS technology.
2
Memory interface is via a 400 kHz I C bus.
The CAT1026 and CAT1027 provide a precision VCC sense circuit
with five reset threshold voltage options that support 5 V, 3.3 V and
3 V systems. The power supply monitor and reset circuit protects
memory and systems controllers during power up/down and against
brownout conditions. If power supply voltages are out of tolerance
reset signals become active preventing the system microcontroller,
ASIC, or peripherals from operating.
PDIP−8
CASE 646AA
TSSOP−8
CASE 948S
The CAT1026 features two open drain reset outputs: one (RESET)
drives high and the other (RESET) drives low whenever VCC falls
below the threshold. Reset outputs become inactive typically 200 ms
after the supply voltage exceeds the reset threshold value. With both
active high and low reset signals, interface to microcontrollers and
other ICs is simple. CAT1027 has only a RESET output. In addition,
the RESET pin can be used as an input for push−button manual reset
capability.
SOIC−8
CASE 751BD
MSOP−8
CASE 846AD
TDFN−8
CASE 511AL
The CAT1026 and CAT1027 provide an auxiliary voltage sensor
input, VSENSE, which is used to monitor a second system supply. The
auxiliary high impedance comparator drives the open drain output,
ORDERING INFORMATION
V
LOW
, whenever the sense voltage is below 1.25 V threshold.
The CAT1027 is designed with a 1.6 second watchdog timer circuit
For Ordering Information details, see page 13.
that resets a system to a known state if software or a hardware glitch
halts or “hangs” the system. The CAT1027 features a watchdog timer
interrupt input, WDI.
The on−chip 2k−bit EEPROM memory features a 16−byte page. In addition, hardware data protection is provided by a V
CC
sense circuit that prevents writes to memory whenever V falls below the reset threshold or until VCC reaches the reset
CC
threshold during power up.
Available packages include an 8−pin DIP and surface mount, 8−pin SO, 8−pin TSSOP, 8−pin TDFN and 8−pin MSOP
packages. The TDFN package thickness is 0.8 mm maximum. TDFN footprint is 3 x 3 mm.
Features
• Precision V Power Supply Voltage Monitor
• 16−Byte Page Write Buffer
CC
♦ 5 V, 3.3 V and 3 V Systems
• Built−in Inadvertent Write Protection
• 1,000,000 Program/Erase Cycles
• Manual Reset Capability
♦ Five Threshold Voltage Options
• Additional Voltage Monitoring
♦ Externally Adjustable Down to 1.25 V
• Watchdog Timer (CAT1027 Only)
• 100 Year Data Retention
• Industrial and Extended Temperature Ranges
• Active High or Low Reset
• 8−Pin DIP, SOIC, TSSOP, MSOP or TDFN (3 x 3 mm
♦ Valid Reset Guaranteed at VCC = 1 V
foot−print) Packages
2
• 400 kHz I C Bus
♦ TDFN max Height is 0.8 mm
• These Devices are Pb−Free, Halogen Free/BFR Free
and are RoHS Compliant
• 2.7 V to 5.5 V Operation
• Low Power CMOS Technology
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
November, 2011 − Rev. 18
CAT1026/D
CAT1026, CAT1027
Table 1. RESET THRESHOLD OPTION
Part Dash
Number
Minimum
Threshold
Maximum
Threshold
−45
−42
−30
−28
−25
4.50
4.25
3.00
2.85
2.55
4.75
4.50
3.15
3.00
2.70
BLOCK DIAGRAM
EXTERNAL LOAD
SENSEAMPS
SHIFT REGISTERS
D
OUT
ACK
V
V
CC
SS
WORDADDRESS
BUFFERS
COLUMN
DECODERS
START/STOP
SDA
LOGIC
2kbit
EEPROM
XDEC
CONTROL
LOGIC
DATA IN STORAGE
HIGHVOLTAGE/
TIMING CONTROL
V
CC Monitor
V
CC
STATE COUNTERS
SCL
RESET
SLAVE
+
-
ADDRESS
Controller
WDI
(CAT1027)
COMPARATORS
V
REF
Auxiliary
Voltage Monitor
RESET RESET
(CAT1026)
V
+
-
SENSE
V
LOW
V
REF
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2
CAT1026, CAT1027
PIN CONFIGURATION
DIP Package (L)
SOIC Package (W)
TSSOP Package (Y)
MSOP Package (Z)
(Bottom View)
TDFN Package: 3 mm x 3 mm
0.8 mm maximum height − (ZD4)
V
V
LOW
8
7
6
5
1
2
3
4
CC
V
1
2
3
4
8
7
6
5
V
CC
LOW
RESET
RESET
RESET
RESET
CAT1026
CAT1027
CAT1026
CAT1027
V
SCL
SDA
SENSE
V
SCL
SDA
SENSE
V
SS
V
SS
V
LOW
1
2
3
4
8
7
6
5
V
CC
V
LOW
V
CC
8
7
6
5
1
2
3
4
RESET
WDI
RESET
WDI
V
SCL
SDA
V
SCL
SDA
SENSE
SENSE
V
SS
V
SS
PIN DESCRIPTION
RESET/RESET: RESET OUTPUTs
(RESET CAT1026 Only)
Table 2. PIN FUNCTION
Pin Name
Function
These are open drain pins and RESET can be used as a
manual reset trigger input. By forcing a reset condition on
the pin the device will initiate and maintain a reset condition.
The RESET pin must be connected through a pull−down
resistor, and the RESET pin must be connected through a
pull−up resistor.
RESET
Active Low Reset Input/Output
Ground
V
SS
SDA
SCL
Serial Data/Address
Clock Input
RESET
Active High Reset Output
(CAT1026 Only)
SDA: SERIAL DATA ADDRESS
The bidirectional serial data/address pin is used to transfer
all data into and out of the device. The SDA pin is an open
drain output and can be wire−ORed with other open drain or
open collector outputs.
V
Power Supply
CC
V
Auxiliary Voltage Monitor Input
Auxiliary Voltage Monitor Output
SENSE
V
LOW
SCL: SERIAL CLOCK
Serial clock input.
WDI
Watchdog Timer Interrupt
(CAT1027 Only)
V
SENSE
: AUXILIARY VOLTAGE MONITOR INPUT
The V
input is a second voltage monitor which is
SENSE
Table 3. OPERATING TEMPERATURE RANGE
compared against CAT1026 and CAT1027 internal
reference voltage of 1.25 V typically. Whenever the input
Industrial
Extended
−40°C to 85°C
−40°C to 125°C
voltage is lower than 1.25 V, the open drain V
output
LOW
will be driven low. An external resistor divider is used to set
the voltage level to be sensed. Connect V
unused.
to V if
SENSE
CC
V
LOW
: AUXILIARY VOLTAGE MONITOR OUTPUT
This open drain output goes low when V
is less than
SENSE
1.25 V and goes high when V
voltage.
exceeds the reference
SENSE
WDI (CAT1027 Only): WATCHDOG TIMER
INTERRUPT
Watchdog Timer Interrupt Input is used to reset the
watchdog timer. If a transition from high to low or low to
high does not occur every 1.6 seconds, the RESET outputs
will be driven active.
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CAT1026, CAT1027
Table 4. CAT102X FAMILY OVERVIEW
Device
Manual Reset
Input Pin
Watchdog
Watchdog
Monitor Pin
Write
Protection
Pin
Independent
Auxiliary Voltage
Sense
RESET:
Active High
and LOW
EEPROM
CAT1021
CAT1022
CAT1023
CAT1024
CAT1025
CAT1026
CAT1027
n
n
n
n
n
n
n
n
SDA
SDA
WDI
n
n
2k
2k
2k
2k
2k
2k
2k
n
n
n
n
n
n
n
WDI
NOTE: For supervisory circuits with embedded 16k EEPROM, please refer to the CAT1161, CAT1162 and CAT1163 data sheets.
SPECIFICATIONS
Table 5. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
°C
°C
V
Temperature Under Bias
Storage Temperature
–55 to +125
–65 to +150
Voltage on any Pin with Respect to Ground (Note 1)
with Respect to Ground
−2.0 to V + 2.0
CC
V
CC
−2.0 to 7.0
1.0
V
Package Power Dissipation Capability (T = 25°C)
W
A
Lead Soldering Temperature (10 s)
Output Short Circuit Current (Note 2)
300
°C
mA
100
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum
DC voltage on output pins is V +0.5 V, which may overshoot to V +2.0 V for periods of less than 20 ns.
CC
CC
2. Output shorted for no more than one second. No more than one output shorted at a time.
Table 6. D.C. OPERATING CHARACTERISTICS
V
CC
= 2.7 V to 5.5 V and over the recommended temperature conditions unless otherwise specified.
Symbol
Parameter
Test Conditions
Min
−2
Typ
Max
10
10
3
Units
mA
I
LI
Input Leakage Current
Output Leakage Current
Power Supply Current (Write)
V
V
= GND to V
IN
CC
CC
I
LO
= GND to V
−10
mA
IN
I
f
= 400 kHz
= 5.5 V
mA
CC1
SCL
V
CC
I
Power Supply Current (Read)
Standby Current
f
= 400 kHz
= 5.5 V
1
mA
CC2
SCL
CC
V
I
V
V
= 5.5 V
= GND or V
CAT1026
CAT1027
50
60
mA
mA
V
SB
CC
IN
CC
V
IL
(Note 3)
(Note 3)
Input Low Voltage
Input High Voltage
−0.5
0.3 x V
CC
V
IH
0.7 x V
V + 0.5
CC
V
CC
V
OL
Output Low Voltage
(SDA, RESET)
I
= 3 mA
CC
0.4
V
OL
V
= 2.7 V
V
OH
Output High Voltage
(RESET)
I
= −0.4 mA
CC
V − 0.75
CC
V
OH
V
= 2.7 V
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CAT1026, CAT1027
Table 6. D.C. OPERATING CHARACTERISTICS
V
CC
= 2.7 V to 5.5 V and over the recommended temperature conditions unless otherwise specified.
Symbol
Parameter
Reset Threshold
Test Conditions
CAT102x−45 (V = 5.0 V)
Min
4.50
4.25
3.00
2.85
2.55
1.00
15
Typ
Max
4.75
4.50
3.15
3.00
2.70
Units
V
TH
V
CC
CAT102x−42 (V = 5.0 V)
CC
CAT102x−30 (V = 3.3 V)
CC
CAT102x−28 (V = 3.3 V)
CC
CAT102x−25 (V = 3.0 V)
CC
V
Reset Output Valid V Voltage
V
RVALID
CC
V
(Note 4)
Reset Threshold Hysteresis
mV
VS
RT
V
REF
Auxiliary Voltage Monitor
Threshold
1.2
1.25
1.3
3. V min and V max are reference values only and are not tested.
IL
IH
4. This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested.
Table 7. CAPACITANCE
T = 25°C, f = 1.0 MHz, V = 5 V
A
CC
Symbol
(Note 5)
Test
Test Conditions
= 0 V
OUT
Max
8
Units
pF
C
Output Capacitance
Input Capacitance
V
V
OUT
C
(Note 5)
= 0 V
IN
6
pF
IN
Table 8. AC CHARACTERISTICS
V
CC
= 2.7 V to 5.5 V and over the recommended temperature conditions, unless otherwise specified.
Memory Read & Write Cycle (Note 6)
Symbol
Parameter
Min
Max
400
100
Units
kHz
ns
f
Clock Frequency
SCL
t
SP
Input Filter Spike Suppression (SDA, SCL)
Clock Low Period
t
1.3
0.6
ms
LOW
t
Clock High Period
ms
HIGH
t
(Note 5)
SDA and SCL Rise Time
300
300
ns
R
t (Note 5)
SDA and SCL Fall Time
ns
F
t
Start Condition Hold Time
0.6
0.6
0
ms
HD; STA
t
Start Condition Setup Time (for a Repeated Start)
Data Input Hold Time
ms
SU; STA
HD; DAT
t
ns
t
Data Input Setup Time
100
0.6
ns
SU; DAT
SU; STO
t
Stop Condition Setup Time
ms
t
SCL Low to Data Out Valid
900
5
ns
AA
t
Data Out Hold Time
50
ns
DH
t
(Note 5)
(Note 7)
Time the Bus must be Free Before a New Transmission Can Start
Write Cycle Time (Byte or Page)
1.3
ms
BUF
t
ms
WC
5. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
6. Test Conditions according to “AC Test Conditions” table.
7. The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the
write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.
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CAT1026, CAT1027
Table 9. RESET CIRCUIT AC CHARACTERISTICS
Symbol
Parameter
Test Conditions
Min
Typ
Max
270
5
Units
ms
ms
t
Power−Up Reset Timeout
Note 2
Note 3
130
200
PURST
t
V
V
to RESET output Delay
Glitch Reject Pulse Width
RDP
TH
CC
t
Notes 4 and 5
Note 1
30
2.1
5
ns
GLITCH
t
Watchdog Timeout
to V Delay
1.0
1.6
s
WD
t
V
Note 5
ms
RPD2
SENSE
LOW
Table 10. POWER−UP TIMING (Notes 6 and 7)
Symbol
Parameter
Power−Up to Read Operation
Power−Up to Write Operation
Test Conditions
Min
Typ
Max
270
270
Units
ms
t
PUR
t
ms
PUW
Table 11. AC TEST CONDITIONS
Parameter
Test Conditions
Input Pulse Voltages
0.2 x V to 0.8 x V
CC
CC
Input Rise and Fall Times
Input Reference Voltages
Output Reference Voltages
Output Load
10 ns
0.3 x V , 0.7 x V
CC
CC
0.5 x V
CC
Current Source: I = 3 mA; C = 100 pF
OL
L
Table 12. RELIABILITY CHARACTERISTICS
Symbol
(Note 6)
Parameter
Endurance
Reference Test Method
Min
1,000,000
100
Max
Units
N
MIL−STD−883, Test Method 1033
MIL−STD−883, Test Method 1008
MIL−STD−883, Test Method 3015
JEDEC Standard 17
Cycles/Byte
Years
END
T
(Note 6)
(Note 6)
Data Retention
DR
V
ESD Susceptibility
2000
Volts
ZAP
I
(Notes 6 & 8) Latch−Up
100
mA
LTH
1. Test Conditions according to “AC Test Conditions” table.
2. Power−up, Input Reference Voltage V = V , Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
CC
TH
3. Power−Down, Input Reference Voltage V = V , Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
CC
TH
4. V Glitch Reference Voltage = V
; Based on characterization data
CC
THmin
5. 0 < V
− V , V
Output Reference Voltage and Load according to “AC Test Conditions” Table.
SENSE
CC
LOW
6. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
7. t
and t
are the delays required from the time V is stable until the specified memory operation can be initiated.
PUR
PUW CC
8. Latch−up protection is provided for stresses up to 100 mA on input and output pins from −1 V to V + 1 V.
CC
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CAT1026, CAT1027
DEVICE OPERATON
Reset Controller Description
Data Protection
The CAT1026 and CAT1027 precision RESET
controllers ensure correct system operation during
brownout and power up/down conditions. They are
configured with open drain RESET outputs.
The CAT1026 and CAT1027 devices have been designed
to solve many of the data corruption issues that have long
been associated with serial EEPROMs. Data corruption
occurs when incorrect data is stored in a memory location
which is assumed to hold correct data.
During power−up, the RESET outputs remain active until
V
reaches the V threshold and will continue driving the
Whenever the device is in a Reset condition, the
embedded EEPROM is disabled for all operations,
including write operations. If the Reset output(s) are active,
in progress communications to the EEPROM are aborted
and no new communications are allowed. In this condition
an internal write cycle to the memory can not be started, but
an in progress internal nonvolatile memory write cycle can
not be aborted. An internal write cycle initiated before the
Reset condition can be successfully finished if there is
CC
TH
outputs for approximately 200 ms (t
) after reaching
PURST
V
TH
. After the t
timeout interval, the device will cease
PURST
to drive the reset outputs. At this point the reset outputs will
be pulled up or down by their respective pull up/down
resistors.
During power−down, the RESET outputs will be active
when V falls below V . The RESET output will be valid
so long as V is > 1.0 V (V
CC
TH
). The device is designed
CC
RVALID
to ignore the fast negative going V transient pulses
enough time (5 ms) before V reaches the minimum value
CC
CC
(glitches).
of 2 V.
Reset output timing is shown in Figure 1.
In addition, to avoid data corruption due to the loss of
power supply voltage during the memory internal write
operation, the system controller should monitor the
unregulated DC power. Using the second voltage sensor,
Manual Reset Capability
The RESET pin can operate as reset output and manual
reset input. The input is edge triggered; that is, the RESET
input will initiate a reset timeout after detecting a high to low
transition.
When RESET I/O is driven to the active state, the 200 ms
timer will begin to time the reset interval. If external reset is
shorter than 200 ms, Reset outputs will remain active at least
200 ms.
V , to monitor an unregulated power supply, the
SENSE
CAT1026 and CAT1027 signals an impending power failure
by setting V low.
LOW
Watchdog Timer
The Watchdog Timer provides an independent protection
for microcontrollers. During a system failure, the CAT1027
device will provide a reset signal after a time−out interval of
1.6 seconds for a lack of activity. CAT1027 is designed with
the Watchdog timer feature on the WDI pin. If WDI does not
toggle within 1.6 second intervals, the reset condition will be
generated on reset output. The watchdog timer is cleared by
any transition on monitored line.
Monitoring Two Voltages
The CAT1026 and CAT1027 feature a second voltage
sensor, V
, which drives the open drain V
SENSE
output
LOW
low whenever the input voltage is below 1.25 V. The
auxiliary voltage monitor timing is shown in Figure 2.
By using an external resistor divider the sense circuitry
can be set to monitor a second supply in the system. The
circuit shown in Figure 3 provides an externally adjustable
As long as reset signal is asserted, the watchdog timer will
not count and will stay cleared.
threshold voltage, V
to monitor the auxiliary voltage.
TH_ADJ
The low leakage current at V
allows the use of large
SENSE
value resistors, to reduce the system power consumption.
The V output can be externally connected to the RESET
LOW
output to generate a reset condition when either of the
supplies is invalid. In other applications, V signal can be
LOW
used to interrupt the system controller for an impending
power failure notification.
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RV
L D
T
T
CAT1026, CAT1027
tGLITCH
VTH
V
tRPD
tPUR
VCC
tRPD
tPUR
RESEꢀT
RESET
Figure 1. RESET Output Timing
V
REF
V
SENSE
t
t
t
t
RPD2
RPD2
RPD2
RPD2
V
LOW
Figure 2. Auxiliary Voltage Monitor Timing
V
CC
V
AUX
CAT1026/27
Externally adjustable
threshold
Power Fail
Interrupt
V
LOW
R
1
2
V
TH-ADJ
V
SENSE
R
R
R
2
R
1 +
R
2
+
1
V
= V
×
= 1.25V ×
TH-ADJ
REF
R
R
2
2
Figure 3. Auxiliary Voltage Monitor
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8TH B
T
ACK
CAT1026, CAT1027
EMBEDDED EEPROM OPERATON
The CAT1026 and CAT1027 feature a 2−kbit embedded
serial EEPROM that supports the I C Bus data transmission
2. During a data transfer, the data line must remain
stable whenever the clock line is high. Any
2
protocol. This Inter−Integrated Circuit Bus protocol defines
any device that sends data to the bus to be a transmitter and
any device receiving data to be a receiver. The transfer is
controlled by the Master device which generates the serial
clock and all START and STOP conditions for bus access.
Both the Master device and Slave device can operate as
either transmitter or receiver, but the Master device controls
which mode is activated.
changes in the data line while the clock line is high
will be interpreted as a START or STOP condition.
Start Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of SDA
when SCL is HIGH. The CAT1026 and CAT1027 monitor
the SDA and SCL lines and will not respond until this
condition is met.
I2C Bus Protocol
The features of the I C bus protocol are defined as
Stop Condition
2
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
follows:
1. Data transfer may be initiated only when the bus is
not busy.
DEVICE ADDRESSING
The Master begins a transmission by sending a START
condition. The Master sends the address of the particular
slave device it is requesting. The four most significant bits
of the 8−bit slave address are programmable in metal and the
default is 1010.
The last bit of the slave address specifies whether a Read
or Write operation is to be performed. When this bit is set to
1, a Read operation is selected, and when set to 0, a Write
operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT1026 and CAT1027 monitor the bus
and responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT1026 and CAT 1027 then perform a Read or Write
operation depending on the R/W bit.
t
t
t
F
HIGH
R
t
t
LOW
LOW
SCL
t
t
HD:DAT
SU:STA
t
t
t
t
HD:STA
SU:DAT
SU:STO
SDA IN
BUF
t
AA
t
DH
SDA OUT
Figure 4. Bus Timing
SCL
SDA
BYTE n
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 5. Write Cycle Timing
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CAT1026, CAT1027
ACKNOWLEDGE
After a successful data transfer, each receiving device is
When the CAT1026 and CAT1027 begin a READ mode
it transmits 8 bits of data, releases the SDA line and monitors
the line for an acknowledge. Once it receives this
acknowledge, the CAT1026 and CAT1027 will continue to
transmit data. If no acknowledge is sent by the Master, the
device terminates data transmission and waits for a STOP
condition.
required to generate an acknowledge. The acknowledging
device pulls down the SDA line during the ninth clock cycle,
signaling that it received the 8 bits of data.
The CAT1026 and CAT1027 respond with an
acknowledge after receiving a START condition and its
slave address. If the device has been selected along with a
write operation, it responds with an acknowledge after
receiving each 8−bit byte.
WRITE OPERATIONS
Byte Write
Master device transmits the data to be written into the
addressed memory location. The CAT1026 and CAT1027
acknowledge once more and the Master generates the STOP
condition. At this time, the device begins an internal
programming cycle to non−volatile memory. While the
cycle is in progress, the device will not respond to any
request from the Master device.
In the Byte Write mode, the Master device sends the
START condition and the slave address information (with
the R/W bit set to zero) to the Slave device. After the Slave
generates an acknowledge, the Master sends a 8−bit address
that is to be written into the address pointers of the device.
After receiving another acknowledge from the Slave, the
SDA
SCL
START BIT
STOP BIT
Figure 6. Start/Stop Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 7. Acknowledge Timing
Default Configuration
1
0
1
0
0
0
0
R/W
Figure 8. Slave Address Bits
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CAT1026, CAT1027
Page Write
The CAT1026 and CAT1027 write up to 16 bytes of data
in a single write cycle, using the Page Write operation. The
page write operation is initiated in the same manner as the
byte write operation, however instead of terminating after
the initial byte is transmitted, the Master is allowed to send
up to 15 additional bytes. After each byte has been
transmitted, the CAT1026 and CAT1027 will respond with
an acknowledge and internally increment the lower order
address bits by one. The high order bits remain unchanged.
If the Master transmits more than 16 bytes before sending
the STOP condition, the address counter ‘wraps around’,
and previously transmitted data will be overwritten.
When all 16 bytes are received, and the STOP condition
has been sent by the Master, the internal programming cycle
begins. At this point, all received data is written to the
CAT1026 and CAT1027 in a single write cycle.
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS
DATA
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
Figure 9. Byte Write Timing
S
T
A
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
R
DATAꢁn
DATA nꢀ+ꢀ1
DATA n+15
T
S
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 10. Page Write Timing
Acknowledge Polling
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is issued
to indicate the end of the host’s write operation, the
CAT1026 and CAT1027 initiate the internal write cycle.
ACK polling can be initiated immediately. This involves
issuing the start condition followed by the slave address for
a write operation. If the device is still busy with the write
operation, no ACK will be returned. If a write operation has
completed, an ACK will be returned and the host can then
proceed with the next read or write operation.
READ OPERATIONS
The READ operation for the CAT1026 and CAT1027 is
initiated in the same manner as the write operation with one
exception, the R/W bit is set to one. Three different READ
operations are possible: Immediate/Current Address
READ, Selective/Random READ and Sequential READ.
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11
CAT1026, CAT1027
S
T
A
R
T
S
T
O
P
BUS ꢀACTIVITꢀY:
MASTER
SLꢀAVE
ADDRESS
SDꢀA LINE
S
P
A
C
K
N
O
DATA
A
C
K
SCꢀL
8
9
SDꢀAꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂ8TH BIꢀT
DATA OUꢀT
NO ACK
STOP
Figure 11. Immediate Address Read Timing
Immediate/Current Address Read
again, this time with the R/W bit set to one. The CAT1026
and CAT1027 then respond with its acknowledge and send
the 8−bit byte requested. The master device does not send an
acknowledge but will generate a STOP condition.
The CAT1026 and CAT1027 address counter contains the
address of the last byte accessed, incremented by one. In
other words, if the last READ or WRITE access was to
address N, the READ immediately following would access
data from address N + 1. For N = E = 255, the counter will
wrap around to zero and continue to clock out valid data.
After the CAT1026 and CAT1027 receive its slave address
information (with the R/W bit set to one), it issues an
acknowledge, then transmits the 8−bit byte requested. The
master device does not send an acknowledge, but will
generate a STOP condition.
Sequential Read
The Sequential READ operation can be initiated by either
the Immediate Address READ or Selective READ
operations. After the CAT1026 and CAT1027 sends the
initial 8− bit byte requested, the Master will respond with an
acknowledge which tells the device it requires more data.
The CAT1026 and CAT1027 will continue to output an 8−bit
byte for each acknowledge, thus sending the STOP
condition.
Selective/Random Read
Selective/Random READ operations allow the Master
device to select at random any memory location for a READ
operation. The Master device first performs a ‘dummy’
write operation by sending the START condition, slave
address and byte addresses of the location it wishes to read.
After the CAT1026 and CAT1027 acknowledges, the Master
device sends the START condition and the slave address
The data being transmitted from the CAT1026 and
CAT1027 is sent sequentially with the data from address N
followed by data from address N + 1. The READ operation
address counter increments all of the CAT1026and
CAT1027 address bits so that the entire memory array can
be read during one operation.
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
SLAVE
ADDRESS
SDA LINE
S
S
P
A
C
K
A
C
K
A
C
K
N
O
DATA n
A
C
K
Figure 12. Selective Read Timing
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12
CAT1026, CAT1027
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
Figure 13. Sequential Read Timing
ORDERING INFORMATION
Orderable Part Numbers − CAT1026 Series
(See Notes 1 − 5)
Device
Reset Threshold
4.50 V − 4.75 V
4.25 V − 4.50 V
3.00 V − 3.15 V
2.85 V − 3.00 V
2.55 V − 2.70 V
4.50 V − 4.75 V
4.25 V − 4.50 V
3.00 V − 3.15 V
2.85 V − 3.00 V
2.55 V − 2.70 V
4.50 V − 4.75 V
4.25 V − 4.50 V
3.00 V − 3.15 V
2.85 V − 3.00 V
2.55 V − 2.70 V
4.50 V − 4.75 V
4.25 V − 4.50 V
3.00 V − 3.15 V
2.85 V − 3.00 V
2.55 V − 2.70 V
4.50 V − 4.75 V
4.25 V − 4.50 V
3.00 V − 3.15 V
2.85 V − 3.00 V
2.55 V − 2.70 V
Package
Shipping
CAT1026LI−45−G
CAT1026LI−42−G
CAT1026LI−30−G
PDIP
CAT1026LI−28−G
CAT1026LI−25−G
CAT1026WI−45−GT3
CAT1026WI−42−GT3
CAT1026WI−30−GT3
CAT1026WI−28−GT3
CAT1026WI−25−GT3
CAT1026YI−45−GT3
CAT1026YI−42−GT3
CAT1026YI−30−GT3
CAT1026YI−28−GT3
CAT1026YI−25−GT3
CAT1026ZI−45−GT3
CAT1026ZI−42−GT3
CAT1026ZI−30−GT3
CAT1026ZI−28−GT3
CAT1026ZI−25−GT3
CAT1026ZD4I−45T3*
CAT1026ZD4I−42T3*
CAT1026ZD4I−30T3*
CAT1026ZD4I−28T3*
CAT1026ZD4I−25T3*
SOIC
TSSOP
MSOP
TDFN
3000 Tape & Reel
1. All packages are RoHS−compliant (Lead−free, Halogen−free).
2. The standard lead finish is NiPdAu.
3. For additional package and temperature options, please contact your nearest
ON Semiconductor Sales office.
4. TDFN not available in NiPdAu (–G) version.
5. For detailed information and a breakdown of device nomenclature and numbering
systems, please see the ON Semiconductor Device Nomenclature document,
TND310/D, available at www.onsemi.com
http://onsemi.com
13
CAT1026, CAT1027
Orderable Part Numbers − CAT1027 Series
(See Notes 1 − 5)
Device
Reset Threshold
4.50 V − 4.75 V
4.25 V − 4.50 V
3.00 V − 3.15 V
2.85 V − 3.00 V
2.55 V − 2.70 V
4.50 V − 4.75 V
4.25 V − 4.50 V
3.00 V − 3.15 V
2.85 V − 3.00 V
2.55 V − 2.70 V
4.50 V − 4.75 V
4.25 V − 4.50 V
3.00 V − 3.15 V
2.85 V − 3.00 V
2.55 V − 2.70 V
4.50 V − 4.75 V
4.25 V − 4.50 V
3.00 V − 3.15 V
2.85 V − 3.00 V
2.55 V − 2.70 V
4.50 V − 4.75 V
4.25 V − 4.50 V
3.00 V − 3.15 V
2.85 V − 3.00 V
2.55 V − 2.70 V
Package
Shipping
CAT1027LI−45−G
CAT1027LI−42−G
CAT1027LI−30−G
PDIP
CAT1027LI−28−G
CAT1027LI−25−G
CAT1027WI−45−GT3
CAT1027WI−42−GT3
CAT1027WI−30−GT3
CAT1027WI−28−GT3
CAT1027WI−25−GT3
CAT1027YI−45−GT3
CAT1027YI−42−GT3
CAT1027YI−30−GT3
CAT1027YI−28−GT3
CAT1027YI−25−GT3
CAT1027ZI−45−GT3
CAT1027ZI−42−GT3
CAT1027ZI−30−GT3
CAT1027ZI−28−GT3
CAT1027ZI−25−GT3
CAT1027ZD4I−45T3*
CAT1027ZD4I−42T3*
CAT1027ZD4I−30T3*
CAT1027ZD4I−28T3*
CAT1027ZD4I−25T3*
SOIC
TSSOP
MSOP
TDFN
3000 Tape & Reel
1. All packages are RoHS−compliant (Lead−free, Halogen−free).
2. The standard lead finish is NiPdAu.
3. For additional package and temperature options, please contact your nearest
ON Semiconductor Sales office.
4. TDFN not available in NiPdAu (–G) version.
5. For detailed information and a breakdown of device nomenclature and numbering
systems, please see the ON Semiconductor Device Nomenclature document,
TND310/D, available at www.onsemi.com
http://onsemi.com
14
CAT1026, CAT1027
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
SYMBOL
MIN
NOM
MAX
1.35
A
1.75
A1
b
0.10
0.33
0.19
0.25
0.51
0.25
c
E1
E
D
E
E1
e
4.80
5.80
3.80
5.00
6.20
4.00
1.27 BSC
h
0.25
0.40
0º
0.50
1.27
8º
L
PIN # 1
IDENTIFICATION
θ
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
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15
CAT1026, CAT1027
PDIP−8, 300 mils
CASE 646AA−01
ISSUE A
SYMBOL
MIN
NOM
MAX
A
5.33
A1
A2
b
0.38
2.92
0.36
3.30
0.46
1.52
0.25
9.27
4.95
0.56
1.78
0.36
10.16
b2
c
1.14
0.20
9.02
E1
D
E
E1
e
7.62
6.10
7.87
6.35
8.25
7.11
2.54 BSC
7.87
2.92
10.92
3.80
eB
L
PIN # 1
IDENTIFICATION
3.30
D
TOP VIEW
E
A2
A1
A
c
b2
L
eB
e
b
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.
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16
CAT1026, CAT1027
MSOP 8, 3x3
CASE 846AD−01
ISSUE O
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
1.10
0.15
0.95
0.38
0.23
3.10
5.00
3.10
0.05
0.75
0.22
0.13
2.90
4.80
2.90
0.10
0.85
c
D
3.00
4.90
E
E1
E
E1
e
3.00
0.65 BSC
0.60
L
0.40
0.80
L1
L2
θ
0.95 REF
0.25 BSC
0º
6º
TOP VIEW
D
A2
A
DETAIL A
A1
e
b
c
SIDE VIEW
END VIEW
q
L2
Notes:
L
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-187.
L1
DETAIL A
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17
CAT1026, CAT1027
TDFN8, 3x3
CASE 511AL−01
ISSUE A
D
A
e
b
L
E
E2
PIN#1 ID
PIN#1 INDEX AREA
A1
D2
TOP VIEW
SIDE VIEW
BOTTOM VIEW
SYMBOL
MIN
0.70
0.00
NOM
MAX
0.80
0.05
A
A1
A3
b
0.75
0.02
0.20 REF
0.30
0.23
2.90
2.20
2.90
1.40
0.37
3.10
2.50
3.10
1.80
A
A3
D
3.00
D2
E
−−−
A1
3.00
FRONT VIEW
E2
e
−−−
0.65 TYP
0.30
L
0.20
0.40
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MO-229.
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18
CAT1026, CAT1027
TSSOP−8
CASE 948S−01
ISSUE C
8x K REF
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T U
S
0.20 (0.008) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
8
5
4
2X L/2
B
−U−
J
J1
L
1
PIN 1
IDENT
K1
K
S
0.20 (0.008) T U
A
SECTION N−N
−V−
MILLIMETERS
INCHES
MIN
0.114
DIM MIN
MAX
MAX
0.122
0.177
0.043
0.006
0.028
A
B
2.90
4.30
---
3.10
−W−
4.50 0.169
1.10 ---
C
C
0.076 (0.003)
D
0.05
0.50
0.15 0.002
0.70 0.020
F
DETAIL E
SEATING
D
−T−
G
G
J
0.65 BSC
0.026 BSC
PLANE
0.09
0.09
0.19
0.19
0.20 0.004
0.16 0.004
0.30 0.007
0.25 0.007
0.008
0.006
0.012
0.010
J1
K
0.25 (0.010)
N
K1
L
6.40 BSC
0.252 BSC
0
M
M
0
8
8
_
_
_
_
N
F
DETAIL E
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CAT1026/D
相关型号：
CAT1026UE-45TE13
IC 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8, TSSOP-8, Power Management Circuit
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