CAT150021JWI-G [ONSEMI]
IC,SERIAL EEPROM,256X8,CMOS,SOP,8PIN,PLASTIC;
| 型号： | CAT150021JWI-G |
| 厂家： | 
ONSEMI |
| 描述： | IC,SERIAL EEPROM,256X8,CMOS,SOP,8PIN,PLASTIC 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总15页 (文件大小：169K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT15002, CAT15004
Voltage Supervisor with 2-Kb and 4-Kb SPI
Serial CMOS EEPROM
FEATURES
DESCRIPTION
The CAT15002/04 (see table below) are memory and
supervisory solutions for microcontroller based
systems. A CMOS serial EEPROM memory and a
system power supervisor with brown-out protection
are integrated together. Memory interface is via SPI
bus serial interface.
Precision Power Supply Voltage Monitor
5V, 3.3V, 3V & 2.5V systems
7 threshold voltage options
Active High or Low Reset
Valid reset guaranteed at VCC = 1V
10MHz SPI compatible
The CAT15002/04 provides a precision VCC sense
circuit with two reset output options: CMOS active low
output or CMOS active high. The RESET output is
active whenever VCC is below the reset threshold or
falls below the reset threshold voltage.
16-byte page write buffer
Low power CMOS technology
1,000,000 Program/Erase cycles
100 year data retention
The power supply monitor and reset circuit protect
system controllers during power up/down and against
brownout conditions. Seven reset threshold voltages
support 5V, 3.3V, 3V and 2.5V systems. If power
supply voltages are out of tolerance reset signals
become active, preventing the system microcontroller,
ASIC or peripherals from operating. Reset signals
become inactive typically 240ms after the supply
voltage exceeds the reset threshold level.
Industrial temperature range
RoHS-compliant 8-pin SOIC package
For Ordering Information details, see page 14.
PIN CONFIGURATION
SOIC (W)
MEMORY SIZE SELECTOR
¯¯
CS
1
2
3
4
8
7
6
5
VCC
Product
15002
Memory density
2-Kbit
¯¯¯¯
SO
RST/RST
¯¯¯
WP
SCK
15004
4-Kbit
SI
VSS
PIN FUNCTION
THRESHOLD SUFFIX SELECTOR
Pin Name
Function
Nominal Threshold
Voltage
Threshold Suffix
Designation
¯¯
CS
Chip Select
4.63V
4.38V
4.00V
3.08V
2.93V
2.63V
2.32V
L
M
J
SO
Serial Data Output
Write Protect
Ground
¯¯¯
WP
VSS
SI
T
S
R
Z
Serial Data Input
Serial Clock Input
Reset Output
Power Supply
SCK
¯¯¯¯
RST/RST
VCC
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
1
Doc. No. MD-1126 Rev. B
CAT15002, CAT15004
BLOCK DIAGRAM
VCC
SO
SCK
SI
VOLTAGE
DETECTOR
EEPROM
RST or RST
CS
WP
VSS
ABSOLUTE MAXIMUM RATINGS(1)
Parameters
Ratings
Units
°C
Storage Temperature
Voltage on Any Pin with Respect to Ground(2)
-65 to +150
-0.5 to +6.5
V
RELIABILITY CHARACTERISTICS(3)
Symbol Parameter
NEND(4) Endurance
Min
1,000,000
100
Units
Program/ Erase Cycles
Years
TDR
Data Retention
D.C. OPERATING CHARACTERISTICS
VCC = +2.5V to +5.5V unless otherwise specified.
Limits
Min.
Typ.
Max.
2
Symbol Parameter
ICC Supply Current
Test Condition
Units
Read or Write at 10MHz, SO open
mA
¯¯
12
10
25
20
2
VCC < 5.5V; VIN = VSS or VCC, CS = VCC
ISB
Standby Current
μA
¯¯
CC < 3.6V; VIN = VSS or VCC, CS = VCC
V
IL
I/O Pin Leakage
Pin at GND or VCC
μA
VIL
Input Low Voltage
-0.5
0.3 VCC
V
VIH
VOL
VOH
Input High Voltage
Output Low Voltage
0.7 VCC
VCC + 0.5
0.4
V
V
V
VCC ≥ 2.5V, IOL = 3.0mA
VCC ≥ 2.5V, IOH = -1.6mA
Output High Voltage VCC - 0.8
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The DC input voltage on any pin should not be lower than -0.5V or higher than VCC + 0.5V. During transitions, the voltage on any pin may
undershoot to no less than -1.5V or overshoot to no more than VCC + 1.5V, for periods of less than 20ns.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Page Mode, VCC = 5V, 25°C
Doc. No. MD-1126 Rev. B
2
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT15002, CAT15004
A.C. CHARACTERISTICS (MEMORY)(1)
VCC = 2.5V to 5.5V, TA = -40°C to 85°C, unless otherwise specified.
Symbol Parameter
Min.
DC
20
Max.
Units
MHz
ns
fSCK
tSU
tH
Clock Frequency
Data Setup Time
Data Hold Time
SCK High Time
SCK Low Time
10
20
ns
tWH
tWL
tLZ
40
ns
40
ns
¯¯¯¯¯
HOLD to Output Low Z
25
2
ns
(2)
tRI
Input Rise Time
Input Fall Time
µs
(2)
tFI
2
µs
¯¯¯¯¯
tHD
tCD
0
ns
HOLD Setup Time
¯¯¯¯¯
HOLD Hold Time
10
ns
tV
Output Valid from Clock Low
Output Hold Time
40
ns
tHO
0
ns
tDIS
tHZ
Output Disable Time
20
25
ns
¯¯¯¯¯
HOLD to Output High Z
ns
¯¯
tCS
15
15
15
10
10
ns
CS High Time
¯¯
tCSS
tCSH
tWPS
tWPH
ns
CS Setup Time
¯¯
ns
CS Hold Time
¯¯¯
ns
WP Setup Time
¯¯¯
WP Hold Time
ns
(4)
tWC
Write Cycle Time
5
1
ms
ms
(2) (3)
tPU
Power-up to Ready Mode
Notes:
(1) Test conditions according to “A.C. Test Conditions” table.
(2) Tested initially and after a design or process change that affects this parameter.
(3) tPU is the delay between the time VCC is stable and the device is ready to accept commands.
¯¯
tWC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
(4)
A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Levels
≤ 10ns
0.3 VCC to 0.7 VCC
Timing Reference Levels
Output Load
0.5 VCC
Current Source: IOL max/ IOH max; CL = 50pF
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
3
Doc. No. MD-1126 Rev. B
CAT15002, CAT15004
ELECTRICAL CHARACTERISTICS (SUPERVISORY FUNCTION)
VCC = Full range, TA = -40°C to +85°C unless otherwise noted. Typical values at TA = +25°C and VCC = 5V for
L/M/J versions, VCC = 3.3V for T/S versions, VCC = 3V for R version and VCC = 2.5V for Z version.
Symbol
Parameter
Threshold Conditions
Min
Typ
Max Units
4.70
VTH
Reset Threshold Voltage
TA = +25°C
L
4.56
4.50
4.31
4.25
3.93
3.89
3.04
3.00
2.89
2.85
2.59
2.55
2.28
2.25
4.63
TA = -40°C to +85°C
4.75
TA = +25°C
4.38
4.00
3.08
2.93
2.63
2.32
4.45
M
J
TA = -40°C to +85°C
TA = +25°C
4.50
4.06
TA = -40°C to +85°C
TA = +25°C
4.10
3.11
V
T
S
R
Z
TA = -40°C to +85°C
TA = +25°C
3.15
2.96
3.00
2.66
2.70
2.35
2.38
TA = -40°C to +85°C
TA = +25°C
TA = -40°C to +85°C
TA = +25°C
TA = -40°C to +85°C
Symbol Parameter
Reset Threshold Tempco
VCC to Reset Delay(2)
Conditions
Min
Typ(1) Max Units
30
20
ppm/°C
µs
tRPD
VCC = VTH to (VTH -100mV)
TA = -40°C to +85°C
tPURST Reset Active Timeout Period
140
240
460
0.3
0.4
0.3
ms
V
VCC = VTH min, ISINK = 1.2mA
R/S/T/Z
¯¯¯¯¯¯
RESET Output Voltage Low
VCC = VTH min, ISINK = 3.2mA
J/L/M
(Push-pull, active LOW,
CAT150xx9)
VOL
VCC > 1.0V, ISINK = 50µA
VCC = VTH max, ISOURCE = -500µA
R/S/T/Z
0.8VCC
¯¯¯¯¯¯
(Push-pull, active LOW,
CAT150xx9)
RESET Output Voltage High
VOH
V
VCC = VTH max, ISOURCE = -800µA
J/L/M
VCC - 1.5
VCC > VTH max, ISINK = 1.2mA
R/S/T/Z
RESET Output Voltage Low
0.3
0.4
VOL
V
V
(Push-pull, active HIGH,
CAT150xx1)
VCC > VTH max, ISINK = 3.2mA
J/L/M
RESET Output Voltage High
1.8V < VCC ≤ VTH min,
ISOURCE = -150µA
VOH
0.8VCC
(Push-pull, active HIGH,
CAT150xx1)
Notes:
(1) Production testing done at TA = +25ºC; limits over temperature guaranteed by design only.
(2) RESET output for the CAT150xx9; RESET output for the CAT150xx1.
Doc. No. MD-1126 Rev. B
4
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT15002, CAT15004
PIN DESCRIPTION
DEVICE OPERATION
¯¯¯¯¯¯
RESET/RESET: Reset output is available in two
The CAT15002/04 products combine the accurate
voltage monitoring capabilities of a standalone voltage
supervisor with the high quality and reliability of
standard EEPROMs from Catalyst Semiconductor.
versions: CMOS Active Low (CAT150xx9) and CMOS
Active High (CAT150xx1). Both versions are push-pull
outputs for high efficiency.
SI: The serial data input pin accepts op-codes,
addresses and data. In SPI modes (0,0) and (1,1)
input data is latched on the rising edge of the SCK
clock input.
RESET CONTROLLER DESCRIPTION
The reset signal is asserted LOW for the CAT150xx9
and HIGH for the CAT150xx1 when the power supply
voltage falls below the threshold trip voltage and
remains asserted for at least 140ms (tPURST) after the
power supply voltage has risen above the threshold.
Reset output timing is shown in Figure 1.
SO: The serial data output pin is used to transfer data
out of the device. In SPI modes (0,0) and (1,1) data is
shifted out on the falling edge of the SCK clock.
SCK: The serial clock input pin accepts the clock
provided by the host and used for synchronizing
communication between host and CAT15002/04.
The CAT15002/04 devices protect µPs against brown-out
failure. Short duration VCC transients of 4µsec or less and
100mV amplitude typically do not generate a Reset pulse.
¯¯
CS: The chip select input pin is used to enable/disable
¯¯
the CAT15002/04. When CS is high, the SO output is
tri-stated (high impedance) and the device is in
Standby Mode (unless an internal write operation is in
progress). Every communication session between host
and CAT15002/04 must be preceded by a high to low
transition and concluded with a low to high transition of
¯¯
the CS input.
¯¯¯
WP: The write protect input pin will allow all write
¯¯¯
operations to the device when held high. When WP
pin is tied low all write operations are inhibited.
VTH
VCC
V
RVALID
tRPD
tPURST
tRPD
tPURST
RESET
RESET
CAT150xx9
CAT150xx1
Figure 1. RESET Output Timing
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
5
Doc. No. MD-1126 Rev. B
CAT15002, CAT15004
Figure 2 shows the maximum pulse duration of
negative-going VCC transients that do not cause a reset
condition. As the amplitude of the transient goes further
below the threshold (increasing VTH - VCC), the
maximum pulse duration decreases. In this test, the
VCC starts from an initial voltage of 0.5V above the
threshold and drops below it by the amplitude of the
overdrive voltage (VTH - VCC).
EMBEDDED EEPROM DESCRIPTION
The CAT15002/04 devices support the Serial Peripheral
Interface (SPI) bus protocol, modes (0,0) and (1,1). The
device contains an 8-bit instruction register. The
instruction set and associated op-codes are listed in
Table 1.
Reading data stored in the CAT15002/04 is accom–
plished by simply providing the READ command and an
address. Writing to the CAT15002/04, in addition to a
WRITE command, address and data, also requires
enabling the device for writing by first setting certain bits
in a Status Register, as will be explained later.
T
AMB
= 25ºC
¯¯
After a high to low transition on the CS input pin, the
CAT15002/04 will accept any one of the six instruction
op-codes listed in Table 1 and will ignore all other
possible 8-bit combinations. The communication
protocol follows the timing from Figure 3.
CAT150xxZ
CAT150xxM
Table 1: Instruction Set
Instruction
WREN
WRDI
Opcode
Operation
0000 0110 Enable Write Operations
0000 0100 Disable Write Operations
0000 0101 Read Status Register
0000 0001 Write Status Register
0000 x011 Read Data from Memory
0000 x010 Write Data to Memory
RESET OVERDRIVE V - V
[mV]
TH
CC
RDSR
Figure 2. Maximum Transient Duration without
Causing a Reset Pulse vs. Overdrive Voltage
WRSR
READ
WRITE
Note:
x = 0 for CAT15002,
x = A8 for CAT15004
Figure 3. Synchronous Data Timing
t
CS
V
IH
CS
V
IL
t
t
CSH
CSS
V
V
IH
t
t
WL
SCK
SI
WH
t
IL
t
H
SU
V
IH
VALID IN
V
IL
t
RI
FI
t
t
V
t
t
HO
DIS
V
OH
HI-Z
HI-Z
SO
V
OL
Note: Dashed Line = mode (1, 1) - - - - - -
Doc. No. MD-1126 Rev. B
6
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT15002, CAT15004
STATUS REGISTER
The Status Register, as shown in Table 2, contains a
number of status and control bits.
in a Write Enable state and when set to 0, the device
is in a Write Disable state.
¯¯¯¯
The RDY (Ready) bit indicates whether the device is
The BP0 and BP1 (Block Protect) bits determine
which blocks are currently write protected. They are
set by the user with the WRSR command and are
non-volatile. The user is allowed to protect a quarter,
one half or the entire memory, by setting these bits
according to Table 3. The protected blocks then
become read-only.
busy with a write operation. This bit is automatically
set to 1 during an internal write cycle, and reset to 0
when the device is ready to accept commands. For
the host, this bit is read only.
The WEL (Write Enable Latch) bit is set/reset by the
WREN/WRDI commands. When set to 1, the device is
Table 2. Status Register
7
1
6
1
5
1
4
1
3
2
1
0
¯¯¯¯
RDY
BP1
BP0
WEL
Table 3. Block Protection Bits
Status Register Bits
Array Address Protected
Protection
BP1
BP0
0
0
None
No Protection
15002: C0-FF
15004: 180-1FF
15002: 80-FF
15004: 100-1FF
15002: 00-FF
15004: 000-1FF
0
1
1
1
0
1
Quarter Array Protection
Half Array Protection
Full Array Protection
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
7
Doc. No. MD-1126 Rev. B
CAT15002, CAT15004
WRITE OPERATIONS
¯¯
The CAT15002/04 device powers up into a write disable
state. The device contains a Write Enable Latch (WEL)
which must be set before attempting to write to the
memory array or to the status register. In addition, the
address of the memory location(s) to be written must be
outside the protected area, as defined by BP0 and BP1
bits from the status register.
take the CS input high after the WREN instruction, as
otherwise the Write Enable Latch will not be properly
set. WREN timing is illustrated in Figure 4. The WREN
instruction must be sent prior any WRITE or WRSR
instruction.
The internal write enable latch is reset by sending the
WRDI instruction as shown in Figure 5. Disabling write
operations by resetting the WEL bit, will protect the
device against inadvertent writes.
Write Enable and Write Disable
The internal Write Enable Latch and the corresponding
Status Register WEL bit are set by sending the WREN
instruction to the CAT15002/04. Care must be taken to
Figure 4. WREN Timing
CS
SCK
1
1
0
SI
0
0
0
0
0
HIGH IMPEDANCE
SO
Note: Dashed Line = mode (1, 1) - - - - - -
Figure 5. WRDI Timing
CS
SCK
SI
1
0
0
0
0
0
0
0
HIGH IMPEDANCE
SO
Note: Dashed Line = mode (1, 1) - - - - - -
Doc. No. MD-1126 Rev. B
8
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT15002, CAT15004
Byte Write
Page Write
Once the WEL bit is set, the user may execute a write
sequence, by sending a WRITE instruction, an 8-bit
address and data as shown in Figure 6 (for the
CAT15004, bit 3 of the Write instruciton opcode
contains address bit A8). Internal programming will
After sending the first data byte to the CAT15002/04,
the host may continue sending data, up to a total of 32
bytes, according to timing shown in Figure 7. After
each data byte, the lower order address bits are
automatically incremented, while the higher order
address bits (page address) remain unchanged. If
during this process the end of page is exceeded, then
loading will “roll over” to the first byte in the page, thus
possibly overwriting previoualy loaded data. Following
completion of the write cycle, the CAT15002/04 is
automatically returned to the write disable state.
¯¯
start after the low to high CS transition. During an
internal write cycle, all commands, except for RDSR
¯¯¯¯
(Read Status Register) will be ignored. The RDY bit
will indicate if the internal write cycle is in progress
¯¯¯¯
(RDY high), or the the device is ready to accept
¯¯¯¯
commands (RDY low).
Figure 6. Byte WRITE Timing
CS
0
1
2
3
4
5
6
7
8
13 14 15 16 17 18 19 20 21 22 23
SCK
SI
OPCODE
X*
BYTE ADDRESS
DATA IN
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
1
0
A7
A0
HIGH IMPEDANCE
SO
Notes:
* X = 0 for CAT15002; X = A8 for CAT15004
Dashed Line = mode (1, 1) - - - - - -
Figure 7. Page WRITE Timing
CS
16+(N-1)x8-1..16+(N-1)x8 16+Nx8-1
0
1
2
3
4
5
6
7
8
13 14 15
16-23
24-31
SCK
SI
DATA IN
Data Data
Byte 2 Byte 3
BYTE ADDRESS
OPCODE
Data
Data Byte N
0
0
0
0
X*
0
1
0
A7
A0
0
Byte 1
7..1
HIGH IMPEDANCE
SO
Notes:
* X = 0 for CAT15002; X = A8 for CAT15004
Dashed Line = mode (1, 1) - - - - - -
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
9
Doc. No. MD-1126 Rev. B
CAT15002, CAT15004
Write Status Register
Write Protection
¯¯¯
The Write Protect (WP) pin can be used to disable all
¯¯¯
write operations when held low. WP going low while
The Status Register is written by sending a WRSR
instruction according to timing shown in Figure 8.
Only bits 2 and 3 can be written using the WRSR
command.
¯¯
CS is still low will interrupt
a
write to the
CAT15002/04. If the internal write cycle has already
¯¯¯
been initiated, WP going low will have no effect on any
¯¯¯
write operation. The WP input timing is shown in
Figure 9.
Figure 8. WRSR Timing
CS
0
1
2
3
4
5
6
7
1
8
9
6
10
5
11
4
12
13
2
14
1
15
0
SCK
OPCODE
DATA IN
SI
0
0
0
0
0
0
0
7
3
MSB
HIGH IMPEDANCE
SO
Note: Dashed Line = mode (1, 1) - - - - - -
¯¯¯
Figure 9. WP Timing
t
t
WPH
WPS
CS
SCK
WP
WP
Note: Dashed Line = mode (1, 1) - - - - - -
Doc. No. MD-1126 Rev. B
10
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT15002, CAT15004
READ OPERATIONS
reaching the highest memory address, the address
counter “rolls over” to the lowest memory address, and
the read cycle can be continued indefinitely. The read
Read from Memory Array
To read from memory, the host sends a READ
instruction followed by an 8-bit address (for the
CAT15008, bit 3 of the Read instruction opcode
contains address bit A8).
¯¯
operation is terminated by taking CS high.
Read Status Register
To read the status register, the host simply sends a
RDSR command. After receiving the last bit of the
command, the CAT15002/04 will shift out the contents
of the status register on the SO pin (Figure 11). The
status register may be read at any time, including
during an internal write cycle.
After receiving the last address bit, the CAT15002/04
will respond by shifting out data on the SO pin (as
shown in Figure 10). Sequentially stored data can be
read out by simply continuing to run the clock. The
internal address pointer is automatically incremented
to the next higher address as data is shifted out. After
Figure 10. READ Timing
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22
SCK
BYTE ADDRESS
A7 A6 A5 A4 A3 A2 A1 A0
OPCODE
SI
0
0
0
0
X
*
0
1
1
DATA OUT
HIGH IMPEDANCE
SO
D7 D6 D5 D4 D3 D2 D1 D0
MSB
Notes:
* Please check the instruction set table for address
X = 0 for CAT15002; X=A8 for CAT15004
Dashed Line = mode (1, 1) - - - - - -
Figure 11. RDSR Timing
CS
0
1
2
3
4
5
1
6
0
7
1
8
9
10
11
12
13
14
SCK
OPCODE
0
0
0
0
0
SI
DATA OUT
HIGH IMPEDANCE
SO
5
7
6
4
3
2
1
0
MSB
Note: Dashed Line = mode (1, 1) - - - - - -
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
11
Doc. No. MD-1126 Rev. B
CAT15002, CAT15004
PACKAGE OUTLINE DRAWING
SOIC 8-Lead 150 mil (W)
E1
E
h x 45
D
C
A
q1
e
A1
L
b
SYMBOL
MIN
0.10
1.35
0.33
0.19
4.80
5.80
3.80
NOM
MAX
0.25
1.75
0.51
0.25
5.00
6.20
4.00
A1
A
b
C
D
E
E1
e
1.27 BSC
h
0.25
0.40
0°
0.50
1.27
8°
L
q1
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC specification MS-012 dimensions.
Doc. No. MD-1126 Rev. B
12
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT15002, CAT15004
PACKAGE MARKING
8-LEAD SOIC
150XXZWI
4YYWWA
○
CSI = Catalyst Semiconductor, Inc.
XX = Device Code (see Marking Code table below)
Z = Supervisory Output Code (see Marking Code table below)
I = Temperature Range
YY = Production Year
WW = Production Week
A = Product Revision
4 = Lead Finish NiPdAu
Device Marking Codes
XX
15002
15004
02
04
Supervisory Marking Codes
Z
output active low
output active high
9
1
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
13
Doc. No. MD-1126 Rev. B
CAT15002, CAT15004
EXAMPLE OF ORDERING INFORMATION
Prefix
Device # Suffix
15002
CAT
9
S
W
I
-
G
T3
Lead Finish
G: NiPdAu
Company ID
Temperature Range
Tape & Reel
I = Industrial (-40ºC to 85ºC)
T: Tape & Reel
3: 3000 units / Reel
Product Type with
Memory Density
15002: 2-Kb EEPROM
15004: 4-Kb EEPROM
Package
W: SOIC
Reset Threshold Voltage
L: 4.50V – 4.75V
M: 4.25V – 4.50V
J: 3.89V – 4.10V
T: 3.00V – 3.15V
S: 2.85V – 3.00V
R: 2.55V – 2.70V
Z: 2.25V – 2.38V
Supervisor Output Type
9: CMOS Active Low
1: CMOS Active High
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The standard lead finish is NiPdAu pre-plated (PPF) lead frames.
(3) The device used in the above example is a CAT150029SWI-GT3 (2-Kb EEPROM, with Active Low CMOS Reset output, with a reset threshold
between 2.85V - 3.00V, in SOIC package, Industrial Temperature, NiPdAu, Tape and Reel.
(4) For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.
Doc. No. MD-1126 Rev. B
14
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT15002, CAT15004
REVISION HISTORY
Date
Rev. Description
16-Jan-07
10-Nov-08
A
B
Initial Issue
Change logo and fine print to ON Semiconductor
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to
any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated
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PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800-282-9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center:
Phone: 81-3-5773-3850
ON Semiconductor Website: www.onsemi.com
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada
Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
15
Doc. No. MD-1126 Rev. B
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