CAT1640JI-45TE13 [ONSEMI]
1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8, MS-012, SOIC-8;
| 型号： | CAT1640JI-45TE13 |
| 厂家： | 
ONSEMI |
| 描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8, MS-012, SOIC-8 光电二极管 |
| 文件： | 总18页 (文件大小：175K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT1640, CAT1641
Supervisory Circuits with
I2C Serial 64K CMOS
EEPROM
Description
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The CAT1640 and CAT1641 are complete memory and supervisory
solutions for microcontroller−based systems. A 64 kbit serial
EEPROM memory and a system power supervisor with brown−out
protection are integrated together in low power CMOS technology.
2
Memory interface is via a 400 kHz I C bus.
The CAT1640 provides a precision V sense circuit and drives an
CC
open drain output, RESET low whenever V falls below the reset
PDIP−8
CASE 646AA
TSSOP−8
CASE 948S
CC
threshold voltage.
The CAT1641 provides a precision VCC sense circuit that drives an
open drain output, RESET high whenever V falls below the reset
CC
threshold voltage.
The power supply monitor and reset circuit protect memory and
system controllers during power up/down and against brownout
conditions. Five reset threshold voltages support 5 V, 3.3 V and 3 V
systems. If power supply voltages are out of tolerance reset signals
become active, preventing the system microcontroller, ASIC or
peripherals from operating. Reset signals become inactive typically
200 ms after the supply voltage exceeds the reset threshold level. With
both active high and low reset options, interface to microcontrollers
and other ICs is simple. In addition, the RESET (CAT1640) pin can be
used as an input for push−button manual reset capability.
SOIC−8
CASE 751BD
TDFN−8
CASE 511AM
ORDERING INFORMATION
For Ordering Information details, see page 13.
The CAT1640/41 memory features a 64−byte page. In addition,
hardware data protection is provided by a V sense circuit that
CC
prevents writes to memory whenever VCC falls below the reset
threshold or until V reaches the reset threshold during power up.
CC
Available packages include an 8−pin DIP, SOIC, TSSOP and
4.9 x 3 mm TDFN.
Features
• Precision Power Supply Voltage Monitor
♦ 5 V, 3.3 V and 3 V Systems
S +5.0 V ( 5%, 10%)
• 3.0 V to 5.5 V Operation
• Low Power CMOS Technology
• 64−Byte Page Write Buffer
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
S +3.3 V ( 5%, 10%)
S +3.0 V ( 10%)
• Active Low Reset, CAT1640
• Active High Reset, CAT1641
• 8−pin DIP, SOIC, TSSOP and TDFN Packages
• Industrial Temperature Range
• Valid Reset Guaranteed at V = 1 V
CC
• These Devices are Pb−Free, Halogen Free/BFR Free
2
• 400 kHz I C Bus
and are RoHS Compliant
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
November, 2011 − Rev. 5
CAT1640/D
CAT1640, CAT1641
Table 1. THRESHOLD VOLTAGE OPTION
Part Dash
Number
Minimum
Threshold
Maximum
Threshold
−45
−42
−30
−28
−25
4.50
4.25
3.00
2.85
2.55
4.75
4.50
3.15
3.00
2.70
BLOCK DIAGRAM
EXTERNAL LOAD
SENSEAMPS
SHIFT REGISTERS
D
OUT
ACK
V
V
CC
SS
WORDADDRESS
BUFFERS
COLUMN
DECODERS
START/STOP
SDA
LOGIC
2kbit
EEPROM
XDEC
CONTROL
LOGIC
DATA IN STORAGE
HIGHVOLTAGE/
TIMING CONTROL
RESET Controller
STATE COUNTERS
SCL
A0
Precision
SLAVE
ADDRESS
COMPARATORS
A1
A2
Vcc Monitor
RESET (CAT1640)
RESET (CAT1641)
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2
CAT1640, CAT1641
PIN CONFIGURATION
PDIP (L)
SOIC (W)
TDFN Package: 4.9 mm x 3 mm
(ZD2)
TSSOP (Y)
1
2
3
4
8
7
6
5
A0
A1
A2
V
CC
V
8
7
6
5
V
CC
8
7
6
5
1
2
3
4
1
2
A0
A1
A2
A0
A1
CC
RESET
SCL
RESET
SCL
RESET
SCL
CAT1640
CAT1641
CAT1640
CAT1641
CAT1640
A2 3
V
SS
V
SS
V
SS
SDA
SDA
4
SDA
V
CC
A0
A1
A2
8
7
6
5
1
2
3
4
V
CC
8
1
2
3
4
V
CC
8
7
6
5
A0
A1
A2
1
2
3
4
A0
A1
A2
RESET
SCL
RESET
SCL
7
6
5
RESET
SCL
CAT1641
V
SS
V
SS
V
SS
SDA
SDA
SDA
PIN DESCRIPTION
RESET/RESET: RESET OUTPUTS
Table 2. PIN FUNCTION
Pin Name
These are open drain pins and RESET can be used as a
manual reset trigger input. By forcing a reset condition on
the pin the device will initiate and maintain a reset condition.
The RESET pin must be connected through a pull−down
resistor, and the RESET pin must be connected through a
pull−up resistor.
Function
RESET
Active Low Reset Input/Output
(CAT1640)
V
SS
Ground
SDA
SCL
Serial Data/Address
Clock Input
SDA: SERIAL DATA ADDRESS
The bidirectional serial data/address pin is used to transfer
all data into and out of the device. The SDA pin is an open
drain output and can be wire−ORed with other open drain or
open collector outputs.
RESET
Active High Reset Output
(CAT1641)
V
CC
Power Supply
SCL: SERIAL CLOCK
Serial clock input.
Table 3. OPERATING TEMPERATURE RANGE
Industrial
−40°C to 85°C
A0, A1, A2: DEVICE ADDRESS INPUTs
When hardwired, up to eight CAT1640/41 devices may be
addressed on a single bus system (refer to Device
Addressing). When the pins are left unconnected, the default
values are zeros.
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3
CAT1640, CAT1641
SPECIFICATIONS
Table 4. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
–40 to +85
–65 to +105
Units
°C
°C
V
Temperature Under Bias
Storage Temperature
Voltage on any Pin with Respect to Ground (Note 1)
−0.5 to V + 2.0
CC
V
with Respect to Ground
−0.5 to +7.0
1.0
V
CC
Package Power Dissipation Capability (T = 25°C)
W
A
Lead Soldering Temperature (10 seconds)
Output Short Circuit Current (Note 1)
300
°C
mA
100
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Output shorted for no more than one second. No more than one output shorted at a time.
Table 5. D.C. OPERATING CHARACTERISTICS
V
CC
= +3.0 V to +5.5 V and over the recommended temperature conditions unless otherwise specified.
Symbol
Parameter
Input Leakage Current
Test Conditions
Min
−2
Typ
Max
10
10
3
Units
mA
I
LI
V
V
= GND to V
= GND to V
IN
CC
CC
I
LO
Output Leakage Current
−10
mA
IN
I
Power Supply Current (Write)
f
= 400 kHz
= 5.5 V
mA
CC1
SCL
V
CC
I
Power Supply Current (Read)
Standby Current
f
= 400 kHz
= 5.5 V
1
40
mA
CC2
SCL
CC
V
I
V
V
= 5.5 V
= GND or V
mA
SB
CC
IN
CC
V
(Note 3)
(Note 3)
Input Low Voltage
Input High Voltage
−0.5
0.3 x V
V
V
V
IL
CC
V
IH
0.7 x V
V
CC
+ 0.5
CC
V
OL
Output Low Voltage
(SDA, RESET)
I
= 3 mA
CC
0.4
OL
V
= 3.0 V
V
Output High Voltage
(RESET)
I
= −0.4 mA
CC
V − 0.75
CC
V
V
OH
OH
V
= 3.0 V
V
Reset Threshold
CAT164x−45
(V = 5.0 V)
4.50
4.75
4.50
3.15
3.00
2.70
TH
CC
CAT164x−42
(V = 5.0 V)
4.25
3.00
2.85
2.55
CC
CAT164x−30
(V = 3.3 V)
CC
CAT164x−28
(V = 3.3 V)
CC
CAT164x−25
(V = 3.0 V)
CC
V
(Note 2) Reset Output Valid V Voltage
1.00
15
V
RVALID
CC
V
RT
(Note 2)
Reset Threshold Hysteresis
mV
2. This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested.
3. V min and V max are reference values only and are not tested.
IL
IH
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4
CAT1640, CAT1641
Table 6. CAPACITANCE
T = 25°C, f = 1.0 MHz, V = 5 V
A
CC
Symbol
(Note 1)
Test
Test Conditions
= 0 V
OUT
Max
8
Units
pF
C
Output Capacitance
Input Capacitance
V
V
OUT
C
(Note 1)
= 0 V
IN
6
pF
IN
Table 7. AC CHARACTERISTICS
V
CC
= 3.0 V to 5.5 V and over the recommended temperature conditions, unless otherwise specified.
Memory Read & Write Cycle (Note 2)
Symbol
Parameter
Min
Max
400
100
Units
kHz
ns
f
Clock Frequency
SCL
t
SP
Input Filter Spike Suppression (SDA, SCL)
Clock Low Period
t
1.3
0.6
ms
LOW
t
Clock High Period
ms
HIGH
t
(Note 1)
SDA and SCL Rise Time
300
300
ns
R
t (Note 1)
SDA and SCL Fall Time
ns
F
t
Start Condition Hold Time
0.6
0.6
0
ms
HD; STA
t
Start Condition Setup Time (for a Repeated Start)
Data Input Hold Time
ms
SU; STA
HD; DAT
t
ns
t
Data Input Setup Time
100
0.6
ns
SU; DAT
SU; STO
t
Stop Condition Setup Time
ms
t
SCL Low to Data Out Valid
900
5
ns
AA
DH
t
Data Out Hold Time
50
ns
t
(Note 1)
(Note 3)
Time the Bus must be Free Before a New Transmission Can Start
Write Cycle Time (Byte or Page)
1.3
ms
BUF
t
ms
WC
1. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
2. Test Conditions according to “AC Test Conditions” table.
3. The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the
write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.
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CAT1640, CAT1641
Table 8. RESET CIRCUIT AC CHARACTERISTICS
Symbol
Parameter
Test Conditions
Min
Typ
Max
270
5
Units
ms
ms
t
Reset Timeout
Note 2
Note 3
130
200
PURST
t
V
TH
V
CC
to RESET output Delay
Glitch Reject Pulse Width
RDP
t
Notes 4 and 5
Note 5
30
ns
GLITCH
MR Glitch
Manual Reset Glitch Immunity
MR Pulse Width
100
ns
t
Note 5
5
ms
MRW
Table 9. POWER−UP TIMING (Notes 5 and 6)
Symbol
Parameter
Power−Up to Read Operation
Power−Up to Write Operation
Test Conditions
Min
Typ
Max
270
270
Units
ms
t
PUR
t
ms
PUW
Table 10. AC TEST CONDITIONS
Parameter
Test Conditions
Input Pulse Voltages
0.2 V to 0.8 V
CC
CC
Input Rise and Fall Times
Input Reference Voltages
Output Reference Voltages
Output Load
10 ns
0.3 V , 0.7 V
CC
CC
0.5 V
CC
Current Source: I = 3 mA; C = 100 pF
OL
L
Table 11. RELIABILITY CHARACTERISTICS
Symbol
(Note 5)
Parameter
Endurance
Reference Test Method
Min
1,000,000
100
Max
Units
N
MIL−STD−883, Test Method 1033
MIL−STD−883, Test Method 1008
MIL−STD−883, Test Method 3015
JEDEC Standard 17
Cycles/Byte
Years
END
T
(Note 5)
(Note 5)
Data Retention
DR
V
ESD Susceptibility
2000
Volts
ZAP
I
(Notes 5 & 7) Latch−Up
100
mA
LTH
1. Test Conditions according to “AC Test Conditions” table.
2. Power−up, Input Reference Voltage V = V , Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
CC
TH
3. Power−Down, Input Reference Voltage V = V , Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
CC
TH
4. V Glitch Reference Voltage = V
; Based on characterization data
CC
THmin
5. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
6. t
and t
are the delays required from the time V is stable until the specified memory operation can be initiated.
PUR
PUW CC
7. Latch−up protection is provided for stresses up to 100 mA on input and output pins from −1 V to V + 1 V.
CC
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RV
L D
T
T
CAT1640, CAT1641
DEVICE OPERATON
Reset Controller Description
When RESET I/O is driven to the active state, the 200 ms
timer will begin to time the reset interval. If external reset is
shorter than 200 ms, Reset outputs will remain active at least
200 ms.
Glitches shorter than 100 ns on RESET input will not
generate a reset pulse.
The CAT1640/41 precision Reset controllers ensure
correct system operation during brownout and power
up/down conditions. They are configured with opendrain
RESET/RESET outputs.
During power−up, the RESET/RESET output remains
active until V reaches the V threshold and will continue
CC
TH
Hardware Data Protection
driving the outputs for approximately 200 ms (t
) after
PURST
The CAT1640/41 family has been designed to solve many
of the data corruption issues that have long been associated
with serial EEPROMs. Data corruption occurs when
incorrect data is stored in a memory location which is
assumed to hold correct data.
reaching V . After the tPURST timeout interval, the device
TH
will cease to drive the reset output. At this point the reset
output will be pulled up or down by their respective pull
up/down resistors.
During power−down, the RESET/RESET outputs will be
Whenever the device is in a Reset condition, the
embedded EEPROM is disabled for all operations,
including write operations. If the Reset output is active, in
progress communications to the EEPROM are aborted and
no new communications are allowed. In this condition an
internal write cycle to the memory can not be started, but an
in progress internal non−volatile memory write cycle can
not be aborted. An internal write cycle initiated before the
Reset condition can be successfully finished if there is
enough time (5 ms) before VCC reaches the minimum value
of 2 V.
active when V falls below V . The RESET/RESET
CC
TH
output will be valid so long as V is > 1.0 V (V
). The
CC
RVALID
device is designed to ignore the fast negative going V
transient pulses (glitches).
CC
Reset output timing is shown in Figure 1.
Manual Reset Operation
The RESET pin can operate as reset output and manual
reset input. The input is edge triggered; that is, the RESET
input will initiate a reset timeout after detecting a high to low
transition.
tGLITCH
VTH
V
tRPD
tPUR
VCC
tRPD
tPUR
RESEꢀT
RESET
Figure 1. RESET/RESET Output Timing
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CAT1640, CAT1641
t
MRW
RESET
(Input)
t
PURST
RESET
(Output)
Figure 2. RESET as Manual Reset Input Operation and Timing
t
t
t
R
F
HIGH
t
t
LOW
LOW
SCL
t
SU:STA
t
HD:DAT
t
t
t
t
HD:STA
SU:DAT
SU:STO
SDA IN
BUF
t
AA
t
DH
SDA OUT
Figure 3. Bus Timing
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CAT1640, CAT1641
EMBEDDED EEPROM OPERATON
The CAT1640 and CAT1641 feature a 64 kbit embedded
serial EEPROM that supports the I C Bus data transmission
2. During a data transfer, the data line must remain
stable whenever the clock line is high. Any
2
protocol. This Inter−Integrated Circuit Bus protocol defines
any device that sends data to the bus to be a transmitter and
any device receiving data to be a receiver. The transfer is
controlled by the Master device which generates the serial
clock and all START and STOP conditions for bus access.
Both the Master device and Slave device can operate as
either transmitter or receiver, but the Master device controls
which mode is activated.
changes in the data line while the clock line is high
will be interpreted as a START or STOP condition.
Start Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of SDA
when SCL is HIGH. The CAT1640/41 monitors the SDA
and SCL lines and will not respond until this condition is
met.
I2C Bus Protocol
The features of the I C bus protocol are defined as
Stop Condition
2
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
follows:
1. Data transfer may be initiated only when the bus is
not busy.
DEVICE ADDRESSING
The Master begins a transmission by sending a START
condition. The Master sends the address of the particular
slave device it is requesting. The four most significant bits
of the 8−bit slave address are programmable in metal and the
default is 1010.
The last bit of the slave address specifies whether a Read
or Write operation is to be performed. When this bit is set to
1, a Read operation is selected, and when set to 0, a Write
operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT1640/41 monitors the bus and
responds with an acknowledge (on the SDA line) when its
address matches the transmitted slave address. The
CAT1640/41 then perform a Read or Write operation
depending on the R/W bit.
SCL
SDA
8TH B
T
ACK
BYTE n
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 4. Write Cycle Timing
ACKNOWLEDGE
After a successful data transfer, each receiving device is
required to generate an acknowledge. The acknowledging
device pulls down the SDA line during the ninth clock cycle,
signaling that it received the 8 bits of data.
The CAT1640/41 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation, it
responds with an acknowledge after receiving each 8−bit
byte.
When the CAT1640/41 begins a READ mode it transmits
8 bits of data, releases the SDA line and monitors the line for
an acknowledge. Once it receives this acknowledge, the
CAT1640/41 will continue to transmit data. If no
acknowledge is sent by the Master, the device terminates
data transmission and waits for a STOP condition.
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CAT1640, CAT1641
WRITE OPERATIONS
Byte Write
Slave, the Master device transmits the data to be written into
the addressed memory location. The CAT1640/41
acknowledges once more and the Master generates the
STOP condition. At this time, the device begins an internal
programming cycle to non−volatile memory. While the
cycle is in progress, the device will not respond to any
request from the Master device.
In the Byte Write mode, the Master device sends the
START condition and the slave address information (with
the R/W bit set to zero) to the Slave device. After the Slave
generates an acknowledge, the Master sends two 8−bit
address bytes that are to be written into the address pointers
of the device. After receiving another acknowledge from the
SDA
SCL
START BIT
STOP BIT
Figure 5. Start/Stop Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 6. Acknowledge Timing
Default Configuration
1
0
1
0
A2
A1
A0 R/W
Figure 7. Slave Address Bits
Page Write
The CAT1640/41 writes up to 64 bytes of data in a single
write cycle, using the Page Write operation. The page write
operation is initiated in the same manner as the byte write
operation, however instead of terminating after the initial
byte is transmitted, the Master is allowed to send up to
additional 63 bytes. After each byte has been transmitted, the
CAT1640/41 will respond with an acknowledge and
internally increment the lower order address bits by one. The
high order bits remain unchanged.
If the Master transmits more than 64 bytes before sending
the STOP condition, the address counter ‘wraps around’,
and previously transmitted data will be overwritten.
When all 64 bytes are received, and the STOP condition
has been sent by the Master, the internal programming cycle
begins. At this point, all received data is written to the
CAT1640/41 in a single write cycle.
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CAT1640, CAT1641
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE ADDRESS
A
–A
A –A
DATA
15
8
7
0
SDA LINE
S
P
**
*
A
C
K
A
C
K
A
C
K
A
C
K
* = Don’t Care Bit
Figure 8. Byte Write Timing
S
T
A
R
T
S
T
O
P
BUS
ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE ADDRESS
–A A –A
0
A
15
DATA
DATA n
DATA n+63
8
7
SDA LINE
S
P
***
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
* = Don’t Care Bit
Figure 9. Page Write Timing
Acknowledge Polling
Read Operations
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is issued
to indicate the end of the host’s write operation, the
CAT1640/41 initiates the internal write cycle. ACK polling
can be initiated immediately. This involves issuing the start
condition followed by the slave address for a write
operation. If the device is still busy with the write operation,
no ACK will be returned. If a write operation has completed,
an ACK will be returned and the host can then proceed with
the next read or write operation.
The READ operation for the CAT1640/41 is initiated in
the same manner as the write operation with one exception,
that R/W bit is set to one. Three different READ operations
are possible: Immediate/Current Address READ,
Selective/Random READ and Sequential READ.
S
T
A
R
T
S
T
O
P
BUS ꢀACTIVITꢀY:
MASTER
SLꢀAVE
ADDRESS
SDꢀA LINE
S
P
A
C
K
N
O
DATA
A
C
K
SCꢀL
8
9
SDꢀAꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ8TH BIꢀT
DATA OUꢀT
NO ACK
STOP
Figure 10. Immediate Address Read Timing
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CAT1640, CAT1641
Immediate/Current Address Read
again, this time with the R/W bit set to one. The CAT1640
and CAT1641 then responds with its acknowledge and sends
the 8−bit byte requested. The master device does not send an
acknowledge but will generate a STOP condition.
The CAT1640 and CAT1641 address counter contains the
address of the last byte accessed, incremented by one. In
other words, if the last READ or WRITE access was to
address N, the READ immediately following would access
data from address N+1. For all devices, N = E = 4,095. The
counter will wrap around to Zero and continue to clock out
valid data. After the CAT1640 and CAT1641 receives its
slave address information (with the R/W bit set to one), it
issues an acknowledge, then transmits the 8−bit byte
requested. The master device does not send an acknowledge,
but will generate a STOP condition.
Sequential Read
The Sequential READ operation can be initiated by either
the Immediate Address READ or Selective READ
operations. After the CAT1640 and CAT1641 sends the
initial 8−bit byte requested, the Master will responds with an
acknowledge which tells the device it requires more data.
The CAT1640 and CAT1641 will continue to output an 8−bit
byte for each acknowledge, thus sending the STOP
condition.
Selective/Random Read
Selective/Random READ operations allow the Master
device to select at random any memory location for a READ
operation. The Master device first performs a ‘dummy’
write operation by sending the START condition, slave
address and byte addresses of the location it wishes to read.
After the CAT1640 and CAT1641 acknowledges, the Master
device sends the START condition and the slave address
The data being transmitted from the CAT1640 and
CAT1641 is sent sequentially with the data from address N
followed by data from address N+1. The READ operation
address counter increments all of the CAT1640 and
CAT1641 address bits so that the entire memory array can
be read during one operation.
S
T
A
S
T
S
T
O
P
A
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE ADDRESS
–A A –A
0
SLAVE
ADDRESS
R
T
R
A
DATA
15
8
7
T
S
SDA LINE
S
P
*
*
*
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
* = Don’t Care Bit
Figure 11. Selective Read Timing
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
Figure 12. Sequential Read Timing
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12
CAT1640, CAT1641
ORDERING INFORMATION
Orderable Part Numbers − CAT1640 Series
(See Notes 1 − 5)
Device
Reset Threshold
4.50 V − 4.75 V
4.25 V − 4.50 V
3.00 V − 3.15 V
2.85 V − 3.00 V
2.55 V − 2.70 V
4.50 V − 4.75 V
4.25 V − 4.50 V
3.00 V − 3.15 V
2.85 V − 3.00 V
2.55 V − 2.70 V
4.50 V − 4.75 V
4.25 V − 4.50 V
3.00 V − 3.15 V
2.85 V − 3.00 V
2.55 V − 2.70 V
4.50 V − 4.75 V
4.25 V − 4.50 V
3.00 V − 3.15 V
2.85 V − 3.00 V
2.55 V − 2.70 V
Package
Shipping
CAT1640LI−45−G
CAT1640LI−42−G
CAT1640LI−30−G
CAT1640LI−28−G
CAT1640LI−25−G
CAT1640WI−45−GT3
CAT1640WI−42−GT3
CAT1640WI−30−GT3
CAT1640WI−28−GT3
CAT1640WI−25−GT3
CAT1640YI−45−GT3
CAT1640YI−42−GT3
CAT1640YI−30−GT3
CAT1640YI−28−GT3
CAT1640YI−25−GT3
CAT1640ZD2I45GT3
CAT1640ZD2I42GT3
CAT1640ZD2I30GT3
CAT1640ZD2I28GT3
CAT1640ZD2I25GT3
PDIP
SOIC
TSSOP
TDFN
3000 Tape & Reel
1. All packages are RoHS−compliant (Lead−free, Halogen−free).
2. The standard lead finish is NiPdAu.
3. For additional package and temperature options, please contact your nearest
ON Semiconductor Sales office.
4. TDFN not available in NiPdAu (–G) version.
5. For detailed information and a breakdown of device nomenclature and numbering
systems, please see the ON Semiconductor Device Nomenclature document,
TND310/D, available at www.onsemi.com
http://onsemi.com
13
CAT1640, CAT1641
Orderable Part Numbers − CAT1641 Series
(See Notes 1 − 5)
Device
Reset Threshold
4.50 V − 4.75 V
4.25 V − 4.50 V
3.00 V − 3.15 V
2.85 V − 3.00 V
2.55 V − 2.70 V
4.50 V − 4.75 V
4.25 V − 4.50 V
3.00 V − 3.15 V
2.85 V − 3.00 V
2.55 V − 2.70 V
4.50 V − 4.75 V
4.25 V − 4.50 V
3.00 V − 3.15 V
2.85 V − 3.00 V
2.55 V − 2.70 V
4.50 V − 4.75 V
4.25 V − 4.50 V
3.00 V − 3.15 V
2.85 V − 3.00 V
2.55 V − 2.70 V
Package
Shipping
CAT1641LI−45−G
CAT1641LI−42−G
CAT1641LI−30−G
CAT1641LI−28−G
CAT1641LI−25−G
CAT1641WI−45−GT3
CAT1641WI−42−GT3
CAT1641WI−30−GT3
CAT1641WI−28−GT3
CAT1641WI−25−GT3
CAT1641YI−45−GT3
CAT1641YI−42−GT3
CAT1641YI−30−GT3
CAT1641YI−28−GT3
CAT1641YI−25−GT3
CAT1641ZD2I45GT3
CAT1641ZD2I42GT3
CAT1641ZD2I30GT3
CAT1641ZD2I28GT3
CAT1641ZD2I25GT3
PDIP
SOIC
TSSOP
TDFN
3000 Tape & Reel
1. All packages are RoHS−compliant (Lead−free, Halogen−free).
2. The standard lead finish is NiPdAu.
3. For additional package and temperature options, please contact your nearest
ON Semiconductor Sales office.
4. TDFN not available in NiPdAu (–G) version.
5. For detailed information and a breakdown of device nomenclature and numbering
systems, please see the ON Semiconductor Device Nomenclature document,
TND310/D, available at www.onsemi.com
http://onsemi.com
14
CAT1640, CAT1641
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
SYMBOL
MIN
NOM
MAX
1.35
A
1.75
A1
b
0.10
0.33
0.19
0.25
0.51
0.25
c
E1
E
D
E
E1
e
4.80
5.80
3.80
5.00
6.20
4.00
1.27 BSC
h
0.25
0.40
0º
0.50
1.27
8º
L
PIN # 1
IDENTIFICATION
θ
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
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15
CAT1640, CAT1641
PDIP−8, 300 mils
CASE 646AA−01
ISSUE A
SYMBOL
MIN
NOM
MAX
A
5.33
A1
A2
b
0.38
2.92
0.36
3.30
0.46
1.52
0.25
9.27
4.95
0.56
1.78
0.36
10.16
b2
c
1.14
0.20
9.02
E1
D
E
E1
e
7.62
6.10
7.87
6.35
8.25
7.11
2.54 BSC
7.87
2.92
10.92
3.80
eB
L
PIN # 1
IDENTIFICATION
3.30
D
TOP VIEW
E
A2
A1
A
c
b2
L
eB
e
b
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.
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16
CAT1640, CAT1641
TDFN8, 3x4.9
CASE 511AM−01
ISSUE A
D
A
DETAIL A
DAP SIZE
2.6 x 3.3mm
E
E2
PIN #1
IDENTIFICATION
A1
PIN #1 IDENTIFICATION
D2
TOP VIEW
SIDE VIEW
BOTTOM VIEW
SYMBOL
MIN
NOM
MAX
A2
A
A
0.70
0.00
0.45
0.75
0.02
0.55
0.80
0.05
0.65
A1
A2
A1
A3
FRONT VIEW
A3
b
0.20 REF
0.30
0.25
2.90
0.90
4.80
0.90
0.35
3.10
1.10
5.00
1.10
b
D
3.00
D2
E
1.00
4.90
L
E2
e
1.00
0.65 TYP
0.60
e
L
0.50
0.70
DETAIL A
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MO-229.
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17
CAT1640, CAT1641
TSSOP−8
CASE 948S−01
ISSUE C
8x K REF
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T U
S
0.20 (0.008) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
8
5
4
2X L/2
B
−U−
J
J1
L
1
PIN 1
IDENT
K1
K
S
0.20 (0.008) T U
A
SECTION N−N
−V−
MILLIMETERS
INCHES
MIN
0.114
DIM MIN
MAX
MAX
0.122
0.177
0.043
0.006
0.028
A
B
2.90
4.30
---
3.10
−W−
4.50 0.169
1.10 ---
C
C
0.076 (0.003)
D
0.05
0.50
0.15 0.002
0.70 0.020
F
DETAIL E
SEATING
D
−T−
G
G
J
0.65 BSC
0.026 BSC
PLANE
0.09
0.09
0.19
0.19
0.20 0.004
0.16 0.004
0.30 0.007
0.25 0.007
0.008
0.006
0.012
0.010
J1
K
0.25 (0.010)
N
K1
L
6.40 BSC
0.252 BSC
0
M
M
0
8
8
_
_
_
_
N
F
DETAIL E
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