CAT24C03 [ONSEMI]
2-Kb and 4-Kb I2C Serial EEPROM with Partial Array Write Protection; 2 - KB和4 KB的I2C串行EEPROM部分阵列写保护
| 型号： | CAT24C03 |
| 厂家： | 
ONSEMI |
| 描述： | 2-Kb and 4-Kb I2C Serial EEPROM with Partial Array Write Protection |
| 文件： | 总14页 (文件大小：159K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT24C03, CAT24C05
2-Kb and 4-Kb I2C Serial
EEPROM with Partial Array
Write Protection
Description
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The CAT24C03/05 is a 2−Kb/4−Kb CMOS Serial EEPROM device
organized internally as 16/32 pages of 16 bytes each, for a total of
256x8/512x8 bits. These devices support both Standard (100 kHz) as
2
well as Fast (400 kHz) I C protocol.
Data is written by providing a starting address, then loading 1 to 16
contiguous bytes into a Page Write Buffer, and then writing all data to
non−volatile memory in one internal write cycle. Data is read by
providing a starting address and then shifting out data serially while
automatically incrementing the internal address count.
PDIP−8
L SUFFIX
CASE 646AA
TSOT−23
TD SUFFIX
CASE 419AE
SOIC−8
W SUFFIX
CASE 751BD
Write operations can be inhibited for upper half of memory by
taking the WP pin High.
External address pins make it possible to address up to eight
CAT24C03 or four CAT24C05 devices on the same bus.
TSSOP8
Y SUFFIX
CASE 948AL
TDFN8
VP2 SUFFIX
CASE 511AK
Features
PIN CONFIGURATIONS
2
• Supports Standard and Fast I C Protocol
TSOT−23 (TD)
• 1.8 V to 5.5 V Supply Voltage Range
• 16−Byte Page Write Buffer
5
4
SCL
WP
1
2
3
V
SS
• Hardware Write Protection for Upper Half of Memory
2
SDA
V
CC
• Schmitt Triggers and Noise Suppression Filters on I C Bus Inputs
(SCL and SDA)
PDIP (L), SOIC (W),
TSSOP (Y), TDFN (VP2)
• Low Power CMOS Technology
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
• Industrial Temperature Range
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
CAT24C05/03
NC/A
V
CC
8
7
6
5
0
1
2
3
4
A /A
WP
1
1
2
A /A
SCL
SDA
2
V
SS
(Top Views)
V
CC
PIN FUNCTION
Pin Name
Function
SCL
A0, A1, A2
Device Address Inputs
Serial Data Input/Output
Serial Clock Input
Write Protect Input
Power Supply
CAT24C03
CAT24C05
SDA
SCL
WP
A , A , A
SDA
2
1
0
WP
V
CC
V
Ground
SS
V
SS
NC
No Connect
Figure 1. Functional Symbol
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
1
Publication Order Number:
August, 2009 − Rev. 3
CAT24C03/D
CAT24C03, CAT24C05
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
°C
Storage Temperature
−65 to +150
−0.5 to +6.5
Voltage on any pin with respect to Ground (Note 1)
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than V + 0.5 V. During transitions, the voltage on any pin may
CC
undershoot to no less than −1.5 V or overshoot to no more than V + 1.5 V, for periods of less than 20 ns.
CC
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol
(Note 3)
Parameter
Min
1,000,000
100
Units
Program / Erase Cycles
Years
N
Endurance
END
T
DR
Data Retention
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, V = 5 V, 25°C.
CC
Table 3. D.C. OPERATING CHARACTERISTICS
(V = 1.8 V to 5.5 V, T = −40°C to +85°C, unless otherwise specified.)
CC
A
Symbol
Parameter
Test Conditions
Min
Max
Units
mA
mA
mA
mA
V
I
Read Current
Read, f
= 400 kHz
= 400 kHz
1
1
1
1
CCR
SCL
SCL
I
Write Current
Write, f
CCW
I
SB
Standby Current
I/O Pin Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
All I/O Pins at GND or V
CC
I
L
Pin at GND or V
CC
V
IL
−0.5
V
x 0.3
CC
V
IH
V
x 0.7
V
+ 0.5
V
CC
CC
V
OL1
V
OL2
V
V
≥ 2.5 V, I = 3 mA
0.4
0.2
V
CC
OL
< 2.5 V, I = 1 mA
V
CC
OL
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2
CAT24C03, CAT24C05
Table 4. PIN IMPEDANCE CHARACTERISTICS
(V = 1.8 V to 5.5 V, T = −40°C to +85°C, unless otherwise specified.)
CC
A
Symbol
Parameter
Conditions
Max
8
Units
pF
C
(Note 4)
SDA I/O Pin Capacitance
Input Capacitance (Other Pins)
WP Input Current
V
IN
V
IN
= 0 V
= 0 V
IN
6
pF
I
(Note 5)
V
IN
V
IN
V
IN
< V , V = 5.5 V
200
150
100
1
mA
WP
IH
CC
< V , V = 3.3 V
IH
CC
< V , V = 1.8 V
IH
CC
V
IN
> V
IH
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
5. When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively strong;
therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power, as
the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V ), the strong pull−down reverts to a weak current source.
CC
Table 5. A.C. CHARACTERISTICS
(Note 6) (V = 1.8 V to 5.5 V, T = −40°C to +85°C, unless otherwise specified.)
CC
A
Standard
Fast
Min
Max
Min
Max
Symbol
Parameter
Units
kHz
ms
F
SCL
Clock Frequency
100
400
t
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
START Condition Setup Time
Data In Hold Time
4
4.7
4
0.6
1.3
0.6
0.6
0
HD:STA
t
ms
LOW
t
ms
HIGH
t
4.7
0
ms
SU:STA
HD:DAT
t
ms
t
Data In Setup Time
250
100
ns
SU:DAT
t
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Condition Setup Time
Bus Free Time Between STOP and START
SCL Low to Data Out Valid
Data Out Hold Time
1000
300
300
300
ns
R
t (Note 7)
ns
F
t
4
0.6
1.3
ms
SU:STO
t
4.7
ms
BUF
t
AA
3.5
0.9
ms
t
100
100
ns
DH
T (Note 7)
Noise Pulse Filtered at SCL and SDA Inputs
WP Setup Time
100
100
ns
i
t
0
0
ms
SU:WP
HD:WP
t
WP Hold Time
2.5
2.5
ms
t
Write Cycle Time
5
1
5
1
ms
ms
WR
t
(Notes 7, 8) Power−up to Ready Mode
PU
6. Test conditions according to “A.C. Test Conditions” table.
7. Tested initially and after a design or process change that affects this parameter.
8. t is the delay between the time V is stable and the device is ready to accept commands.
PU
CC
Table 6. A.C. TEST CONDITIONS
Input Levels
0.2 x V to 0.8 x V
CC
CC
Input Rise and Fall Times
Input Reference Levels
Output Reference Levels
Output Load
v 50 ns
0.3 x V , 0.7 x V
CC
CC
0.5 x V
CC
Current Source: I = 3 mA (V w 2.5 V); I = 1 mA (V < 2.5 V); C = 100 pF
OL
CC
OL
CC
L
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CAT24C03, CAT24C05
Power−On Reset (POR)
device pulls down the SDA line to ‘transmit’ a ‘0’ and
releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
The CAT24C03/05 incorporates Power−On Reset (POR)
circuitry which protects the internal logic against powering
up in the wrong state.
The CAT24C03/05 device will power up into Standby
During data transfer, the SDA line must remain stable
while the SCL line is high. An SDA transition while SCL is
HIGH will be interpreted as a START or STOP condition
(Figure 2). The START condition precedes all commands. It
consists of a HIGH to LOW transition on SDA while SCL
is HIGH. The START acts as a ‘wake−up’ call to all
receivers. Absent a START, a Slave will not respond to
commands. The STOP condition completes all commands.
It consists of a LOW to HIGH transition on SDA while SCL
is HIGH.
mode after V exceeds the POR trigger level and will
CC
power down into Reset mode when V drops below the
CC
POR trigger level. This bi−directional POR feature protects
the device against ‘brown−out’ failure following a
temporary loss of power.
Pin Description
SCL: The Serial Clock input pin accepts the Serial Clock
generated by the Master.
SDA: The Serial Data I/O pin receives input data and
transmits data stored in EEPROM. In transmit mode, this pin
is open drain. Data is acquired on the positive edge, and is
delivered on the negative edge of SCL.
Device Addressing
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an 8−bit
serial Slave address. For normal Read/Write operations, the
first 4 bits of the Slave address are fixed at 1010 (Ah). The
next 3 bits are used as programmable address bits when
cascading multiple devices and/or as internal address bits.
The last bit of the slave address, R/W, specifies whether a
Read (1) or Write (0) operation is to be performed. The 3
address space extension bits are assigned as illustrated in
A0, A1 and A2: The Address inputs set the device address
when cascading multiple devices. When not driven, these
pins are pulled LOW internally.
WP: The Write Protect input pin inhibits the write
operations for upper half of memory, when pulled HIGH.
When not driven, this pin is pulled LOW internally.
Figure 3. A , A and A must match the state of the external
2
1
0
Functional Description
address pins, and a (CAT24C05) is internal address bit.
8
The CAT24C03/05 supports the Inter−Integrated Circuit
2
Acknowledge
(I C) Bus data transmission protocol, which defines a device
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA line
during the 9th clock cycle (Figure 4). The Slave will also
acknowledge the address byte and every data byte presented
in Write mode. In Read mode the Slave shifts out a data byte,
that sends data to the bus as a transmitter and a device
receiving data as a receiver. Data flow is controlled by a
Master device, which generates the serial clock and all
START and STOP conditions. The CAT24C03/05 acts as a
Slave device. Master and Slave alternate as either
transmitter or receiver.
th
and then releases the SDA line during the 9 clock cycle. As
long as the Master acknowledges the data, the Slave will
continue transmitting. The Master terminates the session by
not acknowledging the last data byte (NoACK) and by
issuing a STOP condition. Bus timing is illustrated in
Figure 5.
I2C Bus Protocol
The I C bus consists of two ‘wires’, SCL and SDA. The
two wires are connected to the V supply via pull−up
resistors. Master and Slave devices connect to the 2−wire
2
CC
bus via their respective SCL and SDA pins. The transmitting
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CAT24C03, CAT24C05
SCL
SDA
START
CONDITION
STOP
CONDITION
Figure 2. START/STOP Conditions
1
1
0
0
1
1
0
0
A
A
A
R/W
R/W
CAT24C03
CAT24C05
2
1
0
A
2
A
1
a
8
Figure 3. Slave Address Bits
BUS RELEASE DELAY (TRANSMITTER)
BUS RELEASE DELAY
(RECEIVER)
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACK SETUP (w t
)
SU:DAT
ACK DELAY (v t
)
START
AA
Figure 4. Acknowledge Timing
t
F
t
t
R
HIGH
t
t
LOW
LOW
SCL
t
t
HD:DAT
SU:STA
t
t
t
HD:STA
SU:DAT
SU:STO
SDA IN
t
BUF
t
AA
t
DH
SDA OUT
Figure 5. Bus Timing
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5
CAT24C03, CAT24C05
WRITE OPERATIONS
Byte Write
sixteen bytes are received and the STOP condition has been
sent by the Master, the internal Write cycle begins. At this
point all received data is written to the CAT24C03/05 in a
single write cycle.
In Byte Write mode, the Master sends the START
condition and the Slave address with the R/W bit set to zero
to the Slave. After the Slave generates an acknowledge, the
Master sends the byte address that is to be written into the
address pointer of the CAT24C03/05. After receiving
another acknowledge from the Slave, the Master transmits
the data byte to be written into the addressed memory
location. The CAT24C03/05 device will acknowledge the
data byte and the Master generates the STOP condition, at
which time the device begins its internal Write cycle to
nonvolatile memory (Figure 6). While this internal cycle is
Acknowledge Polling
The acknowledge (ACK) polling routine can be used to
take advantage of the typical write cycle time. Once the stop
condition is issued to indicate the end of the host’s write
operation, the CAT24C03/05 initiates the internal write
cycle. The ACK polling can be initiated immediately. This
involves issuing the start condition followed by the slave
address for a write operation. If the CAT24C03/05 is still
busy with the write operation, NoACK will be returned. If
the CAT24C03/05 has completed the internal write
operation, an ACK will be returned and the host can then
proceed with the next read or write operation.
in progress (t ), the SDA output will be tri−stated and the
CAT24C03/05 will not respond to any request from the
Master device (Figure 7).
WR
Page Write
The CAT24C03/05 writes up to 16 bytes of data in a single
write cycle, using the Page Write operation (Figure 8). The
Page Write operation is initiated in the same manner as the
Byte Write operation, however instead of terminating after
the data byte is transmitted, the Master is allowed to send up
to fifteen additional bytes. After each byte has been
transmitted the CAT24C03/05 will respond with an
acknowledge and internally increments the four low order
address bits. The high order bits that define the page address
remain unchanged. If the Master transmits more than sixteen
bytes prior to sending the STOP condition, the address
counter ‘wraps around’ to the beginning of page and
previously transmitted data will be overwritten. Once all
Hardware Write Protection
With the WP pin held HIGH, the upper half of memory is
protected against Write operations. If the WP pin is left
floating or is grounded, it has no impact on the operation of
the CAT24C03/05. The state of the WP pin is strobed on the
last falling edge of SCL immediately preceding the first data
byte (Figure 9). If the WP pin is HIGH during the strobe
interval, the CAT24C03/05 will not acknowledge the data
byte and the Write request will be rejected.
Delivery State
The CAT24C03/05 is shipped erased, i.e., all bytes are
FFh.
S
T
A
R
T
BUS ACTIVITY:
MASTER
S
ADDRESS
BYTE
DATA
BYTE
T
O
P
SLAVE
ADDRESS
a
7
÷ a
d ÷ d
7 0
0
S
P
A
C
K
A
C
K
A
C
K
SLAVE
Figure 6. Byte Write Sequence
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6
CAT24C03, CAT24C05
SCL
SDA
th
8
Bit
ACK
Byte n
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 7. Write Cycle Timing
S
T
A
R
T
BUS ACTIVITY:
MASTER
S
DATA
DATA
DATA
T
O
P
ADDRESS
BYTE
SLAVE
ADDRESS
BYTE
n+1
BYTE
n+P
BYTE
n
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
SLAVE
n = 1
P v 15
Figure 8. Page Write Sequence
ADDRESS
BYTE
DATA
BYTE
1
8
9
1
7
8
SCL
a
7
a
d
d
0
SDA
WP
0
t
SU:WP
t
HD:WP
Figure 9. WP Timing
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7
CAT24C03, CAT24C05
READ OPERATIONS
Immediate Read
address of the location it wishes to read. After the
CAT24C03/05 acknowledges the byte address, the Master
device resends the START condition and the slave address,
this time with the R/W bit set to one. The CAT24C03/05 then
responds with its acknowledge and sends the requested data
byte. The Master device does not acknowledge the data
(NoACK) but will generate a STOP condition (Figure 11).
Upon receiving a Slave address with the R/W bit set to ‘1’,
the CAT24C03/05 will interpret this as a request for data
residing at the current byte address in memory. The
CAT24C03/05 will acknowledge the Slave address, will
immediately shift out the data residing at the current address,
and will then wait for the Master to respond. If the Master
does not acknowledge the data (NoACK) and then follows
up with a STOP condition (Figure 10), the CAT24C03/05
returns to Standby mode.
Sequential Read
st
If during a Read session, the Master acknowledges the 1
data byte, then the CAT24C03/05 will continue transmitting
data residing at subsequent locations until the Master
responds with a NoACK, followed by a STOP (Figure 12).
In contrast to Page Write, during Sequential Read the
address count will automatically increment to and then
wrap−around at end of memory (rather than end of page).
Selective Read
Selective Read operations allow the Master device to
select at random any memory location for a read operation.
The Master device first performs a ‘dummy’ write operation
by sending the START condition, slave address and byte
N
S
T
A
R
T
O
BUS ACTIVITY:
MASTER
S
A T
C O
K P
SLAVE
ADDRESS
S
P
A
DATA
C
SLAVE
8
BYTE
K
SCL
SDA
9
th
8
Bit
DATA OUT
NO ACK
STOP
Figure 10. Immediate Read Sequence and Timing
N
O
S
T
A
R
T
S
T
A
R
T
BUS ACTIVITY:
MASTER
S
A T
C O
K P
ADDRESS
BYTE
SLAVE
ADDRESS
SLAVE
ADDRESS
S
S
P
A
C
K
A
C
K
A
C
K
DATA
BYTE
SLAVE
Figure 11. Selective Read Sequence
N
O
BUS ACTIVITY:
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
SLAVE
ADDRESS
MASTER
P
A
C
K
SLAVE
DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+2
DATA
BYTE
n+x
Figure 12. Sequential Read Sequence
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CAT24C03, CAT24C05
PACKAGE DIMENSIONS
PDIP−8, 300 mils
CASE 646AA−01
ISSUE A
SYMBOL
MIN
NOM
MAX
A
5.33
A1
A2
b
0.38
2.92
0.36
3.30
0.46
1.52
0.25
9.27
4.95
0.56
1.78
0.36
10.16
b2
c
1.14
0.20
9.02
E1
D
E
E1
e
7.62
6.10
7.87
6.35
8.25
7.11
2.54 BSC
7.87
2.92
10.92
3.80
eB
L
PIN # 1
IDENTIFICATION
3.30
D
TOP VIEW
E
A2
A1
A
c
b2
L
eB
e
b
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.
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CAT24C03, CAT24C05
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
SYMBOL
MIN
NOM
MAX
1.35
A
A1
b
1.75
0.25
0.51
0.25
0.10
0.33
0.19
c
E1
E
D
E
E1
e
4.80
5.80
3.80
5.00
6.20
4.00
1.27 BSC
h
0.25
0.40
0º
0.50
1.27
8º
L
PIN # 1
IDENTIFICATION
θ
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
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10
CAT24C03, CAT24C05
PACKAGE DIMENSIONS
TSSOP8, 4.4x3
CASE 948AL−01
ISSUE O
b
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
1.20
0.15
1.05
0.30
0.20
3.10
6.50
4.50
0.05
0.80
0.19
0.09
2.90
6.30
4.30
0.90
E
c
E1
D
3.00
6.40
E
E1
e
4.40
0.65 BSC
1.00 REF
L
L1
0.50
0.60
0.75
0º
8º
θ
e
TOP VIEW
D
c
A2
A
q1
A1
L1
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
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11
CAT24C03, CAT24C05
PACKAGE DIMENSIONS
TDFN8, 2x3
CASE 511AK−01
ISSUE A
D
A
e
b
E2
E
PIN#1
IDENTIFICATION
A1
PIN#1 INDEX AREA
D2
L
TOP VIEW
SIDE VIEW
BOTTOM VIEW
SYMBOL
MIN
0.70
0.00
0.45
NOM
MAX
0.80
0.05
0.65
A
A1
A2
A3
b
0.75
0.02
A2
0.55
0.20 REF
0.25
A3
0.20
1.90
1.30
2.90
1.20
0.30
2.10
1.50
3.10
1.40
D
2.00
FRONT VIEW
D2
E
1.40
3.00
E2
e
1.30
0.50 TYP
0.30
L
0.20
0.40
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MO-229.
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CAT24C03, CAT24C05
PACKAGE DIMENSIONS
TSOT−23, 5 LEAD
CASE 419AE−01
ISSUE O
SYMBOL
MIN
NOM
MAX
1.00
0.10
0.90
0.45
0.20
D
A
A1
A2
b
e
0.01
0.80
0.30
0.12
0.05
0.87
c
0.15
D
2.90 BSC
2.80 BSC
1.60 BSC
0.95 TYP
0.40
E1
E
E
E1
e
L
0.30
0.50
L1
L2
θ
0.60 REF
0.25 BSC
0º
8º
TOP VIEW
A2 A
q
L
b
c
A1
L2
L1
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-193.
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CAT24C03, CAT24C05
Example of Ordering Information
Prefix
Device #
Suffix
CAT
24C03
Y
I
− G
T3
Temperature Range
Lead Finish
Tape & Reel (Note 13)
Company ID
G: NiPdAu
Blank: Matte−Tin
T: Tape & Reel
3: 3,000 Units / Reel
I = Industrial (−40°C to +85°C)
Product Number
24C03
24C05
Package
L: PDIP
W: SOIC, JEDEC
Y: TSSOP
VP2: TDFN
TD: TSOT
9. All packages are RoHS−compliant (Lead−free, Halogen−free).
10.The standard lead finish is NiPdAu pre−plated (PPF) lead frames.
11. The device used in the above example is a CAT24C03YI−GT3 (TSSOP, Industrial Temperature, NiPdAu, Tape & Reel).
12.For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.
13.For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
2
ON Semiconductor is licensed by Philips Corporation to carry the I C Bus Protocol.
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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CAT24C03/D
相关型号：
CAT24C03LI
256X8 I2C/2-WIRE SERIAL EEPROM, PDIP8, 0.300 INCH, ROHS COMPLIANT, PLASTIC, MS-001, DIP-8
ONSEMI
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