CAT24C08XI-T2 [ONSEMI]
EEPROM Serial 2/4/8/16Kb I2C;
| 型号： | CAT24C08XI-T2 |
| 厂家： | 
ONSEMI |
| 描述： | EEPROM Serial 2/4/8/16Kb I2C 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总19页 (文件大小：216K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT24C02, CAT24C04,
CAT24C08, CAT24C16
EEPROM Serial
2/4/8/16ꢀKb I2C
Description
The CAT24C02/04/08/16 are 2−Kb, 4−Kb, 8−Kb and 16−Kb
respectively I C Serial EEPROM devices organized internally as
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2
16/32/64 and 128 pages respectively of 16 bytes each. All devices
2
support both the Standard (100 kHz) as well as Fast (400 kHz) I C
protocol.
UDFN8−EP
HU4 SUFFIX
CASE 517AZ
Data is written by providing a starting address, then loading 1 to 16
contiguous bytes into a Page Write Buffer, and then writing all data to
non−volatile memory in one internal write cycle. Data is read by
providing a starting address and then shifting out data serially while
automatically incrementing the internal address count.
External address pins make it possible to address up to eight
CAT24C02, four CAT24C04, two CAT24C08 and one CAT24C16
device on the same bus.
SOIC−8 WIDE
X SUFFIX
CASE 751BE
TSSOP−8
Y SUFFIX
CASE 948AL
TSOT−23
TD SUFFIX
CASE 419AE
Features
2
• Supports Standard and Fast I C Protocol
WLCSP−4**
C4A SUFFIX
CASE 567DC
• 1.7 V to 5.5 V Supply Voltage Range
• 16−Byte Page Write Buffer
SOIC−8
W SUFFIX
CASE 751BD
• Hardware Write Protection for Entire Memory
2
• Schmitt Triggers and Noise Suppression Filters on I C Bus Inputs
WLCSP−5**
C5A SUFFIX
CASE 567DD
WLCSP−4**
C4U SUFFIX
CASE 567NX
(SCL and SDA)
• Low power CMOS Technology
• More than 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
** WLCSP are available for the CAT24C04,
CAT24C08 and CAT24C16 only.
For serial EEPROM in the US8 package, please
consult the N24C02 datasheet
• Industrial and Extended Temperature Range
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 18 of this data sheet.
This document contains information on some products that are still under development.
ON Semiconductor reserves the right to change or discontinue these products without
notice.
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
October, 2018 − Rev. 34
CAT24C01/D
CAT24C02, CAT24C04, CAT24C08, CAT24C16
PIN CONFIGURATIONS AND MARKING INFORMATION
V
CC
Table 1. PIN FUNCTION
†
Pin Name
Function
A0, A1, A2
SDA
Device Address Input
SCL
Serial Data Input/Output
Serial Clock Input
Write Protect Input
Power Supply
SCL
A , A , A
CAT24Cxx
SDA
2
1
0
WP
WP
V
CC
V
SS
Ground
NC
No Connect
V
SS
†The exposed pad for the UDFN packages can be left floating or
connected to Ground.
Figure 1. Functional Symbol
CAT24C__
1
2
1
2
3
Pin 1
Pin 1
A
16 / 08 / 04 / 02
V
/
/
/
/
/
8
7
6
5
NC NC NC
A
A
A
CC
1
2
3
4
0
1
2
A
B
C
V
CC
V
SS
V
CC
V
SS
/
/
/
WP
NC NC
A
1
A
2
SDA
/
NC
SCL
SDA
A
2
B
SCL
SDA
WP
SCL
V
SS
SOIC (W, X), TSSOP (Y),
UDFN−EP (HU4) (Top View)
WLCSP−4***
(Top Views)
WLCSP−5***
*** WLCSP are available for the CAT24C04,
CAT24C08 and CAT24C16 only.
TOP MARKING FOR WLCSP
(Ball Down)
5
4
SCL
WP
1
2
3
Pin 1
Pin 1
Pin 1
V
SS
X
Y M
X
Y W
X
SDA
V
CC
Y M
TSOT−23 (TD) (Top View)
WLCSP−4
WLCSP−4
WLCSP−5
(C4A)
(C4U)
X = Specific Device
X = Code
4 or R = 24C04
8 or T = 24C08
6 or V = 24C16
Y = Production Year (Last Digit)
M = Production Month (1−9, O, N, D)
W = Production Week
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2
CAT24C02, CAT24C04, CAT24C08, CAT24C16
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
°C
Storage Temperature
Voltage on any pin with respect to Ground (Note 1)
−65 to +150
−0.5 to +6.5
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. During input transitions, voltage undershoot on any pin should not exceed −1 V for more than 20 ns. Voltage overshoot on pins A , A , A
0
1
2
2
and WP should not exceed V + 1 V for more than 20 ns, while voltage on the I C bus pins, SCL and SDA, should not exceed the absolute
CC
maximum ratings, irrespective of V
.
CC
Table 3. RELIABILITY CHARACTERISTICS (Note 2)
Symbol Parameter
(Note 3)
Min
1,000,000
100
Units
Program / Erase Cycles
Years
N
Endurance
END
T
DR
Data Retention
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, V = 5 V, 25°C.
CC
Table 4. D.C. OPERATING CHARACTERISTICS
(V = 1.8 V to 5.5 V, T = −40°C to +125°C and V = 1.7 V to 5.5 V, T = −40°C to +85°C, unless otherwise specified.)
CC
A
CC
A
Symbol
Parameter
Test Conditions
Min
Max
Units
mA
I
Read Current
Write Current
Standby Current
Read, f
Write, f
= 400 kHz
= 400 kHz
1
2
1
CCR
SCL
I
mA
CCW
SCL
I
SB
All I/O Pins at GND or V
T = −40°C to +85°C
CC
mA
CC
A
V
≤ 3.3 V
T = −40°C to +85°C
CC
3
A
V
> 3.3 V
T = −40°C to +125°C
A
5
2
I
I/O Pin Leakage
Input Low Voltage
Input High Voltage
Pin at GND or V
mA
V
L
IL
IH
CC
V
−0.5
0.3 x V
CC
V
A , A , A and WP
0.7 x V
V + 0.5
CC
V
0
1
2
CC
CC
SCL and SDA
> 2.5 V, I = 3 mA
0.7 x V
5.5
V
Output Low
Voltage
V
V
0.4
0.2
OL
CC
OL
< 2.5 V, I = 1 mA
CC
OL
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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3
CAT24C02, CAT24C04, CAT24C08, CAT24C16
Table 5. PIN IMPEDANCE CHARACTERISTICS
(V = 1.8 V to 5.5 V, T = −40°C to +125°C and V = 1.7 V to 5.5 V, T = −40°C to +85°C, unless otherwise specified.)
CC
A
CC
A
Symbol
Parameter
SDA Pin Capacitance
Other Pins
Conditions
= 0 V, f = 1.0 MHz, V = 5.0 V
Max
8
Units
pF
C
(Note 4)
V
IN
IN
CC
6
pF
I
(Note 5)
WP Input Current
V
IN
V
IN
V
IN
< V , V = 5.5 V
130
120
80
2
mA
WP
IH
CC
< V , V = 3.3 V
IH
CC
< V , V = 1.7 V
IH
CC
V
IN
> V
IH
I
A
(Note 5)
Address Input Current
(A0, A1, A2)
Product Rev H: CAT24C02
Product Rev K: CAT24C04,
CAT24C08, CAT24C16
V
IN
V
IN
V
IN
< V , V = 5.5 V
50
35
25
2
mA
IH
CC
< V , V = 3.3 V
IH
CC
< V , V = 1.7 V
IH
CC
V
IN
> V
IH
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
5. When not driven, the WP, A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is
relatively strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To
conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull−down reverts to a weak
current source.
Table 6. A.C. CHARACTERISTICS
(Note 6) (V = 1.8 V to 5.5 V, T = −40°C to +125°C and V = 1.7 V to 5.5 V, T = −40°C to +85°C, unless otherwise specified.)
CC
A
CC
A
Standard
Fast
Min
Max
Min
Max
Symbol
Parameter
Units
kHz
ms
F
SCL
Clock Frequency
100
400
t
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
START Condition Setup Time
Data In Hold Time
4
4.7
4
0.6
1.3
0.6
0.6
0
HD:STA
t
ms
LOW
t
ms
HIGH
t
4.7
0
ms
SU:STA
HD:DAT
t
ms
t
Data In Setup Time
250
100
ns
SU:DAT
t
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Condition Setup Time
1000
300
300
300
ns
R
t (Note 6)
ns
F
t
4
0.6
1.3
ms
SU:STO
t
Bus Free Time Between STOP and START
SCL Low to Data Out Valid
Data Out Hold Time
4.7
ms
BUF
t
3.5
0.9
ms
AA
DH
t
100
100
ns
T (Note 6)
Noise Pulse Filtered at SCL and SDA Inputs
WP Setup Time
100
100
ns
i
t
0
0
ms
SU:WP
HD:WP
t
WP Hold Time
2.5
2.5
ms
t
Write Cycle Time
5
1
5
1
ms
ms
WR
t
(Notes 7, 8) Power−up to Ready Mode
PU
6. Test conditions according to “AC Test Conditions” table.
7. Tested initially and after a design or process change that affects this parameter.
8. t is the delay between the time V is stable and the device is ready to accept commands.
PU
CC
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4
CAT24C02, CAT24C04, CAT24C08, CAT24C16
Table 7. A.C. TEST CONDITIONS
Input Drive Levels
0.2 x V to 0.8 x V
CC
CC
Input Rise and Fall Time
Input Reference Levels
Output Reference Level
Output Test Load
v 50 ns
0.3 x V , 0.7 x V
CC
CC
0.5 x V
CC
Current Source I = 3 mA (V w 2.5 V); I = 1 mA (V < 2.5 V); C = 100 pF
OL
CC
OL
CC
L
Power−On Reset (POR)
During data transfer, the SDA line must remain stable
Each CAT24Cxx* incorporates Power−On Reset (POR)
circuitry which protects the internal logic against powering
up in the wrong state.
while the SCL line is high. An SDA transition while SCL is
high will be interpreted as a START or STOP condition
(Figure 2). The START condition precedes all commands. It
consists of a HIGH to LOW transition on SDA while SCL
is HIGH. The START acts as a ‘wake−up’ call to all
receivers. Absent a START, a Slave will not respond to
commands. The STOP condition completes all commands.
It consists of a LOW to HIGH transition on SDA while SCL
is HIGH.
A CAT24Cxx device will power up into Standby mode
after V exceeds the POR trigger level and will power
CC
down into Reset mode when V drops below the POR
CC
trigger level. This bi−directional POR feature protects the
device against ‘brown−out’ failure following a temporary
loss of power.
*For common features, the CAT24C02/04/08/16 will be
referred to as CAT24Cxx.
NOTE: The I/O pins of CAT24Cxx do not obstruct the SCL
and SDA lines if the VCC supply is switched off. During
power−up, the SCL and SDA pins (connected with pull−up
resistors to VCC) will follow the VCC monotonically from
VSS (0 V) to nominal VCC value, regardless of pull−up
resistor value. The delta between the VCC and the
instantaneous voltage levels during power ramping will be
determined by the relation between bus time constant
(determined by pull−up resistance and bus capacitance) and
actual VCC ramp rate.
Pin Description
SCL: The Serial Clock input pin accepts the Serial Clock
generated by the Master.
SDA: The Serial Data I/O pin receives input data and
transmits data stored in EEPROM. In transmit mode, this pin
is open drain. Data is acquired on the positive edge, and is
delivered on the negative edge of SCL.
A0, A1 and A2: The Address inputs set the device address
when cascading multiple devices. When not driven, these
pins are pulled LOW internally.
Device Addressing
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an 8−bit
serial Slave address. For normal Read/Write operations, the
first 4 bits of the Slave address are fixed at 1010 (Ah). The
next 3 bits are used as programmable address bits when
cascading multiple devices and/or as internal address bits.
The last bit of the slave address, R/W, specifies whether a
Read (1) or Write (0) operation is to be performed. The 3
address space extension bits are assigned as illustrated in
WP: The Write Protect input pin inhibits all write
operations, when pulled HIGH. When not driven, this pin is
pulled LOW internally.
Functional Description
The CAT24Cxx supports the Inter−Integrated Circuit
2
(I C) Bus data transmission protocol, which defines a device
that sends data to the bus as a transmitter and a device
receiving data as a receiver. Data flow is controlled by a
Master device, which generates the serial clock and all
START and STOP conditions. The CAT24Cxx acts as a
Slave device. Master and Slave alternate as either
transmitter or receiver.
Figure 3. A , A and A must match the state of the external
2
1
0
address pins, and a , a and a are internal address bits.
10
9
8
Acknowledge
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA line
during the 9th clock cycle (Figure 4). The Slave will also
acknowledge the address byte and every data byte presented
in Write mode. In Read mode the Slave shifts out a data byte,
I2C Bus Protocol
2
The I C bus consists of two ‘wires’, SCL and SDA. The
th
two wires are connected to the V supply via pull−up
CC
and then releases the SDA line during the 9 clock cycle. As
resistors. Master and Slave devices connect to the 2−wire
bus via their respective SCL and SDA pins. The transmitting
device pulls down the SDA line to ‘transmit’ a ‘0’ and
releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see AC Characteristics).
long as the Master acknowledges the data, the Slave will
continue transmitting. The Master terminates the session by
not acknowledging the last data byte (NoACK) and by
issuing a STOP condition. Bus timing is illustrated in
Figure 5.
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5
CAT24C02, CAT24C04, CAT24C08, CAT24C16
SCL
SDA
START
CONDITION
STOP
CONDITION
Figure 2. Start/Stop Timing
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
A
A
A
R/W
R/W
R/W
R/W
CAT24C02
CAT24C04
CAT24C08
CAT24C16
2
1
0
8
8
8
A
2
A
1
a
a
a
A
a
a
2
9
a
10
9
Figure 3. Slave Address Bits
BUS RELEASE DELAY (TRANSMITTER)
BUS RELEASE DELAY
(RECEIVER)
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACK SETUP (w t
)
SU:DAT
ACK DELAY (v t
)
START
AA
Figure 4. Acknowledge Timing
t
F
t
t
R
HIGH
t
t
LOW
LOW
SCL
t
t
HD:DAT
SU:STA
t
t
t
HD:SDA
SU:DAT
SU:STO
SDA IN
t
BUF
t
AA
t
DH
SDA OUT
Figure 5. Bus Timing
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6
CAT24C02, CAT24C04, CAT24C08, CAT24C16
WRITE OPERATIONS
Byte Write
sixteen bytes are received and the STOP condition has been
sent by the Master, the internal Write cycle begins. At this
point all received data is written to the CAT24Cxx in a single
write cycle.
In Byte Write mode, the Master sends the START
condition and the Slave address with the R/W bit set to zero
to the Slave. After the Slave generates an acknowledge, the
Master sends the byte address that is to be written into the
address pointer of the CAT24Cxx. After receiving another
acknowledge from the Slave, the Master transmits the data
byte to be written into the addressed memory location. The
CAT24Cxx device will acknowledge the data byte and the
Master generates the STOP condition, at which time the
device begins its internal Write cycle to nonvolatile memory
Acknowledge Polling
The acknowledge (ACK) polling routine can be used to
take advantage of the typical write cycle time. Once the stop
condition is issued to indicate the end of the host’s write
operation, the CAT24Cxx initiates the internal write cycle.
The ACK polling can be initiated immediately. This
involves issuing the start condition followed by the slave
address for a write operation. If the CAT24Cxx is still busy
with the write operation, NoACK will be returned. If the
CAT24Cxx has completed the internal write operation, an
ACK will be returned and the host can then proceed with the
next read or write operation.
(Figure 6). While this internal cycle is in progress (t ), the
SDA output will be tri−stated and the CAT24Cxx will not
respond to any request from the Master device (Figure 7).
WR
Page Write
The CAT24Cxx writes up to 16 bytes of data in a single
write cycle, using the Page Write operation (Figure 8). The
Page Write operation is initiated in the same manner as the
Byte Write operation, however instead of terminating after
the data byte is transmitted, the Master is allowed to send up
to fifteen additional bytes. After each byte has been
transmitted the CAT24Cxx will respond with an
acknowledge and internally increments the four low order
address bits. The high order bits that define the page address
remain unchanged. If the Master transmits more than sixteen
bytes prior to sending the STOP condition, the address
counter ‘wraps around’ to the beginning of page and
previously transmitted data will be overwritten. Once all
Hardware Write Protection
With the WP pin held HIGH, the entire memory is
protected against Write operations. If the WP pin is left
floating or is grounded, it has no impact on the operation of
the CAT24Cxx. The state of the WP pin is strobed on the last
falling edge of SCL immediately preceding the first data
byte (Figure 9). If the WP pin is HIGH during the strobe
interval, the CAT24Cxx will not acknowledge the data byte
and the Write request will be rejected.
Delivery State
The CAT24Cxx is shipped erased, i.e., all bytes are FFh.
S
T
A
R
T
BUS ACTIVITY:
MASTER
S
ADDRESS
BYTE
DATA
BYTE
T
O
P
SLAVE
ADDRESS
a
− a
d − d
7 0
7
0
S
P
A
C
K
A
C
K
A
C
K
SLAVE
Figure 6. Byte Write Sequence
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7
CAT24C02, CAT24C04, CAT24C08, CAT24C16
SCL
SDA
th
8
Bit
ACK
Byte n
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 7. Write Cycle Timing
S
T
A
R
T
BUS ACTIVITY:
MASTER
S
DATA
DATA
DATA
T
O
P
ADDRESS
BYTE
SLAVE
ADDRESS
BYTE
n+1
BYTE
n+P
BYTE
n
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
SLAVE
n = 1
P v 15
Figure 8. Page Write Sequence
ADDRESS
BYTE
DATA
BYTE
1
8
9
1
7
8
SCL
a
7
a
d
d
0
SDA
WP
0
t
SU:WP
t
HD:WP
Figure 9. WP Timing
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8
CAT24C02, CAT24C04, CAT24C08, CAT24C16
READ OPERATIONS
Immediate Read
address of the location it wishes to read. After the
CAT24Cxx acknowledges the byte address, the Master
device resends the START condition and the slave address,
this time with the R/W bit set to one. The CAT24Cxx then
responds with its acknowledge and sends the requested data
byte. The Master device does not acknowledge the data
(NoACK) but will generate a STOP condition (Figure 11).
Upon receiving a Slave address with the R/W bit set to ‘1’,
the CAT24Cxx will interpret this as a request for data
residing at the current byte address in memory. The
CAT24Cxx will acknowledge the Slave address, will
immediately shift out the data residing at the current address,
and will then wait for the Master to respond. If the Master
does not acknowledge the data (NoACK) and then follows
up with a STOP condition (Figure 10), the CAT24Cxx
returns to Standby mode.
Sequential Read
st
If during a Read session, the Master acknowledges the 1
data byte, then the CAT24Cxx will continue transmitting
data residing at subsequent locations until the Master
responds with a NoACK, followed by a STOP (Figure 12).
In contrast to Page Write, during Sequential Read the
address count will automatically increment to and then
wrap−around at end of memory (rather than end of page).
Selective Read
Selective Read operations allow the Master device to
select at random any memory location for a read operation.
The Master device first performs a ‘dummy’ write operation
by sending the START condition, slave address and byte
N
S
T
A
R
T
O
BUS ACTIVITY:
MASTER
S
A T
C O
K P
SLAVE
ADDRESS
S
P
A
DATA
C
SLAVE
8
BYTE
K
SCL
SDA
9
th
8
Bit
DATA OUT
NO ACK
STOP
Figure 10. Immediate Read Sequence and Timing
N
O
S
T
A
R
T
S
T
A
R
T
BUS ACTIVITY:
MASTER
S
A T
C O
K P
ADDRESS
BYTE
SLAVE
ADDRESS
SLAVE
ADDRESS
S
S
P
A
C
K
A
C
K
A
C
K
DATA
BYTE
SLAVE
Figure 11. Selective Read Sequence
N
O
BUS ACTIVITY:
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
SLAVE
ADDRESS
MASTER
P
A
C
K
SLAVE
DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+2
DATA
BYTE
n+x
Figure 12. Sequential Read Sequence
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9
CAT24C02, CAT24C04, CAT24C08, CAT24C16
PACKAGE DIMENSIONS
SOIC−8, 208 mils
CASE 751BE−01
ISSUE O
SYMBOL
MIN
NOM
MAX
A
A1
b
2.03
0.25
0.48
0.25
5.33
8.26
5.38
0.05
0.36
0.19
5.13
7.75
5.13
c
E
E1
D
E
E1
e
1.27 BSC
0.51
0.76
L
0º
8º
θ
PIN#1 IDENTIFICATION
TOP VIEW
D
A
q
e
b
L
c
A1
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with EIAJ EDR-7320.
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10
CAT24C02, CAT24C04, CAT24C08, CAT24C16
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD
ISSUE O
SYMBOL
MIN
NOM
MAX
1.35
A
A1
b
1.75
0.25
0.51
0.25
0.10
0.33
0.19
c
E1
E
D
E
E1
e
4.80
5.80
3.80
5.00
6.20
4.00
1.27 BSC
h
0.25
0.40
0º
0.50
1.27
8º
L
PIN # 1
IDENTIFICATION
θ
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
www.onsemi.com
11
CAT24C02, CAT24C04, CAT24C08, CAT24C16
PACKAGE DIMENSIONS
TSSOP8, 4.4x3
CASE 948AL
ISSUE O
b
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
1.20
0.15
1.05
0.30
0.20
3.10
6.50
4.50
0.05
0.80
0.19
0.09
2.90
6.30
4.30
0.90
E
c
E1
D
3.00
6.40
E
E1
e
4.40
0.65 BSC
1.00 REF
L
L1
0.50
0.60
0.75
0º
8º
θ
e
TOP VIEW
D
c
A2
A
q1
A1
L1
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
www.onsemi.com
12
CAT24C02, CAT24C04, CAT24C08, CAT24C16
PACKAGE DIMENSIONS
TSOT−23, 5 LEAD
CASE 419AE
ISSUE O
SYMBOL
MIN
NOM
MAX
1.00
0.10
0.90
0.45
0.20
D
A
A1
A2
b
e
0.01
0.80
0.30
0.12
0.05
0.87
c
0.15
D
2.90 BSC
2.80 BSC
1.60 BSC
0.95 TYP
0.40
E1
E
E
E1
e
L
0.30
0.50
L1
L2
θ
0.60 REF
0.25 BSC
0º
8º
TOP VIEW
A2 A
q
L
b
c
A1
L2
L1
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-193.
www.onsemi.com
13
CAT24C02, CAT24C04, CAT24C08, CAT24C16
PACKAGE DIMENSIONS
UDFN8, 2x3 EXTENDED PAD
CASE 517AZ
ISSUE O
b
D
e
A
L
DAP SIZE 1.8 x 1.8
E2
E
PIN #1
IDENTIFICATION
A1
PIN #1 INDEX AREA
D2
TOP VIEW
SIDE VIEW
BOTTOM VIEW
SYMBOL
MIN
0.45
0.00
NOM
MAX
0.55
0.05
A
A1
A3
b
0.50
0.02
0.127 REF
0.25
A3
A
DETAIL A
0.065 REF
0.20
1.95
1.35
2.95
1.25
0.30
2.05
1.45
3.05
1.35
D
2.00
FRONT VIEW
D2
E
1.40
3.00
E2
e
1.30
0.50 REF
0.30
L
0.25
0.35
0.065 REF
Copper Exposed
A3 0.0 - 0.05
DETAIL A
Notes:
(1) ꢀAll dimensions are in millimeters.
(2) Refer JEDEC MO-236/MO-252.
www.onsemi.com
14
CAT24C02, CAT24C04, CAT24C08, CAT24C16
PACKAGE DIMENSIONS
WLCSP4, 0.84x0.86
CASE 567NX
ISSUE A
NOTES:
A
B
D
E
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
PIN A1
REFERENCE
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DATUM C, THE SEATING PLANE, IS DEFINED BY
THE SPHERICAL CROWNS OF THE CONTACT
BALLS.
4. COPLANARITY APPLIES TO SPHERICAL CROWNS
OF THE CONTACT BALLS.
5. DIMENSION b IS MEASURED AT THE MAXIMUM
CONTACT BALL DIAMETER PARALLEL TO DATUM C.
A3
OPTIONAL
BACKSIDE COAT
TOP VIEW
A2
MILLIMETERS
DETAIL A
DIM
A
A1
A2
A3
b
D
E
e
MIN
−−−
0.08
NOM
−−−
0.10
0.15 REF
0.025 REF
0.18
MAX
0.30
0.12
A
DETAIL A
0.05
C
0.05
C
0.16
0.82
0.84
0.20
0.86
0.88
A1
SEATING
C
PLANE
0.84
0.86
NOTE 4
NOTE 3
SIDE VIEW
0.40 BSC
RECOMMENDED
e
4X
0.05 C A
0.03 C
b
B
SOLDERING FOOTPRINT*
e
A1
PACKAGE
OUTLINE
B
NOTE 5
A
1
2
BOTTOM VIEW
4X0.18
0.40
PITCH
0.40
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
15
CAT24C02, CAT24C04, CAT24C08, CAT24C16
PACKAGE DIMENSIONS
WLCSP4, 0.84x0.86
CASE 567DC
ISSUE D
NOTES:
A
B
D
E
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
PIN A1
REFERENCE
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DATUM C, THE SEATING PLANE, IS DEFINED BY
THE SPHERICAL CROWNS OF THE CONTACT
BALLS.
2X
0.10
0.10
C
C
4. COPLANARITY APPLIES TO SPHERICAL CROWNS
OF THE CONTACT BALLS.
5. DIMENSION b IS MEASURED AT THE MAXIMUM
CONTACT BALL DIAMETER PARALLEL TO DATUM C.
2X
A2
TOP VIEW
A3*
A
* Die Coat
(Optional)
MILLIMETERS
DIM
A
A1
A2
A3*
b
MIN
0.28
0.08
0.23 REF
0.025 REF
0.16 0.20
0.84 BSC
MAX
0.38
0.12
A2
DETAIL A
DETAIL A
A
0.10
C
D
E
e
0.86 BSC
0.40 BSC
0.05
C
SEATING
NOTE 4
C
* Die Coat (Optional)
A1
SIDE VIEW
PLANE
NOTE 3
RECOMMENDED
SOLDERING FOOTPRINT*
e
4X
b
e
A1
PACKAGE
OUTLINE
M
0.10
C A B
B
NOTE 5
A
1
2
4X0.18
0.40
PITCH
BOTTOM VIEW
0.40
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
16
CAT24C02, CAT24C04, CAT24C08, CAT24C16
PACKAGE DIMENSIONS
WLCSP5, 0.86x0.84
CASE 567DD
ISSUE C
NOTES:
A
B
D
E
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
PIN A1
REFERENCE
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DATUM C, THE SEATING PLANE, IS DEFINED BY THE
SPHERICAL CROWNS OF THE CONTACT BALLS.
4. COPLANARITY APPLIES TO SPHERICAL CROWNS
OF THE CONTACT BALLS.
2X
0.10
0.10
C
C
5. DIMENSION b IS MEASURED AT THE MAXIMUM CON-
TACT BALL DIAMETER PARALLEL TO DATUM C.
2X
TOP VIEW
MILLIMETERS
DIM
A
A1
A2
b
MIN
0.29
0.10
0.23 REF
0.14
MAX
0.39
0.14
A
A2
0.10
C
0.18
D
E
e
e1
0.86 BSC
0.84 BSC
0.30 BSC
0.52 BSC
0.05
C
5X
SEATING
PLANE
C
NOTE 3
A1
SIDE VIEW
RECOMMENDED
e
SOLDERING FOOTPRINT*
5X
b
e1
PACKAGE
A1
M
0.10
C A B
OUTLINE
C
B
A
NOTE 4
PIN A1
REFERENCE
1 2 3
5X0.16
0.52
PITCH
BOTTOM VIEW
0.30
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
17
CAT24C02, CAT24C04, CAT24C08, CAT24C16
Ordering Information
CAT24C02 Ordering Information (Notes 10, 11)
Specific
Device Marking
Package
Type
Temperature
Range (Note 9)
Lead
Finish
Device Order Number
Shipping
CAT24C02TDI−GT3A
C1
TSOT−23−5
Industrial
NiPdAu
Tape & Reel, 3,000 Units / Reel
CAT24C04 Ordering Information
Specific
Device Marking
Package
Type
Temperature
Range (Note 9)
Lead
Finish
Device Order Number
CAT24C04WI−GT3
CAT24C04XI−T2 (Note 17)
CAT24C04YI−GT3
Shipping
24C04K
TBD
C04K
R
SOIC−8
SOIC−8
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
NiPdAu
Tape & Reel, 3,000 Units / Reel
Matte−Tin Tape & Reel, 2,000 Units / Reel
TSSOP−8
WLCSP−4
WLCSP−4
WLCSP−5
TSOT−23−5
UDFN8−EP
NiPdAu
N/A
Tape & Reel, 3,000 Units / Reel
(Notes 12 and 13)
CAT24C04C4UTR
CAT24C04C4ATR
4
N/A
Tape & Reel, 5,000 Units / Reel
Tape & Reel, 5,000 Units / Reel
Tape & Reel, 3,000 Units / Reel
Tape & Reel, 3,000 Units / Reel
CAT24C04C5ATR
4
N/A
CAT24C04TDI−GT3
CAT24C04HU4I−GT3
C2
NiPdAu
NiPdAu
C2U
CAT24C08 Ordering Information
Specific
Device Marking
Package
Type
Temperature
Range (Note 9)
Lead
Finish
Device Order Number
CAT24C08WI−GT3
CAT24C08XI−T2 (Note 17)
CAT24C08YI−GT3
Shipping
24C08K
SOIC−8
SOIC−8
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
NiPdAu
Tape & Reel, 3,000 Units / Reel
TBD
C08K
T
Matte−Tin Tape & Reel, 2,000 Units / Reel
TSSOP−8
WLCSP−4
WLCSP−4
WLCSP−4
WLCSP−5
TSOT−23−5
UDFN8−EP
NiPdAu
N/A
Tape & Reel, 3,000 Units / Reel
(Notes 12 and 13)
CAT24C08C4UTR
CAT24C08C4ATR
8
N/A
Tape & Reel, 5,000 Units / Reel
Tape & Reel, 5,000 Units / Reel
Tape & Reel, 5,000 Units / Reel
Tape & Reel, 3,000 Units / Reel
Tape & Reel, 3,000 Units / Reel
CAT24C08C4CTR**
CAT24C08C5ATR
8
N/A
8
N/A
CAT24C08TDI−GT3
CAT24C08HU4I−GT3
C3
C3U
NiPdAu
NiPdAu
CAT24C16 Ordering Information
Specific
Device Marking
Package
Type
Temperature
Range (Note 9)
Lead
Finish
Device Order Number
CAT24C16WI−GT3
Shipping
24C16K
TBD
C16K
6
SOIC−8
SOIC−8
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Extended
NiPdAu
Tape & Reel, 3,000 Units / Reel
CAT24C16XI−T2 (Note 17)
CAT24C16YI−GT3
Matte−Tin Tape & Reel, 2,000 Units / Reel
TSSOP−8
WLCSP−4
WLCSP−4
WLCSP−5
TSOT−23−5
UDFN8−EP
UDFN8−EP
NiPdAu
N/A
Tape & Reel, 3,000 Units / Reel
(Notes 12 and 13)
CAT24C16C4UTR
CAT24C16C4ATR
6
N/A
Tape & Reel, 5,000 Units / Reel
Tape & Reel, 5,000 Units / Reel
Tape & Reel, 3,000 Units / Reel
Tape & Reel, 3,000 Units / Reel
Tape & Reel, 3,000 Units / Reel
CAT24C16C5ATR
6
N/A
CAT24C16TDI−GT3
CAT24C16HU4I−GT3
CAT24C16HU4E−GT3 (Note 17)
C4
NiPdAu
NiPdAu
NiPdAu
C4U
C4E
9. Industrial temperature range is −40°C to +85°C and Extended temperature range is −40°C to +125°C.
10.Part numbers ending with “A” for the CAT24C02 are for Gresham (Product Rev H) only die.
11. The CAT24C02 “non−A” Device Order Numbers use Gresham die (Rev H) for date codes, starting August 1st, 2012. Therefore the Specific
Device Marking for these OPNs reflect Rev H die.
12.Contact local sales office for availability.
13.CAUTION: The EEPROM devices delivered in WLCSP must never be exposed to ultraviolet light. When exposed to ultraviolet light the
EEPROM cells lose their stored data.
14.All packages are RoHS−compliant (Lead−free, Halogen−free).
15.For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
16.For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device
Nomenclature document, TND310/D, available at www.onsemi.com
17.In Development
** CAT24C08C4CTR is a backside coated version. Contact factory for other densities.
www.onsemi.com
18
CAT24C02, CAT24C04, CAT24C08, CAT24C16
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
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arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
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