CAT24C128HU3I-GT3 [ONSEMI]
128 kb I2C CMOS Serial EEPROM; 128 KB I2C CMOS串行EEPROM
| 型号： | CAT24C128HU3I-GT3 |
| 厂家： | 
ONSEMI |
| 描述： | 128 kb I2C CMOS Serial EEPROM |
| 文件： | 总14页 (文件大小：157K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT24C128
128 kb I2C CMOS Serial
EEPROM
Description
The CAT24C128 is a 128 kb Serial CMOS EEPROM, internally
organized as 16,384 words of 8 bits each.
http://onsemi.com
It features a 64−byte page write buffer and supports both the
2
Standard (100 kHz) as well as Fast (400 kHz) I C protocol.
Write operations can be inhibited by taking the WP pin High (this
protects the entire memory).
Features
PDIP−8
L SUFFIX
CASE 646AA
TSSOP−8
Y SUFFIX
CASE 948AL
2
• Supports Standard and Fast I C Protocol
• 1.8 V to 5.5 V Supply Voltage Range
• 64−Byte Page Write Buffer
• Hardware Write Protection for Entire Memory
2
• Schmitt Triggers and Noise Suppression Filters on I C Bus Inputs
(SCL and SDA)
SOIC−8
W SUFFIX
CASE 751BD
MSOP−8
Z SUFFIX
UDFN−8
HU3 SUFFIX
CASE 517AX
• Low Power CMOS Technology
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
CASE 846AD
PIN CONFIGURATION
• Industrial and Extended Temperature Range
• 8−lead PDIP, SOIC, TSSOP, MSOP and UDFN Packages
1
A
0
A
1
A
2
V
CC
• This Device is Pb−Free, Halogen Free/BFR Free and RoHS
WP
Compliant*
SCL
SDA
V
CC
V
SS
PDIP (L), SOIC (W), TSSOP (Y),
MSOP (Z), UDFN (HU3)
SCL
For the location of Pin 1, please consult the
corresponding package drawing.
CAT24C128
SDA
A , A , A
2
1
0
PIN FUNCTION
WP
Pin Name
Function
Device Address Inputs
Serial Data Input/Output
Serial Clock Input
Write Protect Input
Power Supply
A , A , A
0
1
2
V
SS
SDA
Figure 1. Functional Symbol
SCL
WP
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
V
CC
V
SS
Ground
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
1
Publication Order Number:
September, 2009 − Rev. 11
CAT24C128/D
CAT24C128
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Units
°C
Storage Temperature
−65 to +150
−0.5 to +6.5
Voltage on Any Pin with Respect to Ground (Note 1)
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than V + 0.5 V. During transitions, the voltage on any pin may
CC
undershoot to no less than −1.5 V or overshoot to no more than V + 1.5 V, for periods of less than 20 ns.
CC
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol
(Note 3)
Parameter
Min
1,000,000
100
Units
Program / Erase Cycles
Years
N
Endurance
END
T
DR
Data Retention
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, V = 5 V, 25°C
CC
Table 3. D.C. OPERATING CHARACTERISTICS (V = 1.8 V to 5.5 V, T = −40°C to +125°C, unless otherwise specified.)
CC
A
Symbol
Parameter
Read Current
Write Current
Standby Current
Test Conditions
Min
Max
1
Units
mA
I
Read, f
= 400 kHz
= 400 kHz
CCR
SCL
SCL
I
Write, f
3
mA
CCW
I
SB
All I/O Pins at GND or V
T = −40°C to +85°C
A
1
mA
CC
T = −40°C to +125°C
A
2
I
L
I/O Pin Leakage
Pin at GND or V
T = −40°C to +85°C
A
1
mA
CC
T = −40°C to +125°C
A
2
V
Input Low Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
−0.5
V
x 0.3
V
V
V
V
IL
CC
V
IH
V
x 0.7
V
CC
+ 0.5
CC
V
V
V
< 2.5 V, I = 3.0 mA
0.4
0.2
OL1
OL2
CC
OL
V
< 2.5 V, I = 1.0 mA
CC
OL
Table 4. PIN IMPEDANCE CHARACTERISTICS (V = 1.8 V to 5.5 V, T = −40°C to +125°C, unless otherwise specified.)
CC
A
Symbol
Parameter
SDA I/O Pin Capacitance
Conditions
Max
8
Units
pF
C
C
I
(Note 4)
(Note 4)
(Note 5)
V
IN
V
IN
V
IN
V
IN
= 0 V
= 0 V
IN
IN
Input Capacitance (other pins)
WP Input Current
6
pF
< V
200
1
mA
WP
IH
> V
mA
IH
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
5. When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively strong;
therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power, as
the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V ), the strong pull−down reverts to a weak current source.
CC
http://onsemi.com
2
CAT24C128
Table 5. A.C. CHARACTERISTICS (V = 1.8 V to 5.5 V, T = −40°C to +125°C) (Note 6)
CC
A
Standard
Fast
Min
Max
Min
Max
Symbol
Parameter
Units
kHz
ms
F
SCL
Clock Frequency
100
400
t
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
START Condition Setup Time
Data Hold Time
4
4.7
4
0.6
1.3
0.6
0.6
0
HD:STA
t
ms
LOW
t
ms
HIGH
t
4.7
0
ms
SU:STA
HD:DAT
t
ms
t
Data Setup Time
250
100
ns
SU:DAT
t
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Condition Setup Time
1000
300
300
300
ns
R
t (Note 7)
ns
F
t
4
0.6
1.3
ms
SU:STO
t
Bus Free Time Between STOP and START
SCL Low to SDA Data Out
Data Out Hold Time
4.7
ms
BUF
t
AA
3.5
0.9
ms
t
100
100
ns
DH
T (Note 7)
Noise Pulse Filtered at SCL and SDA Inputs
WP Setup Time
100
100
ns
i
t
0
0
ms
SU:WP
HD:WP
t
WP Hold Time
2.5
2.5
ms
t
Write Cycle Time
5
1
5
1
ms
ms
WR
t
(Notes 7 and 8)
Power−up to Ready Mode
PU
6. Test conditions according to “A.C. Test Conditions” table.
7. Tested initially and after a design or process change that affects this parameter.
8. t is the delay between the time V is stable and the device is ready to accept commands.
PU
CC
Table 6. A.C. TEST CONDITIONS
Input Levels
0.2 x V to 0.8 x V
CC CC
Input Rise and Fall Times
Input Reference Levels
Output Reference Levels
Output Load
v 50 ns
0.3 x V , 0.7 x V
CC
CC
0.5 x V
CC
Current Source: I = 3 mA (V ≥ 2.5 V); I = 1 mA (V < 2.5 V); C = 100 pF
OL
CC
OL
CC
L
http://onsemi.com
3
CAT24C128
Power−On Reset (POR)
resistors. Master and Slave devices connect to the 2−wire
bus via their respective SCL and SDA pins. The transmitting
device pulls down the SDA line to ‘transmit’ a ‘0’ and
releases it to ‘transmit’ a ‘1’.
The CAT24C128 incorporates Power−On Reset (POR)
circuitry which protects the device against powering up in
the wrong state.
The CAT24C128 will power up into Standby mode after
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
V
exceeds the POR trigger level and will power down into
CC
Reset mode when V drops below the POR trigger level.
This bi−directional POR feature protects the device against
‘brown−out’ failure following a temporary loss of power.
During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while SCL
is HIGH will be interpreted as a START or STOP condition
(Figure 2). The START condition precedes all commands. It
consists of a HIGH to LOW transition on SDA while SCL
is HIGH. The START acts as a ‘wake−up’ call to all
receivers. Absent a START, a Slave will not respond to
commands. The STOP condition completes all commands.
It consists of a LOW to HIGH transition on SDA while SCL
is HIGH.
CC
Pin Description
SCL: The Serial Clock input pin accepts the Serial Clock
generated by the Master.
SDA: The Serial Data I/O pin receives input data and
transmits data stored in EEPROM. In transmit mode, this pin
is open drain. Data is acquired on the positive edge, and is
delivered on the negative edge of SCL.
Device Addressing
A , A and A : The Address pins accept the device address.
0
1
2
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an 8−bit
serial Slave address. The first 4 bits of the Slave address are
set to 1010, for normal Read/Write operations (Figure 3).
The next 3 bits, A , A and A , select one of 8 possible Slave
When not driven, these pins are pulled LOW internally.
WP: The Write Protect input pin inhibits all write
operations, when pulled HIGH. When not driven, this pin is
pulled LOW internally.
2
1
0
devices and must match the state of the external address pins.
The last bit, R/W, specifies whether a Read (1) or Write (0)
operation is to be performed.
Functional Description
The CAT24C128 supports the Inter−Integrated Circuit
2
(I C) Bus data transmission protocol, which defines a device
Acknowledge
that sends data to the bus as a transmitter and a device
receiving data as a receiver. Data flow is controlled by a
Master device, which generates the serial clock and all
START and STOP conditions. The CAT24C128 acts as a
Slave device. Master and Slave alternate as either
transmitter or receiver. Up to 8 devices may be connected to
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA line
th
during the 9 clock cycle (Figure 4). The Slave will also
acknowledge all address bytes and every data byte presented
in Write mode. In Read mode the Slave shifts out a data byte,
th
and then releases the SDA line during the 9 clock cycle. As
the bus as determined by the device address inputs A , A ,
0
1
long as the Master acknowledges the data, the Slave will
continue transmitting. The Master terminates the session by
not acknowledging the last data byte (NoACK) and by
issuing a STOP condition. Bus timing is illustrated in
Figure 5.
and A .
2
2
I C Bus Protocol
2
The I C bus consists of two ‘wires’, SCL and SDA. The
two wires are connected to the V supply via pull−up
CC
http://onsemi.com
4
CAT24C128
SCL
SDA
START
CONDITION
STOP
CONDITION
Figure 2. START/STOP Conditions
DEVICE ADDRESS
A
2
A
1
A
0
R/W
1
0
1
0
Figure 3. Slave Address Bits
BUS RELEASE DELAY (TRANSMITTER)
1
BUS RELEASE DELAY (RECEIVER)
SCL FROM
MASTER
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACK SETUP (≥ t
)
SU:DAT
START
ACK DELAY (≤ t
)
AA
Figure 4. Acknowledge Timing
t
F
t
t
R
HIGH
t
t
LOW
LOW
SCL
t
t
HD:DAT
SU:STA
t
t
t
SU:DAT
SU:STO
HD:STA
SDA IN
t
BUF
t
AA
t
DH
SDA OUT
Figure 5. Bus Timing
http://onsemi.com
5
CAT24C128
Write Operations
latched and the address count automatically increments to
and then wraps−around at the page boundary. Previously
loaded data can thus be overwritten by new data. What is
eventually written to memory reflects the latest Page Write
Buffer contents. Only data loaded within the most recent
Page Write sequence will be written to memory.
Byte Write
Upon receiving a Slave address with the R/W bit set to ‘0’,
the CAT24C128 will interpret the next two bytes as address
bytes. These bytes are used to initialize the internal address
counter; the 2 most significant bits are ‘don’t care’, the next
8 point to one of 256 available pages and the last 6 point to
a location within a 64 byte page. A byte following the
address bytes will be interpreted as data. The data will be
loaded into the Page Write Buffer and will eventually be
written to memory at the address specified by the 14 active
address bits provided earlier. The CAT24C128 will
acknowledge the Slave address, address bytes and data byte.
The Master then starts the internal Write cycle by issuing a
STOP condition (Figure 6). During the internal Write cycle
Acknowledge Polling
The ready/busy status of the CAT24C128 can be
ascertained by sending Read or Write requests immediately
following the STOP condition that initiated the internal
Write cycle. As long as internal Write is in progress, the
CAT24C128 will not acknowledge the Slave address.
Hardware Write Protection
With the WP pin held HIGH, the entire memory is
protected against Write operations. If the WP pin is left
floating or is grounded, it has no impact on the operation of
the CAT24C128. The state of the WP pin is strobed on the
last falling edge of SCL immediately preceding the first data
byte (Figure 9). If the WP pin is HIGH during the strobe
interval, the CAT24C128 will not acknowledge the data byte
and the Write request will be rejected.
(t ), the SDA output will be tri−stated and additional Read
WR
or Write requests will be ignored (Figure 7).
Page Write
By continuing to load data into the Page Write Buffer after
st
the 1 data byte and before issuing the STOP condition, up
to 64 bytes can be written simultaneously during one
internal Write cycle (Figure 8). If more data bytes are loaded
than locations available to the end of page, then loading will
continue from the beginning of page, i.e. the page address is
Delivery State
The CAT24C128 is shipped erased, i.e., all bytes are FFh.
BUS ACTIVITY:
MASTER
S
T
A
R
T
ADDRESS
BYTE
ADDRESS
BYTE
a −a
7 0
S
T
O
P
DATA
BYTE
SLAVE
ADDRESS
a
13
−a
8
S
P
* *
A
C
K
A
C
K
A
C
K
A
C
K
SLAVE
* = Don’t Care Bit
Figure 6. Byte Write Sequence
SCL
SDA
8th Bit
Byte n
ACK
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 7. Write Cycle Timing
http://onsemi.com
6
CAT24C128
BUS ACTIVITY:
MASTER
S
T
A
R
T
ADDRESS
BYTE
ADDRESS
DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+P
S
T
O
P
BYTE
SLAVE
ADDRESS
a
−a
a −a
13
8
7
0
S
P
* *
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
SLAVE
* = Don’t Care Bit
P v 63
Figure 8. Page Write Sequence
ADDRESS
BYTE
DATA
BYTE
1
8
a
9
1
8
d
SCL
a
7
d
7
SDA
WP
0
0
t
SU:WP
t
HD:WP
Figure 9. WP Timing
Read Operations
Immediate Read
with data, the Master instead follows up with an Immediate
Read sequence, then the CAT24C128 will use the 14 active
address bits to initialize the internal address counter and will
shift out data residing at the corresponding location. If the
Master does not acknowledge the data (NoACK) and then
follows up with a STOP condition (Figure 11), the
CAT24C128 returns to Standby mode.
Upon receiving a Slave address with the R/W bit set to ‘1’,
the CAT24C128 will interpret this as a request for data
residing at the current byte address in memory. The
CAT24C128 will acknowledge the Slave address, will
immediately shift out the data residing at the current address,
and will then wait for the Master to respond. If the Master
does not acknowledge the data (NoACK) and then follows
up with a STOP condition (Figure 10), the CAT24C128
returns to Standby mode.
Sequential Read
If during a Read session the Master acknowledges the 1
st
data byte, then the CAT24C128 will continue transmitting
data residing at subsequent locations until the Master
responds with a NoACK, followed by a STOP (Figure 12).
In contrast to Page Write, during Sequential Read the
address count will automatically increment to and then
wrap−around at end of memory (rather than end of page).
Selective Read
To read data residing at a specific location, the internal
address counter must first be initialized as described under
Byte Write. If rather than following up the two address bytes
http://onsemi.com
7
CAT24C128
N
O
A
C
K
BUS ACTIVITY:
MASTER
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
S
P
A
C
K
DATA
BYTE
SLAVE
SCL
SDA
8
9
8th Bit
DATA OUT
NO ACK
STOP
Figure 10. Immediate Read Sequence and Timing
BUS ACTIVITY:
S
T
A
R
T
S
N
O
A
C
K
T
A
R
T
S
T
O
P
ADDRESS
BYTE
ADDRESS
BYTE
a −a
7 0
SLAVE
ADDRESS
SLAVE
ADDRESS
MASTER
a
−a
13
8
S
S
P
* *
A
C
K
A
C
K
A
C
K
A
C
K
DATA
BYTE
SLAVE
* = Don’t Care Bit
Figure 11. Selective Read Sequence
N
O
A T
C O
K P
BUS ACTIVITY:
S
SLAVE
ADDRESS
MASTER
P
A
C
K
A
C
K
A
C
K
A
C
K
DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+2
DATA
BYTE
n+x
SLAVE
Figure 12. Sequential Read Sequence
http://onsemi.com
8
CAT24C128
PACKAGE DIMENSIONS
PDIP−8, 300 mils
CASE 646AA−01
ISSUE A
SYMBOL
MIN
NOM
MAX
A
5.33
A1
A2
b
0.38
2.92
0.36
3.30
0.46
1.52
0.25
9.27
4.95
0.56
1.78
0.36
10.16
b2
c
1.14
0.20
9.02
E1
D
E
E1
e
7.62
6.10
7.87
6.35
8.25
7.11
2.54 BSC
7.87
2.92
10.92
3.80
eB
L
PIN # 1
IDENTIFICATION
3.30
D
TOP VIEW
E
A2
A1
A
c
b2
L
eB
e
b
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.
http://onsemi.com
9
CAT24C128
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
SYMBOL
MIN
NOM
MAX
1.35
A
A1
b
1.75
0.25
0.51
0.25
0.10
0.33
0.19
c
E1
E
D
E
E1
e
4.80
5.80
3.80
5.00
6.20
4.00
1.27 BSC
h
0.25
0.40
0º
0.50
1.27
8º
L
PIN # 1
IDENTIFICATION
θ
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
http://onsemi.com
10
CAT24C128
PACKAGE DIMENSIONS
TSSOP8, 4.4x3
CASE 948AL−01
ISSUE O
b
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
1.20
0.15
1.05
0.30
0.20
3.10
6.50
4.50
0.05
0.80
0.19
0.09
2.90
6.30
4.30
0.90
E
c
E1
D
3.00
6.40
E
E1
e
4.40
0.65 BSC
1.00 REF
0.60
L
L1
0.50
0.75
0º
8º
θ
e
TOP VIEW
D
c
A2
A
q1
A1
L1
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
http://onsemi.com
11
CAT24C128
PACKAGE DIMENSIONS
UDFN8, 2x3
CASE 517AX−01
ISSUE O
D
A
DETAIL A
DAP SIZE 1.3 x 1.8
E
PIN #1
IDENTIFICATION
E2
A1
PIN #1 INDEX AREA
D2
TOP VIEW
SIDE VIEW
BOTTOM VIEW
SYMBOL
MIN
0.45
0.00
NOM
MAX
0.55
0.05
b
A
A1
A3
b
0.50
0.02
L
0.127 REF
0.25
K
0.20
1.90
1.50
2.90
0.10
0.30
e
D
2.00
2.10
1.70
3.10
0.30
DETAIL A
D2
E
1.60
3.00
E2
e
0.20
0.50 TYP
0.10 REF
0.35
A3
K
A
L
0.30
0.40
A1
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MO-229.
FRONT VIEW
http://onsemi.com
12
CAT24C128
PACKAGE DIMENSIONS
MSOP 8, 3x3
CASE 846AD−01
ISSUE O
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
1.10
0.15
0.95
0.38
0.23
3.10
5.00
3.10
0.05
0.75
0.22
0.13
2.90
4.80
2.90
0.10
0.85
c
D
3.00
4.90
E
E1
E
E1
e
3.00
0.65 BSC
0.60
L
0.40
0.80
L1
L2
θ
0.95 REF
0.25 BSC
0º
6º
TOP VIEW
D
A2
A
DETAIL A
A1
e
b
c
SIDE VIEW
END VIEW
q
L2
Notes:
L
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-187.
L1
DETAIL A
http://onsemi.com
13
CAT24C128
Example of Ordering Information
Prefix
Device #
Suffix
CAT
24C128
Y
I
− G
T3
Tape & Reel (Note 9)
Temperature Range
Lead Finish
Company ID
T: Tape & Reel
3: 3000/Reel
G: NiPdAu
Blank: Matte−Tin
I = Industrial (−40°C to +85°C)
E = Extended (−40°C to +125°C)
Product Number
24C128
Package
L: PDIP
W: SOIC, JEDEC
Y: TSSOP
HU3: UDFN (2 x 3 mm)
Z: MSOP
9. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
ORDERABLE PART NUMBERS
Order Number
Order Number
CAT24C128LI−G
CAT24C128LE−G
CAT24C128WI−GT3
CAT24C128YI−GT3
CAT24C128HU3IGT3*
CAT24C128ZI−GT3
CAT24C128WE−GT3
CAT24C128YE−GT3
CAT24C128HU3EGT3*
CAT24C128ZE−GT3
*Part number is not exactly the same as the “Example of Ordering Information” shown above.
For part numbers marked with “*” there are NO hyphens in the orderable part numbers.
2
ON Semiconductor is licensed by Philips Corporation to carry the I C Bus Protocol.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
CAT24C128/D
相关型号：
CAT24C128LE
EEPROM, 16KX8, Serial, CMOS, PDIP8, 0.300 INCH, ROHS COMPLIANT, PLASTIC, MS-001, DIP-8
CATALYST
CAT24C128LE-G
EEPROM, 16KX8, Serial, CMOS, PDIP8, 0.300 INCH, ROHS COMPLIANT, PLASTIC, MS-001, DIP-8
CATALYST
©2020 ICPDF网 联系我们和版权申明