CAT24WC66LE-1.8-GT2 [ONSEMI]
8KX8 I2C/2-WIRE SERIAL EEPROM, PDIP8, 0.300 INCH, HALOGEN, BFR FREE AND ROHS COMPLIANT, PLASTIC, MS-001, DIP-8;
| 型号： | CAT24WC66LE-1.8-GT2 |
| 厂家： | 
ONSEMI |
| 描述： | 8KX8 I2C/2-WIRE SERIAL EEPROM, PDIP8, 0.300 INCH, HALOGEN, BFR FREE AND ROHS COMPLIANT, PLASTIC, MS-001, DIP-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 |
| 文件： | 总11页 (文件大小：136K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT24WC66
64-Kb I2C Serial EEPROM
with Partial Array Write
Protection
Description
http://onsemi.com
The CAT24WC66 is a 64−Kb Serial CMOS EEPROM internally
organized as 8192 words of 8 bits each. ON Semiconductor’s
advanced CMOS technology substantially reduces device power
requirements. The CAT24WC66 features a 32−byte page write buffer.
2
The device operates via the I C bus serial interface and is available in
8−pin PDIP or 8−pin SOIC packages.
Features
PDIP−8
SOIC−8
L SUFFIX
CASE 646AA
W or X SUFFIX
CASE 751BD
2
• 400 kHz I C Bus
• 1.8 V to 5.5 V Supply Voltage Range
• Cascadable for up to Eight Devices
• 32−byte Page Write Buffer
PIN CONFIGURATIONS
• Self−timed Write Cycle with Auto−clear
• Schmitt Trigger Inputs for Noise Protection
• Write Protection
1
A
A
A
V
0
1
2
CC
WP
SCL
SDA
− Top 1/4 Array Protected when WP at V
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
IH
V
SS
DIP Package (L)
1
• Industrial and Automotive Temperature Ranges
A
0
V
CC
• This Device is Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
A
1
WP
V
CC
SCL
SDA
A
2
V
SS
SOIC Package (W, X)
SCL
PIN FUNCTION
CAT24CW66
SDA
A , A , A
0
2
1
Pin Name
A0, A1, A2
SDA
Function
Device Address Inputs
Serial Data/Address
Serial Clock
WP
SCL
WP
Write Protect
V
SS
V
Power Supply
Ground
CC
Figure 1. Functional Symbol
V
SS
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
1
Publication Order Number:
August, 2009 − Rev. 10
CAT24WC66/D
CAT24WC66
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
°C
°C
V
Temperature Under Bias
–55 to +125
–65 to +150
Storage Temperature
Voltage on any Pin with Respect to Ground (Note 1)
–2.0 to V + 2.0
CC
V
with Respect to Ground
–2.0 to 7.0
1.0
V
CC
Package Power Dissipation Capability (T = 25°C)
W
A
Lead Soldering Temperature (10 secs)
Output Short Circuit Current (Note 2)
300
°C
mA
100
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is V + 0.5 V, which may overshoot to V + 2.0 V for periods of less than 20 ns.
CC
CC
2. Output shorted for no more than one second. No more than one output shorted at a time.
Table 2. REABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Reference Test Method
Min
Max
Units
NEND
(Note 3)
MIL−STD−883, Test Method 1033
1,000,000
Cycles / Byte
TDR
Data Retention
ESD Susceptibility
Latch−up
MIL−STD−883, Test Method 1008
MIL−STD−883, Test Method 3015
JEDEC Standard 17
100
2000
100
Years
Volts
mA
(Note 3)
VZAP
(Note 3)
ILTH
(Notes 3, 4)
3. This parameter is tested initially and after a design or process change that affects the parameter.
4. Latch−up protection is provided for stresses up to 100 mA on address and data pins from –1 V to V + 1 V.
CC
Table 3. D.C. OPERATING CHARACTERISTICS (V = 1.8 V to 5.5 V, unless otherwise specified.)
CC
Symbol
Parameter
Power Supply Current
Test Conditions
Min
Typ
Max
3
Units
mA
I
f
= 100 kHz
CC
SCL
I
Standby Current (V = 5 V)
V
V
= GND or V
= GND to V
1
mA
SB
CC
IN
CC
(Note 5)
I
Input Leakage Current
Output Leakage Current
Input Low Voltage
10
10
mA
mA
LI
IN
CC
I
LO
V
= GND to V
OUT CC
V
−1
V
x 0.3
V
V
V
V
IL
CC
V
Input High Voltage
V
x 0.7
V
CC
+ 0.5
IH
CC
V
OL1
V
OL2
Output Low Voltage (V = +3.0 V)
I
I
= 3.0 mA
= 1.5 mA
0.4
CC
OL
Output Low Voltage(V = +1.8 V)
0.5
CC
OL
5. Maximum standby current (ISB) = 10 mA for the Automotive and Extended Automotive temperature range.
Table 4. CAPACITANCE (T = 25°C, f = 1.0 MHz, V = 5 V)
A
CC
Symbol
Parameter
Conditions
Min
Typ
Max
Units
C
Input/Output Capacitance (SDA)
V
I/O
= 0 V
8
pF
I/O
(Note 3)
C
Input Capacitance
(A0, A1, A2, SCL, WP)
V
IN
= 0 V
6
pF
IN
(Note 3)
http://onsemi.com
2
CAT24WC66
Table 5. A.C. CHARACTERISTICS (V = 1.8 V to 5.5 V, unless otherwise specified. Output Load is 1TTL Gate and 100 pF.)
CC
1.8 V − 2.5 V
4.5 V − 5.5 V
Min
Max
Min
Max
Symbol
Parameter
Units
MEMORY READ & WRITE CYCLE LIMITS
FSCL
Clock Frequency
100
200
400
200
kHz
ns
T
I
Noise Suppression Time Constant at
SCL, SDA Inputs
(Note 6)
t
SCL Low to SDA Data Out and ACK Out
3.5
1
ms
ms
AA
t
Time the Bus Must be Free Before a
New Transmission Can Start
4.7
1.2
BUF
(Note 6)
t
Start Condition Hold Time
Clock Low Period
4
0.6
1.2
0.6
0.6
ms
ms
ms
ms
HD:STA
t
4.7
4
LOW
t
Clock High Period
HIGH
t
Start Condition Setup Time
(for a Repeated Start Condition)
4.7
SU:STA
t
Data In Hold Time
0
0
ns
ns
ms
HD:DAT
t
Data In Setup Time
SDA and SCL Rise Time
50
50
SU:DAT
t
R
1
0.3
(Note 6)
t
SDA and SCL Fall Time
300
300
ns
F
(Note 6)
t
Stop Condition Setup Time
Data Out Hold Time
4
0.6
ms
SU:STO
t
100
100
ns
DH
6. This parameter is tested initially and after a design or process change that affects the parameter.
Table 6. POWER−UP TIMING (Notes 6, 7)
Symbol
Parameter
Power−Up to Read Operation
Power−Up to Write Operation
Min
Typ
Max
1
Units
ms
t
PUR
t
1
ms
PUW
7. t
and t are the delays required from the time V is stable until the specified operation can be initiated.
PUW CC
PUR
Table 7. WRITE CYCLE LIMITS
Symbol
Parameter
Min
Typ
Max
Units
t
Write Cycle Time
10
ms
WR
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle.
During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond
to its slave address.
http://onsemi.com
3
CAT24WC66
Functional Description
The bidirectional serial data/address pin is used to transfer
all data into and out of the device. The SDA pin is an open
drain output and can be wire−ORed with other open drain or
open collector outputs.
2
The CAT24WC66 supports the I C Bus data transmission
protocol. This Inter−Integrated Circuit Bus protocol defines
any device that sends data to the bus to be a transmitter and
any device receiving data to be a receiver. The transfer is
controlled by the Master device which generates the serial
clock and all START and STOP conditions for bus access.
The CAT24WC66 operates as a Slave device. Both the
Master device and Slave device can operate as either
transmitter or receiver, but the Master device controls which
mode is activated.
A0, A1, A2: Device Address Inputs
These pins are hardwired or left unconnected (for
hardware compatibility with CAT24WC16). When
hardwired, up to eight CAT24WC66 devices may be
addressed on a single bus system (refer to Device
Addressing). When the pins are left unconnected, the default
values are zeros.
WP: Write Protect
This input, when tied to GND, allows write operations to
the entire memory. When this pin is tied to V , the top 1/4
array of memory is write protected. When left floating,
memory is unprotected.
Pin Description
SCL: Serial Clock
The serial clock input clocks all data transferred into or out
of the device.
CC
SDA: Serial Data/Address
t
F
t
R
t
HIGH
t
t
LOW
LOW
SCL
t
t
HD:DAT
SU:STA
t
t
SU:STO
t
SU:DAT
HD:STA
SDA IN
t
BUF
t
AA
t
DH
SDA OUT
Figure 2. Bus Timing
SCL
SDA
8TH BIT
BYTE n
ACK
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 3. Write Cycle Timing
SDA
SCL
START BIT
STOP BIT
Figure 4. Start/Stop Timing
http://onsemi.com
4
CAT24WC66
2
I C Bus Protocol
The features of the I C bus protocol are defined as
follows:
specifies whether a Read or Write operation is to be
performed. When this bit is set to 1, a Read operation is
selected, and when set to 0, a Write operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT24WC66 monitors the bus and
responds with an acknowledge (on the SDA line) when its
address matches the transmitted slave address. The
CAT24WC66 then performs a Read or Write operation
depending on the state of the R/W bit.
2
1. Data transfer may be initiated only when the bus is
not busy.
2. During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock line is high
will be interpreted as a START or STOP condition.
START Condition
Acknowledge
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of SDA
when SCL is HIGH. The CAT24WC66 monitors the SDA
and SCL lines and will not respond until this condition is
met.
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledging
device pulls down the SDA line during the ninth clock cycle,
signaling that it received the 8 bits of data.
The CAT24WC66 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation, it
responds with an acknowledge after receiving each 8−bit
byte.
When the CAT24WC66 begins a READ mode it transmits
8 bits of data, releases the SDA line, and monitors the line
for an acknowledge. Once it receives this acknowledge, the
CAT24WC66 will continue to transmit data. If no
acknowledge is sent by the Master, the device terminates
data transmission and waits for a STOP condition. The
master must then issue a stop condition to return the
CAT24WC66 to the standby power mode and place the
device in a known state.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
Device Addressing
The bus Master begins a transmission by sending a
START condition. The Master sends the address of the
particular slave device it is requesting. The four most
significant bits of the 8−bit slave address are fixed as 1010
(Figure 6). The next three bits (A2, A1, A0) are the device
address bits; up to eight 64K devices may to be connected to
the same bus. These bits must compare to the hardwired
input pins, A2, A1 and A0. The last bit of the slave address
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 5. Acknowledge Timing
1
0
1
0
A2
A1
A0
R/W
DEVICE ADDRESS
Figure 6. Slave Address Bits
http://onsemi.com
5
CAT24WC66
WRITE OPERATIONS
Byte Write
When all 32 bytes are received, and the STOP condition
has been sent by the Master, the internal programming cycle
begins. At this point, all received data is written to the
CAT24WC66 in a single write cycle.
In the Byte Write mode, the Master device sends the
START condition and the slave address information (with
the R/W bit set to zero) to the Slave device. After the Slave
generates an acknowledge, the Master sends two 8−bit
address words that are to be written into the address pointers
of the CAT24WC66. After receiving another acknowledge
from the Slave, the Master device transmits the data to be
written into the addressed memory location. The
CAT24WC66 acknowledges once more and the Master
generates the STOP condition. At this time, the device
begins an internal programming cycle to nonvolatile
memory. While the cycle is in progress, the device will not
respond to any request from the Master device.
Acknowledge Polling
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is issued
to indicate the end of the host’s write operation,
CAT24WC66 initiates the internal write cycle. ACK polling
can be initiated immediately. This involves issuing the start
condition followed by the slave address for a write
operation. If CAT24WC66 is still busy with the write
operation, no ACK will be returned. If CAT24WC66 has
completed the write operation, an ACK will be returned and
the host can then proceed with the next read or write
operation.
Page Write
The CAT24WC66 writes up to 32 bytes of data, in a single
write cycle, using the Page Write operation. The page write
operation is initiated in the same manner as the byte write
operation, however instead of terminating after the initial
byte is transmitted, the Master is allowed to send up to 31
additional bytes. After each byte has been transmitted,
CAT24WC66 will respond with an acknowledge, and
internally increment the five low order address bits by one.
The high order bits remain unchanged.
Write Protection
The Write Protection feature allows the user to protect
against inadvertent programming of the memory array. If the
WP pin is tied to VCC, the top 1/4 of the memory array
(locations 1800H to 1FFF) is protected and becomes read
only. The CAT24WC66 will accept both slave and byte
addresses, but the memory location accessed is protected
from programming by the device’s failure to send an
acknowledge after the first byte of data is received.
If the Master transmits more than 32 bytes before sending
the STOP condition, the address counter ‘wraps around’,
and previously transmitted data will be overwritten.
S
T
S
T
A
R
T
SLAVE
ADDRESS
BUS ACTIVITY:
MASTER
BYTE ADDRESS
−A A −A
0
O
P
DATA
A
15
8
7
SDA LINE
S
P
XX X
A
C
K
A
C
K
A
C
K
A
C
K
Figure 7. Byte Write Timing
S
T
A
R
T
S
T
BUS
ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE ADDRESS
−A A −A
0
O
P
DATA
DATA n
DATA n+31
A
15
8
7
SDA LINE
S
P
XX X
A
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
C
K
Figure 8. Page Write Timing
READ OPERATIONS
Immediate/Current Address Read
The READ operation for the CAT24WC66 is initiated in
the same manner as the write operation with one exception,
that R/W bit is set to one. Three different READ operations
are possible: Immediate/Current Address READ, Selective/
Random READ and Sequential READ.
The CAT24WC66’s address counter contains the address
of the last byte accessed, incremented by one. In other
words, if the last READ or WRITE access was to address N,
the READ immediately following would access data from
http://onsemi.com
6
CAT24WC66
Sequential Read
address N+1. If N=E (where E=8191), then the counter will
‘wrap around’ to address 0 and continue to clock out data.
After the CAT24WC66 receives its slave address
information (with the R/W bit set to one), it issues an
acknowledge, then transmits the 8 bit byte requested. The
master device does not send an acknowledge, but will
generate a STOP condition.
The Sequential READ operation can be initiated by either
the Immediate Address READ or Selective READ
operations. After the CAT24WC66 sends the initial 8−bit
byte requested, the Master will respond with an
acknowledge which tells the device it requires more data.
The CAT24WC66 will continue to output an 8−bit byte for
each acknowledge sent by the Master. The operation will
terminate when the Master fails to respond with an
acknowledge, thus sending the STOP condition.
The data being transmitted from CAT24WC66 is
outputted sequentially with data from address N followed by
data from address N+1. The READ operation address
counter increments all of the CAT24WC66 address bits so
that the entire memory array can be read during one
operation. If more than E (where E=8191) bytes are read out,
the counter will ‘wrap around’ and continue to clock out data
bytes.
Selective/Random Read
Selective/Random READ operations allow the Master
device to select at random any memory location for a READ
operation. The Master device first performs a ‘dummy’
write operation by sending the START condition, slave
address and byte addresses of the location it wishes to read.
After CAT24WC66 acknowledges, the Master device sends
the START condition and the slave address again, this time
with the R/W bit set to one. The CAT24WC66 then responds
with its acknowledge and sends the 8−bit byte requested.
The master device does not send an acknowledge but will
generate a STOP condition.
S
T
S
T
A
R
T
BUS ACTIVITY:
MASTER
SLAVE
O
P
ADDRESS
DATA
SDA LINE
S
P
A
C
K
N
O
A
C
K
SCL
SDA
8
9
8TH BIT
DATA OUT
NO ACK
STOP
Figure 9. Immediate Address Read Timing
S
T
A
R
T
S
T
S
T
A
R
T
BUS ACTIVITY:
MASTER
SLAVE
BYTE ADDRESS
−A A −A
0
SLAVE
O
P
ADDRESS
ADDRESS
DATA
A
15
8
7
SDA LINE
S
S
P
X X X
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
Figure 10. Selective Read Timing
S
T
O
P
BUS ACTIVITY:
SLAVE
MASTER ADDRESS
DATA n
DATA n+1
DATA n+2
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
Figure 11. Sequential Read Timing
http://onsemi.com
7
CAT24WC66
PACKAGE DIMENSIONS
PDIP−8, 300 mils
CASE 646AA−01
ISSUE A
SYMBOL
MIN
NOM
MAX
A
5.33
A1
A2
b
0.38
2.92
0.36
3.30
0.46
1.52
0.25
9.27
4.95
0.56
1.78
0.36
10.16
b2
c
1.14
0.20
9.02
E1
D
E
E1
e
7.62
6.10
7.87
6.35
8.25
7.11
2.54 BSC
7.87
2.92
10.92
3.80
eB
L
PIN # 1
IDENTIFICATION
3.30
D
TOP VIEW
E
A2
A1
A
c
b2
L
eB
e
b
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.
http://onsemi.com
8
CAT24WC66
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
SYMBOL
MIN
NOM
MAX
1.35
A
A1
b
1.75
0.25
0.51
0.25
0.10
0.33
0.19
c
E1
E
D
E
E1
e
4.80
5.80
3.80
5.00
6.20
4.00
1.27 BSC
h
0.25
0.40
0º
0.50
1.27
8º
L
PIN # 1
IDENTIFICATION
θ
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
http://onsemi.com
9
CAT24WC66
PACKAGE DIMENSIONS
SOIC−8, 208 mils
CASE 751BE−01
ISSUE O
SYMBOL
MIN
NOM
MAX
A
2.03
A1
b
0.05
0.36
0.19
5.13
7.75
5.13
0.25
0.48
0.25
5.33
8.26
5.38
c
E
E1
D
E
E1
e
1.27 BSC
0.51
0.76
L
0º
8º
θ
PIN#1 IDENTIFICATION
TOP VIEW
D
A
q
e
b
L
c
A1
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with EIAJ EDR-7320.
http://onsemi.com
10
CAT24WC66
Example of Ordering Information
Prefix
Device #
Suffix
CAT
24WC66
W
I
−1.8
−
G
T3
Rev C (Note 11)
Temperature Range
Lead Finish
Die Revision
24WC66: C
Company ID
Blank: Matte−Tin
G: NiPdAu
I = Industrial (−40°C to 85°C)
A = Automotive (−40°C to 105°C)
E = Extended (−40°C to 125°C)
Product Number
24WC66
Tape & Reel (Note 14)
T: Tape & Reel
Package
Operating Voltage
L: PDIP
W: SOIC, JEDEC
X: SOIC, EIAJ (Note 12)
Blank: V = 2.5 V to 5.5 V
2: 2000 / Reel (Note 12)
3: 3000 / Reel
CC
1.8: V = 1.8 V to 5.5 V
CC
8. All packages are RoHS-compliant (Lead-free, Halogen-free).
9. The standard lead finish is NiPdAu.
10.The device used in the above example is a CAT24W66WI−1.8−GT3 (SOIC, Industrial Temperature, 1.8 to 5.5 V Operating Voltage, NiPdAu,
Tape & Reel).
11. Product die revision letter is marked on top of the package as a suffix to the production date code (e.g. AYWWC). For additional information,
please contact your ON Semiconductor sales office.
12.For SOIC, EIAJ (X) package the standard lead finish is Matte-Tin. This package is available in 2000 pcs/reel, i.e. CAT24WC66XI-T2.
13.For additional package and temperature options, please contact your nearest ON Semiconductor sales office.
14.For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
2
ON Semiconductor is licensed by Philips Corporation to carry the I C Bus Protocol.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
CAT24WC66/D
相关型号：
CAT24WC66LE-1.8REV-C
8KX8 I2C/2-WIRE SERIAL EEPROM, PDIP8, LEAD AND HALOGEN FREE, PLASTIC, DIP-8
CATALYST
CAT24WC66LE-1.8REVC
EEPROM, 8KX8, Serial, CMOS, PDIP8, 0.300 INCH, ROHS COMPLIANT, PLASTIC, MS-001, DIP-8
CATALYST
CAT24WC66LE-REVC
EEPROM, 8KX8, Serial, CMOS, PDIP8, 0.300 INCH, ROHS COMPLIANT, PLASTIC, MS-001, DIP-8
CATALYST
©2020 ICPDF网 联系我们和版权申明