CAT25040YI-G [ONSEMI]
1-Kb, 2-Kb and 4-Kb SPI Serial CMOS EEPROM;
| 型号： | CAT25040YI-G |
| 厂家： | 
ONSEMI |
| 描述： | 1-Kb, 2-Kb and 4-Kb SPI Serial CMOS EEPROM 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 内存集成电路 |
| 文件： | 总15页 (文件大小：131K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT25010, CAT25020,
CAT25040
1-Kb, 2-Kb and 4-Kb SPI
Serial CMOS EEPROM
Description
The CAT25010/20/40 are 1−Kb/2−Kb/4−Kb Serial CMOS
EEPROM devices internally organized as 128x8/256x8/512x8 bits.
They feature a 16−byte page write buffer and support the Serial
Peripheral Interface (SPI) protocol. The device is enabled through a
Chip Select (CS) input. In addition, the required bus signals are a clock
input (SCK), data input (SI) and data output (SO) lines. The HOLD
input may be used to pause any serial communication with the
CAT25010/20/40 device. These devices feature software and
hardware write protection, including partial as well as full array
protection.
www.onsemi.com
SOIC−8
UDFN−8
V SUFFIX
CASE 751BD
HU4 SUFFIX
CASE 517AZ
Features
• 20 MHz (5 V) SPI Compatible
• 1.8 V to 5.5 V Supply Voltage Range
• SPI Modes (0,0) & (1,1)
PDIP−8*
L SUFFIX
CASE 646AA
TSSOP−8
Y SUFFIX
CASE 948AL
• 16−byte Page Write Buffer
• Self−timed Write Cycle
PIN CONFIGURATION
• Hardware and Software Protection
• Block Write Protection
1
CS
SO
WP
V
CC
HOLD
SCK
SI
− Protect 1/4, 1/2 or Entire EEPROM Array
• Low Power CMOS Technology
• 1,000,000 Program/Erase Cycles
V
SS
PDIP (L), SOIC (V),
TSSOP (Y), UDFN (HU4)
• 100 Year Data Retention
• Industrial and Extended Temperature Range
• PDIP, SOIC, TSSOP 8−Lead and UDFN 8−Pad Packages
• These Devices are Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
For the location of Pin 1, please consult the
corresponding package drawing.
* Not recommended for new designs
PIN FUNCTION
V
CC
Pin Name
CS
Function
Chip Select
SI
SO
Serial Data Output
Write Protect
CS
CAT25010
CAT25020
CAT25040
SO
WP
WP
V
SS
Ground
HOLD
SCK
SI
Serial Data Input
Serial Clock
SCK
HOLD
V
SS
Hold Transmission Input
Power Supply
Figure 1. Functional Symbol
V
CC
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 15 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
July, 2015 − Rev. 25
CAT25010/D
CAT25010, CAT25020, CAT25040
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
°C
Operating Temperature
Storage Temperature
−45 to +130
−65 to +150
°C
Voltage on any Pin with Respect to Ground (Note 1)
−0.5 to V + 0.5
V
CC
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol
(Note 3)
Parameter
Min
1,000,000
100
Units
Program / Erase Cycles
Years
N
Endurance
END
T
DR
Data Retention
Table 3. D.C. OPERATING CHARACTERISTICS
(V = 1.8 V to 5.5 V, T = −40°C to +85°C and V = 2.5 V to 5.5 V, T = −40°C to +125°C, unless otherwise specified.)
CC
A
CC
A
Symbol
Parameter
Test Conditions
Min
Max
Units
mA
I
Supply Current
Read, Write, V = 5.0 V,
10 MHz / −40°C to 85°C
5 MHz / −40°C to 125°C
2
2
2
CC
CC
SO open
mA
I
I
Standby Current
Standby Current
V
IN
= GND or V , CS = V
WP = V , V = 5.0 V
,
,
mA
SB1
CC
CC
CC
CC
V
IN
= GND or V , CS = V
T = −40°C to +85°C
4
5
2
1
2
mA
mA
mA
mA
mA
V
SB2
CC
CC
CC
A
WP = GND, V = 5.0 V
T = −40°C to +125°C
A
I
L
Input Leakage Current
V
IN
= GND or V
CC
−2
−1
I
LO
Output Leakage
Current
CS = V
,
T = −40°C to +85°C
A
CC
V
OUT
= GND or V
CC
T = −40°C to +125°C
A
−1
V
IL
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
−0.5
0.3 V
CC
V
IH
0.7 V
V + 0.5
CC
V
CC
V
V
CC
V
CC
V
CC
V
CC
> 2.5 V, I = 3.0 mA
0.4
V
OL1
OH1
OL
V
> 2.5 V, I = −1.6 mA
V
V
− 0.8 V
− 0.2 V
V
OH
CC
V
> 1.8 V, I = 150 mA
0.2
V
OL2
OH2
OL
V
> 1.8 V, I = −100 mA
V
OH
CC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Table 4. PIN CAPACITANCE (Note 2) (T = 25°C, f = 1.0 MHz, V = +5.0 V)
A
CC
Symbol
Test
Conditions
= 0 V
Min
Typ
Max
8
Units
pF
C
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI, WP, HOLD)
V
OUT
OUT
C
V
IN
= 0 V
8
pF
IN
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than V + 0.5 V. During transitions, the voltage on any pin may
CC
undershoot to no less than −1.5 V or overshoot to no more than V + 1.5 V, for periods of less than 20 ns.
CC
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, V = 5 V, 25°C.
CC
www.onsemi.com
2
CAT25010, CAT25020, CAT25040
Table 5. A.C. CHARACTERISTICS − Mature Product
(T = −40°C to +85°C (Industrial) and T = −40°C to +125°C (Extended).) (Notes 4, 8)
A
A
V
= 1.8 V − 5.5 V / −405C to +855C
= 2.5 V − 5.5 V / −405C to +1255C
V
= 2.5 V − 5.5 V
CC
CC
V
CC
−405C to +855C
Min
DC
40
Max
Min
Max
Symbol
Parameter
Units
f
Clock Frequency
5
DC
10
MHz
SCK
t
Data Setup Time
Data Hold Time
20
20
40
40
ns
ns
ns
ns
ns
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
SU
t
40
H
t
SCK High Time
75
WH
t
SCK Low Time
75
WL
t
HOLD to Output Low Z
Input Rise Time
50
2
25
2
LZ
t
RI
(Note 5)
(Note 5)
t
FI
Input Fall Time
2
2
t
t
HOLD Setup Time
HOLD Hold Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD to Output High Z
CS High Time
0
0
HD
CD
10
10
t
V
75
40
t
0
0
HO
t
50
20
25
DIS
t
100
HZ
t
140
30
30
20
20
10
10
70
15
15
15
15
10
10
CS
t
CS Setup Time
CSS
CSH
CNS
CNH
WPS
WPH
t
t
CS Hold Time
CS Inactive Setup Time
CS Inactive Hold Time
WP Setup Time
t
t
t
WP Hold Time
t
(Note 7)
Write Cycle Time
5
5
WC
Table 6. POWER−UP TIMING (Notes 5, 6)
Symbol
Parameter
Max
1
Units
t
Power−up to Read Operation
Power−up to Write Operation
ms
ms
PUR
t
1
PUW
4. AC Test Conditions:
Input Pulse Voltages: 0.3 V to 0.7 V
CC
CC
Input rise and fall times: ≤ 10 ns
Input and output reference voltages: 0.5 V
CC
Output load: current source I
/I
; C = 50 pF
OL max OH max L
5. This parameter is tested initially and after a design or process change that affects the parameter.
6. t
7. t
and t
are the delays required from the time V is stable until the specified operation can be initiated.
PUR
WC
PUW CC
is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
8. All Chip Select (CS) timing parameters are defined relative to the positive clock edge (Figure 2). t
timing specification is valid
CSH
for die revision D and higher. The die revision D is identified by letter “D” or a dedicated marking code on top of the package. For
previous product revision (Rev. C) the t
is defined relative to the negative clock edge (please refer to data sheet Doc. No.
CSH
MD−1006 Rev. U)
www.onsemi.com
3
CAT25010, CAT25020, CAT25040
Table 7. A.C. CHARACTERISTICS – New Product (Rev E)
(T = −40°C to +85°C (Industrial) and T = −40°C to +125°C (Extended), unless otherwise specified.) (Note 9)
A
A
V
CC
= 1.8 V − 5.5 V
V
CC
= 2.5 V − 5.5 V
V
CC
= 4.5 V − 5.5 V
−405C to +855C
−405C to +1255C
−405C to +855C
Min
DC
20
Max
Min
DC
10
Max
Min
DC
5
Max
Symbol
Parameter
Units
MHz
ns
f
Clock Frequency
5
10
20
SCK
t
Data Setup Time
Data Hold Time
SU
t
H
20
10
5
ns
t
SCK High Time
75
40
20
20
ns
WH
t
SCK Low Time
75
40
ns
WL
t
HOLD to Output Low Z
Input Rise Time
50
2
25
2
25
2
ns
LZ
t
RI
(Note 10)
(Note 10)
ms
t
FI
Input Fall Time
2
2
2
ms
t
HOLD Setup Time
HOLD Hold Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD to Output High Z
CS High Time
0
0
0
5
ns
HD
CD
t
10
10
ns
t
V
70
35
20
ns
t
0
0
0
ns
HO
t
50
20
25
20
25
ns
DIS
t
100
ns
HZ
t
80
30
30
20
20
10
10
40
30
30
20
20
10
10
20
15
20
15
15
10
10
ns
CS
t
CS Setup Time
ns
CSS
CSH
CNS
CNH
WPS
WPH
t
t
CS Hold Time
ns
CS Inactive Setup Time
CS Inactive Hold Time
WP Setup Time
ns
t
ns
t
ns
t
WP Hold Time
ns
t
(Note 12)
Write Cycle Time
5
5
5
ms
WC
Table 8. POWER−UP TIMING (Notes 10, 11)
Symbol
Parameter
Min
0.1
0.1
Max
1
Units
ms
t
Power−up to Read Operation
Power−up to Write Operation
PUR
t
1
ms
PUW
9. AC Test Conditions:
Input Pulse Voltages: 0.3 V to 0.7 V
CC
CC
Input rise and fall times: ≤ 10 ns
Input and output reference voltages: 0.5 V
CC
Output load: current source I
/I
; C = 30 pF
OL max OH max L
10.This parameter is tested initially and after a design or process change that affects the parameter.
11. t
12.t
and t
are the delays required from the time V is stable at the operating voltage until the specified operation can be initiated.
PUR
WC
PUW CC
is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
www.onsemi.com
4
CAT25010, CAT25020, CAT25040
Pin Description
Functional Description
The CAT25010/20/40 devices support the Serial
Peripheral Interface (SPI) bus protocol, modes (0,0) and
(1,1). The device contains an 8−bit instruction register. The
instruction set and associated op−codes are listed in Table 9.
Reading data stored in the CAT25010/20/40 is
accomplished by simply providing the READ command and
an address. Writing to the CAT25010/20/40, in addition to
a WRITE command, address and data, also requires
enabling the device for writing by first setting certain bits in
a Status Register, as will be explained later.
SI: The serial data input pin accepts op−codes, addresses
and data. In SPI modes (0,0) and (1,1) input data is latched
on the rising edge of the SCK clock input.
SO: The serial data output pin is used to transfer data out of
the device. In SPI modes (0,0) and (1,1) data is shifted out
on the falling edge of the SCK clock.
SCK: The serial clock input pin accepts the clock provided
by the host and used for synchronizing communication
between host and CAT25010/20/40.
CS: The chip select input pin is used to enable/disable the
CAT25010/20/40. When CS is high, the SO output is
tri−stated (high impedance) and the device is in Standby
Mode (unless an internal write operation is in progress).
Every communication session between host and
CAT25010/20/40 must be preceded by a high to low transition
and concluded with a low to high transition of the CS input.
After a high to low transition on the CS input pin, the
CAT25010/20/40 will accept any one of the six instruction
op−codes listed in Table 9 and will ignore all other possible
8−bit combinations. The communication protocol follows
the timing from Figure 2.
Table 9. INSTRUCTION SET (Note 13)
Instruction
WREN
WRDI
Opcode
0000 0110
0000 0100
0000 0101
0000 0001
0000 X011
0000 X010
Operation
WP: The write protect input pin will allow all write
operations to the device when held high. When WP pin is
tied low all write operations are inhibited.
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
HOLD: The HOLD input pin is used to pause transmission
between host and CAT25010/20/40, without having to
retransmit the entire sequence at a later time. To pause,
HOLD must be taken low and to resume it must be taken
back high, with the SCK input low during both transitions.
When not used for pausing, the HOLD input should be tied
RDSR
WRSR
READ
WRITE
13.X = 0 for CAT25010, CAT25020. X = A8 for CAT25040
to V , either directly or through a resistor.
CC
t
CS
CS
t
t
t
WL
CSS
WH
t
t
t
CNH
CSH
CNS
SCK
SI
t
H
t
RI
t
FI
t
SU
VALID
IN
t
V
t
V
t
DIS
t
HO
HI−Z
HI−Z
VALID
OUT
SO
Figure 2. Synchronous Data Timing
Status Register
The Status Register, as shown in Table 10, contains a
number of status and control bits.
Write Enable state and when set to 0, the device is in a Write
Disable state.
The RDY (Ready) bit indicates whether the device is busy
with a write operation. This bit is automatically set to 1 during
an internal write cycle, and reset to 0 when the device is ready
to accept commands. For the host, this bit is read only.
The WEL (Write Enable Latch) bit is set/reset by the
WREN/WRDI commands. When set to 1, the device is in a
The BP0 and BP1 (Block Protect) bits determine which
blocks are currently write protected. They are set by the user
with the WRSR command and are non−volatile. The user is
allowed to protect a quarter, one half or the entire memory,
by setting these bits according to Table 11. The protected
blocks then become read−only.
www.onsemi.com
5
CAT25010, CAT25020, CAT25040
Table 10. STATUS REGISTER
7
1
6
1
5
1
4
1
3
2
1
0
BP1
BP0
WEL
RDY
Table 11. BLOCK PROTECTION BITS
Status Register Bits
BP1
BP0
Array Address Protected
Protection
No Protection
0
0
1
1
0
1
0
1
None
CAT25010: 060−07F, CAT25020: 0C0−0FF, CAT25040: 180−1FF
CAT25010: 040−07F, CAT25020: 080−0FF, CAT25040: 100−1FF
CAT25010: 000−07F, CAT25020: 000−0FF, CAT25040: 000−1FF
Quarter Array Protection
Half Array Protection
Full Array Protection
WRITE OPERATIONS
The CAT25010/20/40 device powers up into a write
disable state. The device contains a Write Enable Latch
(WEL) which must be set before attempting to write to the
memory array or to the status register. In addition, the
address of the memory location(s) to be written must be
outside the protected area, as defined by BP0 and BP1 bits
from the status register.
instruction to the CAT25010/20/40. Care must be taken to
take the CS input high after the WREN instruction, as
otherwise the Write Enable Latch will not be properly set.
WREN timing is illustrated in Figure 3. The WREN
instruction must be sent prior to any WRITE or WRSR
instruction.
The internal write enable latch is reset by sending the
WRDI instruction as shown in Figure 4. Disabling write
operations by resetting the WEL bit, will protect the device
against inadvertent writes.
Write Enable and Write Disable
The internal Write Enable Latch and the corresponding
Status Register WEL bit are set by sending the WREN
CS
SCK
1
1
0
SI
0
0
0
0
0
HIGH IMPEDANCE
SO
Dashed Line = mode (1, 1)
Figure 3. WREN Timing
CS
SCK
1
0
0
SI
0
0
0
0
0
HIGH IMPEDANCE
SO
Dashed Line = mode (1, 1)
Figure 4. WRDI Timing
www.onsemi.com
6
CAT25010, CAT25020, CAT25040
Byte Write
Page Write
Once the WEL bit is set, the user may execute a write
sequence, by sending a WRITE instruction, a 8−bit address
and data as shown in Figure 5. For the CAT25040, bit 3 of
the write instruction opcode contains A8 address bit.
Internal programming will start after the low to high CS
transition. During an internal write cycle, all commands,
except for RDSR (Read Status Register) will be ignored.
The RDY bit will indicate if the internal write cycle is in
progress (RDY high), or the device is ready to accept
commands (RDY low).
After sending the first data byte to the CAT25010/20/40,
the host may continue sending data, up to a total of 16 bytes,
according to timing shown in Figure 6. After each data byte,
the lower order address bits are automatically incremented,
while the higher order address bits (page address) remain
unchanged. If during this process the end of page is
exceeded, then loading will “roll over” to the first byte in the
page, thus possibly overwriting previously loaded data.
Following completion of the write cycle, the
CAT25010/20/40 is automatically returned to the write
disable state.
CS
0
1
2
3
4
5
6
7
8
13 14 15 16 17 18 19 20 21 22 23
SCK
SI
OPCODE
X*
DATA IN
BYTE ADDRESS
A
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
1
0
A
7
HIGH IMPEDANCE
Dashed Line = mode (1, 1)
SO
* X = 0 for CAT25010, CAT25020. x = A8 for CAT25040
Figure 5. Byte WRITE Timing
CS
16+(N−1)x8−1..16+(N−1)x8
13 14 15 16−23 24−31
0
1
2
3
4
5
6
7
8
16+Nx8−1
SCK
SI
Data Byte N
7..1
BYTEADDRESS
OPCODE
X*
DATA IN
A
7
A
0
0
0
0
0
0
1
0
0
Data Data Data
Byte 1 Byte 2 Byte 3
HIGH IMPEDANCE
SO
Dashed Line = mode (1, 1)
* X = 0 for CAT25010, CAT25020. x = A8 for CAT25040
Figure 6. Page WRITE Timing
www.onsemi.com
7
CAT25010, CAT25020, CAT25040
Write Status Register
Write Protection
The Status Register is written by sending a WRSR
instruction according to timing shown in Figure 7. Only bits
2 and 3 can be written using the WRSR command.
When WP input is low all write operations to the memory
array and Status Register are inhibited. WP going low while
CS is still low will interrupt a write operation. If the internal
write cycle has already been initiated, WP going low will
have no effect on any write operation to the Status Register
or memory array. The WP input timing is shown in Figure 8.
CS
0
1
2
3
4
5
6
7
1
8
9
6
10
5
11
4
12
13
2
14
1
15
0
SCK
SI
OPCODE
0
DATA IN
3
0
0
0
0
0
0
7
MSB
HIGH IMPEDANCE
Dashed Line = mode (1, 1)
SO
Figure 7. WRSR Timing
t
t
WPH
WPS
CS
SCK
WP
WP
Dashed Line = mode (1, 1)
Figure 8. WP Timing
www.onsemi.com
8
CAT25010, CAT25020, CAT25040
READ OPERATIONS
Read Status Register
Read from Memory Array
To read from memory, the host sends a READ instruction
followed by a 8−bit address (for the CAT25040, bit 3 of the
read instruction opcode contains A8 address bit).
To read the status register, the host simply sends a RDSR
command. After receiving the last bit of the command, the
CAT25010/20/40 will shift out the contents of the status
register on the SO pin (Figure 10). The status register may
be read at any time, including during an internal write cycle.
While the internal write cycle is in progress, the RDSR
command will output the full content of the status register
(New product, Rev. E) or the RDY (Ready) bit only (i.e.,
data out = FFh) for previous product revisions C, D (Mature
product). For easy detection of the internal write cycle
completion, both during writing to the memory array and to
the status register, we recommend sampling the RDY bit
only through the polling routine. After detecting the RDY bit
“0”, the next RDSR instruction will always output the
expected content of the status register.
After receiving the last address bit, the CAT25010/20/40
will respond by shifting out data on the SO pin (as shown in
Figure 9). Sequentially stored data can be read out by simply
continuing to run the clock. The internal address pointer is
automatically incremented to the next higher address as data
is shifted out. After reaching the highest memory address,
the address counter “rolls over” to the lowest memory
address, and the read cycle can be continued indefinitely.
The read operation is terminated by taking CS high.
CS
12 13 14 15 16 17 18 19 20 21 22
0
1
2
3
4
5
6
7
8
9
SCK
SI
OPCODE
X*
BYTE ADDRESS
A
0
A
7
0
0
0
0
0
1
1
DATA OUT
HIGH IMPEDANCE
SO
D7 D6 D5 D4 D3 D2 D1 D0
MSB
Dashed Line = mode (1, 1)
* X = 0 for CAT25010, CAT25020. X = A8 for CAT25040
Figure 9. READ Timing
CS
0
1
2
3
4
5
1
6
0
7
1
8
9
10
11
12
13
14
SCK
OPCODE
0
0
0
0
0
SI
DATA OUT
3
HIGH IMPEDANCE
Dashed Line = mode (1, 1)
5
7
6
4
2
1
0
SO
MSB
Figure 10. RDSR Timing
www.onsemi.com
9
CAT25010, CAT25020, CAT25040
Hold Operation
VCC drops below the POR trigger level. This bi−directional
The HOLD input can be used to pause communication
between host and CAT25010/20/40. To pause, HOLD must
be taken low while SCK is low (Figure 11). During the hold
condition the device must remain selected (CS low). During
the pause, the data output pin (SO) is tri−stated (high
impedance) and SI transitions are ignored. To resume
communication, HOLD must be taken high while SCK is low.
POR behavior protects the device against ‘brown−out’
failure following a temporary loss of power.
The CAT25010/20/40 device powers up in a write disable
state and in a low power standby mode. A WREN instruction
must be issued prior to any writes to the device.
After power up, the CS pin must be brought low to enter
a ready state and receive an instruction. After a successful
byte/page write or status register write, the device goes into
a write disable mode. The CS input must be set high after the
proper number of clock cycles to start the internal write
cycle. Access to the memory array during an internal write
cycle is ignored and programming is continued. Any invalid
op−code will be ignored and the serial output pin (SO) will
remain in the high impedance state.
Design Considerations
The CAT25010/20/40 devices incorporate Power−On
Reset (POR) circuitry which protects the internal logic
against powering up in the wrong state. The device will
power up into Standby mode after VCC exceeds the POR
trigger level and will power down into Reset mode when
CS
t
t
CD
CD
SCK
t
HD
t
HD
HOLD
SO
t
HZ
HIGH IMPEDANCE
t
LZ
Dashed Line = mode (1, 1)
Figure 11. HOLD Timing
www.onsemi.com
10
CAT25010, CAT25020, CAT25040
PACKAGE DIMENSIONS
PDIP−8, 300 mils
CASE 646AA−01
ISSUE A
SYMBOL
MIN
NOM
MAX
A
5.33
A1
A2
b
0.38
2.92
0.36
3.30
0.46
1.52
0.25
9.27
4.95
0.56
1.78
0.36
10.16
b2
c
1.14
0.20
9.02
E1
D
E
E1
e
7.62
6.10
7.87
6.35
8.25
7.11
2.54 BSC
7.87
2.92
10.92
3.80
eB
L
PIN # 1
IDENTIFICATION
3.30
D
TOP VIEW
E
A2
A1
A
c
b2
L
eB
e
b
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.
www.onsemi.com
11
CAT25010, CAT25020, CAT25040
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
SYMBOL
MIN
NOM
MAX
1.35
A
A1
b
1.75
0.25
0.51
0.25
0.10
0.33
0.19
c
E1
E
D
E
E1
e
4.80
5.80
3.80
5.00
6.20
4.00
1.27 BSC
h
0.25
0.40
0º
0.50
1.27
8º
L
PIN # 1
IDENTIFICATION
θ
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
www.onsemi.com
12
CAT25010, CAT25020, CAT25040
PACKAGE DIMENSIONS
TSSOP8, 4.4x3
CASE 948AL−01
ISSUE O
b
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
1.20
0.15
1.05
0.30
0.20
3.10
6.50
4.50
0.05
0.80
0.19
0.09
2.90
6.30
4.30
0.90
E
c
E1
D
3.00
6.40
E
E1
e
4.40
0.65 BSC
1.00 REF
0.60
L
L1
0.50
0.75
0º
8º
θ
e
TOP VIEW
D
c
A2
A
q1
A1
L1
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
www.onsemi.com
13
CAT25010, CAT25020, CAT25040
PACKAGE DIMENSIONS
UDFN8, 2x3 EXTENDED PAD
CASE 517AZ−01
ISSUE O
b
D
e
A
L
DAP SIZE 1.8 x 1.8
E2
E
PIN #1
IDENTIFICATION
A1
PIN #1 INDEX AREA
D2
TOP VIEW
SIDE VIEW
BOTTOM VIEW
SYMBOL
MIN
0.45
0.00
NOM
MAX
0.55
0.05
A
A1
A3
b
0.50
0.02
0.127 REF
0.25
A3
A
DETAIL A
0.065 REF
0.20
1.95
1.35
2.95
1.25
0.30
2.05
1.45
3.05
1.35
D
2.00
FRONT VIEW
D2
E
1.40
3.00
E2
e
1.30
0.50 REF
0.30
L
0.25
0.35
0.065 REF
Copper Exposed
A3 0.0 - 0.05
DETAIL A
Notes:
(1) ꢀAll dimensions are in millimeters.
(2) Refer JEDEC MO-236/MO-252.
www.onsemi.com
14
CAT25010, CAT25020, CAT25040
ORDERING INFORMATION
Specific
Device
Marking
(Note 14)
Device Order Number
Package Type
UDFN8−EP
PDIP−8
Temperature Range
−40°C to +85°C
Lead Finish
NiPdAu
Shipping
3,000 Units / Tape & Reel
Tube, 50 Units
CAT25010HU4I−GT3
S0U
CAT25010LI−G
(Note 17)
25010E
−40°C to +85°C
NiPdAu
CAT25010VI−G
CAT25010VI−GT3
CAT25010YI−G
CAT25010YI−GT3
25010E
25010E
S01E
SOIC−8, JEDEC
SOIC−8, JEDEC
TSSOP−8
−40°C to +125°C
−40°C to +125°C
−40°C to +85°C
−40°C to +85°C
NiPdAu
NiPdAu
NiPdAu
NiPdAu
Tube, 100 Units
3,000 Units / Tape & Reel
Tube, 100 Units
S01E
TSSOP−8
3,000 Units / Tape & Reel
CAT25020HU4I−GT3
S1U
UDFN8−EP
PDIP−8
−40°C to +85°C
−40°C to +85°C
NiPdAu
NiPdAu
3,000 Units / Tape & Reel
Tube, 50 Units
CAT25020LI−G
(Note 17)
25020E
CAT25020VI−G
CAT25020VI−GT3
CAT25020YI−G
CAT25020YI−GT3
25020E
25020E
S02E
SOIC−8, JEDEC
SOIC−8, JEDEC
TSSOP−8
−40°C to +125°C
−40°C to +125°C
−40°C to +85°C
−40°C to +85°C
NiPdAu
NiPdAu
NiPdAu
NiPdAu
Tube, 100 Units
3,000 Units / Tape & Reel
Tube, 100 Units
S02E
TSSOP−8
3,000 Units / Tape & Reel
CAT25040HU4I−GT3
S2U
UDFN8−EP
PDIP−8
−40°C to +85°C
−40°C to +85°C
NiPdAu
NiPdAu
3,000 Units / Tape & Reel
Tube, 50 Units
CAT25040LI−G
(Note 17)
25040E
CAT25040VI−G
CAT25040VI−GT3
CAT25040YI−G
CAT25040YI−GT3
25040E
25040E
S04E
SOIC−8, JEDEC
SOIC−8, JEDEC
TSSOP−8
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
NiPdAu
NiPdAu
NiPdAu
NiPdAu
Tube, 100 Units
3,000 Units / Tape & Reel
Tube, 100 Units
S04E
TSSOP−8
3,000 Units / Tape & Reel
14.Specific Device Marking shows the first row top marking for new product (Revision E).
15.All packages are RoHS−compliant (Lead−free, Halogen−free).
16.The standard lead finish is NiPdAu.
17.Not recommended for new designs.
18.For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
19.For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device
Nomenclature document, TND310/D, available at www.onsemi.com
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
CAT25010/D
相关型号：
©2020 ICPDF网 联系我们和版权申明