CAT25C64PE [ONSEMI]
CAT25C64PE;
| 型号： | CAT25C64PE |
| 厂家： | 
ONSEMI |
| 描述： | CAT25C64PE 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总11页 (文件大小：403K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT25C32/64
32K/64K-Bit SPI Serial CMOS EEPROM
FEATURES
■ 1,000,000 program/erase cycles
■ 100 year data tetention
■ 10 MHz SPI compatible
■ 1.8 to 6.0 volt operation
■ Hardware and software protection
■ Low power CMOS technology
■ SPI modes (0,0 &1,1)
■ Self-timed write cycle
■ 8-pin DIP/SOIC and 14-pin TSSOP
■ 64-Byte page write buffer
■ Block write protection
■ Commercial, industrial and automotive
– Protect 1/4, 1/2 or all of EEPROM array
temperature ranges
DESCRIPTION
required to access the device. The HOLD pin may be
used to suspend any serial communication without
resetting the serial sequence. The CAT25C32/64 is
designed with software and hardware write protection
features including Block write protection. The device is
available in 8-pin DIP, 8-pin SOIC, 14-pin TSSOP and
20-pin TSSOP packages.
The CAT25C32/64 is a 32K/64K-Bit SPI Serial CMOS
EEPROM internally organized as 4Kx8/8Kx8 bits.
Catalyst’s advanced CMOS Technology substantially
reduces device power requirements. The CAT25C32/
64 features a 64-byte page write buffer. The device
operates via the SPI bus serial interface and is enabled
thoughaChipSelect(CS). InadditiontotheChipSelect,
the clock input (SCK), data in (SI) and data out (SO) are
PIN CONFIGURATION
DIP Package (P, L, GL)
SOIC Package (S, V, GV)
TSSOP Package (U14, Y14)
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
V
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VCC
HOLD
NC
NC
NC
V
CS
SO
WP
CS
SO
NC
NC
NC
WP
CS
SO
CC
CC
HOLD
SCK
SI
HOLD
SCK
SI
WP
V
V
SS
SS
SCK
SI
V
SS
BLOCK DIAGRAM
SENSE AMPS
SHIFT REGISTERS
PIN FUNCTIONS
COLUMN
DECODERS
WORD ADDRESS
BUFFERS
Pin Name
Function
SO
Serial Data Output
Serial Clock
SO
SI
I/O
CONTROL
SCK
WP
VCC
VSS
CS
E2PROM
ARRAY
CS
SPI
CONTROL
LOGIC
XDEC
Write Protect
WP
HOLD
SCK
+1.8V to +6.0V Power Supply
Ground
BLOCK
PROTECT
LOGIC
Chip Select
DATA IN
STORAGE
SI
Serial Data Input
Suspends Serial Input
HOLD
HIGH VOLTAGE/
TIMING CONTROL
NC
No Connect
STATUS
REGISTER
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1001, Rev. J
1
CAT25C32/64
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
Voltage on any Pin with
Respect to VSS1) ................... –2.0V to +VCC +2.0V
V
CC with Respect to VSS................................ –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Min.
1,000,000
100
Max.
Units
Cycles/Byte
Years
(3)
NEND
(3)
TDR
Data Retention
ESD Susceptibility
Latch-Up
(3)
VZAP
2000
Volts
(3)(4)
ILTH
100
mA
D.C. OPERATING CHARACTERISTICS
= +1.8V to +6.0V, unless otherwise specified.
V
CC
Limits
Typ.
Symbol
Parameter
Min.
Max.
Units
Test Conditions
ICC1
Power Supply Current
(Operating Write)
10
mA
mA
µA
VCC = 5V @ 10MHz
SO=open; CS=Vss
ICC2
Power Supply Current
(Operating Read)
2
1
VCC = 5.0V
FCLK = 10MHz
(5)
ISB
Power Supply Current
(Standby)
CS = VCC
VIN = VSS or VCC
ILI
Input Leakage Current
Output Leakage Current
2
3
µA
µA
ILO
VOUT = 0V to VCC
,
CS = 0V
(3)
VIL
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
-1
VCC x 0.3
VCC + 0.5
0.4
V
V
V
V
(3)
VIH
VCC x 0.7
VOL1
VOH1
4.5V≤V <5.5V
CC
= 3.0mA
= -1.6mA
I
I
OL
OH
VCC - 0.8
VOL2
VOH2
Output Low Voltage
Output High Voltage
0.2
V
V
1.8V≤VCC<2.7V
VCC-0.2
IOL = 150µA
IOH = -100µA
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V +2.0V for periods of less than 20 ns.
CC
CC
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) These parameter are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.
CC
(5) Maximum standby current (I ) = 10µA for the Automotive and Extended Automotive temperature range.
SB
Doc. No. 1001, Rev. J
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
2
CAT25C32/64
(1)
PIN CAPACITANCE
Applicable over recommended operating range from TA=25˚C, f=1.0 MHz, VCC=+5.0V (unless otherwise noted).
Symbol
COUT
CIN
Test Conditions
Max.
Units
pF
Conditions
VOUT=0V
VIN=0V
Output Capacitance (SO)
8
6
Input Capacitance (CS, SCK, SI, WP, HOLD)
pF
A.C. CHARACTERISTICS
Limits
Vcc=
1.8V-6.0V
VCC
2.5V-6.0V
=
VCC
4.5V-5.5V
Max. Min. Max. UNITS Conditions
=
Test
SYMBOL PARAMETER
Min. Max. Min.
tSU
tH
Data Setup Time
Data Hold Time
50
50
50
50
20
20
40
40
DC
ns
ns
ns
ns
MHz
ns
µs
µs
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
tWH
tWL
fSCK
tLZ
SCK High Time
250
250
DC
125
125
DC
SCK Low Time
Clock Frequency
HOLD to Output Low Z
Input Rise Time
1
50
2
3
50
2
10
50
2
(1)
tRI
CL = 50pF
(1)
tFI
Input Fall Time
2
2
2
tHD
HOLD Setup Time
HOLD Hold Time
Write Cycle Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD to Output High Z
CS High Time
100
100
100
100
40
40
tCD
tWC
tV
10
10
5
250
250
80
tHO
tDIS
tHZ
0
0
0
250
150
250
100
75
50
tCS
500
500
500
250
250
250
200
100
100
tCSS
tCSH
NOTE:
CS Setup Time
CS Hold Time
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. 1001, Rev. J
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
CAT25C32/64
FUNCTIONAL DESCRIPTION
PIN DESCRIPTION
The CAT25C32/64 supports the SPI bus data
transmissionprotocol.ThesynchronousSerialPeripheral
Interface (SPI) helps the CAT25C32/64 to interface
directly with many of today’s popular microcontrollers.
TheCAT25C32/64containsan8-bitinstructionregister.
(Theinstructionset andtheoperationcodesaredetailed
in the instruction set table)
SI: Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses, and data to be written to the
25C32/64. Input data is latched on the rising edge of the
serial clock.
SO: Serial Output
SO is the serial data output pin. This pin is used to
transfer data out of the 25C32/64. During a read cycle,
data is shifted out on the falling edge of the serial clock.
After the device is selected with CS going low, the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK.
Thefirstbytecontainsoneofthesixop-codesthatdefine
the operation to be performed.
SCK: Serial Clock
SCKistheserialclockpin.Thispinisusedtosynchronize
Figure 1. Sychronous Data Timing
t
CS
VIH
CS
VIL
t
CSH
t
CSS
VIH
VIL
t
t
WL
SCK
SI
WH
t
t
H
SU
VIH
VALID IN
V
IL
t
RI
FI
t
t
V
t
t
HO
DIS
VOH
VOL
HI-Z
HI-Z
SO
Note: Dashed Line= mode (1, 1) — — — —
INSTRUCTION SET
Instruction
WREN
WRDI
Opcode
Operation
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
RDSR
WRSR
READ
WRITE
(1)(2)
Power-Up Timing
Symbol
tPUR
Parameter
Max.
Units
ms
Power-up to Read Operation
Power-up to Write Operation
1
1
tPUW
ms
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t and t are the delays required from the time V is stable until the specified operation can be initiated.
PUR
PUW
CC
Doc. No. 1001, Rev. J
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
4
CAT25C32/64
the communication between the microcontroller and the
25C32/64.Opcodes,byteaddresses,ordatapresenton
theSIpinarelatchedontherisingedgeoftheSCK. Data
on the SO pin is updated on the falling edge of the SCK.
will interrupt a write to the status register. If the internal
write cycle has already been initiated, WP going low will
have no effect on any write operation to the status
register.TheWPpinfunctionisblockedwhentheWPEN
bit is set to 0.
CS: Chip Select
HOLD: Hold
CSistheChipselectpin.CSlowenablestheCAT25C32/
64 and CS high disables the CAT25C32/64. CS high
takes the SO output pin to high impedance and forces
the devices into a Standby Mode (unless an internal
write operation is underway). The CAT25C32/64 draws
ZERO current in the Standby mode. A high to low
transition on CS is required prior to any sequence being
initiated. A low to high transition on CS after a valid write
sequence is what initiates an internal write cycle.
The HOLD pin is used to pause transmission to the
CAT25C32/64 while in the middle of a serial sequence
without having to re-transmit entire sequence at a later
time. To pause, HOLD must be brought low while SCK
islow.TheSOpinisinahighimpedancestateduringthe
timethepartispaused, andtransitionsontheSIpinswill
beignored.Toresumecommunication,HOLDisbrought
high, while SCK is low. (HOLD should be held high any
time this function is not being used.) HOLD may be tied
high directly to Vcc or tied to Vcc through a resistor.
Figure 9 illustrates hold timing sequence.
WP: Write Protect
WP is the Write Protect pin. The Write Protect pin will
allow normal read/write operations when held high.
When WP is tied low and the WPEN bit in the status
register is set to “1”, all write operations to the status
register are inhibited. WP going low while CS is still low
STATUS REGISTER
7
6
5
4
3
2
1
0
WPEN
X
X
X
BP1
BP0
WEL
RDY
BLOCK PROTECTION BITS
Status Register Bits
Array Address
Protected
Protection
BP1
0
BP0
0
None
No Protection
0
1
25C32: 0C00-0FFF
25C64:1800-1FFF
Quarter Array Protection
Half Array Protection
Full Array Protection
1
1
0
1
25C32: 800-0FFF
25C64:1000-1FFF
25C32: 0000-0FFF
25C64:0000-1FFF
WRITE PROTECT ENABLE OPERATION
Protected
Blocks
Unprotected
Blocks
Status
WPEN
WP
X
WEL
Register
0
0
1
1
X
X
0
1
0
1
0
1
Protected
Protected
Protected
Protected
Protected
Protected
Protected
Writable
Protected
Writable
Protected
Writable
Protected
Writable
X
Low
Low
High
High
Protected
Protected
Protected
Writable
Doc. No. 1001, Rev. J
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
CAT25C32/64
The WPEN (Write Protect Enable) is an enable bit for the
WP pin. The WP pin and WPEN bit in the status register
controltheprogrammablehardwarewriteprotectfeature.
HardwarewriteprotectionisenabledwhenWPis lowand
WPENbitissettohigh.Theusercannotwritetothestatus
register (including the block protect bits and the WPEN
bit) and the block protected sections in the memory array
when the chip is hardware write protected. Only the
sections of the memory array that are not block protected
can be written. Hardware write protection is disabled
when either WP pin is high or the WPEN bit is zero.
STATUS REGISTER
The Status Register indicates the status of the device.
TheRDY(Ready)bitindicateswhethertheCAT25C32/
64 is busy with a write operation. When set to 1 a write
cycle is in progress and when set to 0 the device
indicates it is ready. This bit is read only.
The WEL (Write Enable) bit indicates the status of the
write enable latch . When set to 1, the device is in a
Write Enable state and when set to 0 the device is in a
Write Disable state. The WEL bit can only be set by the
WREN instruction and can be reset by the WRDI
instruction.
DEVICE OPERATION
Write Enable and Disable
The BP0 and BP1 (Block Protect) bits indicate which
blocksarecurrentlyprotected. Thesebitsaresetbythe
user issuing the WRSR instruction. The user is allowed
to protect quarter of the memory, half of the memory or
theentirememorybysettingthesebits. Onceprotected
the user may only read from the protected portion of the
array. These bits are non-volatile.
The CAT25C32/64 contains a write enable latch. This
latch must be set before any write operation. The device
powers up in a write disable state when Vcc is applied.
WREN instruction will enable writes (set the latch) to
thedevice. WRDI instruction will disable writes (reset the
latch) to the device. Disabling writes will protect the
device against inadvertent writes.
Figure 2. WREN Instruction Timing
CS
SK
1
1
0
SI
0
0
0
0
0
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) — — — —
Figure 3. WRDI Instruction Timing
CS
SK
SI
1
0
0
0
0
0
0
0
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) — — — —
Doc. No. 1001, Rev. J
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
6
CAT25C32/64
READ Sequence
sent. The contents of the status register are shifted out on
the SO line. The status register may be read at any time
even during a write cycle. Read sequece is illustrated in
Figure 4. Reading status register is illustrated in Figure 5.
WRITE Sequence
The part is selected by pulling CS low. The 8-bit read
instruction is transmitted to the CAT25C32/64, fol-
lowed by the 16-bit address(the three Most Significant
Bits are don’t care for 25C64 and four most significant
bits are don't care for 25C32).
TheCAT25C32/64powersupinaWriteDisablestate.Prior
to any write instructions, the WREN instruction must be
sent to CAT25C32/64. The device goes into Write enable
state by pulling the CS low and then clocking the WREN
instruction into CAT25C32/64. The CS must be brought
high after the WREN instruction to enable writes to the
device. If the write operation is initiated immediately after
the WREN instruction without CS being brought high, the
data will not be written to thearray because the write enable
latch will not have been properly set. Also, for a successful
write operation the address of the memory location(s) to be
programmed must be outside the protected address field
location selected by the block protection level.
After the correct read instruction and address are sent,
the data stored in the memory at the selected address
is shifted out on the SO pin. The data stored in the
memory at the next address can be read sequentially
by continuing to provide clock pulses. The internal
address pointer is automatically incremented to the
next higher address after each byte of data is shifted
out. When the highest address (1FFFh for 25C64 and
FFFh for 25C32) is reached, the address counter rolls
over to 0000h allowing the read cycle to be continued
indefinitely. The readoperation is terminated by pulling
the CS high.
Toreadthestatusregister,RDSRinstructionshouldbe
Figure 4. Read Instruction Timing
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30
SK
OPCODE
BYTE ADDRESS*
SI
0
0
0
0
0
0
1
1
DATA OUT
HIGH IMPEDANCE
SO
7
6
5
4
3
2
1
0
MSB
*Please check the instruction set table for address
Note: Dashed Line= mode (1, 1) — — — —
Figure 5. RDSR Instruction Timing
CS
0
1
2
3
4
5
1
6
0
7
1
8
9
10
11
12
13
14
SCK
OPCODE
0
0
0
0
0
SI
DATA OUT
HIGH IMPEDANCE
SO
5
7
6
4
3
2
1
0
MSB
Note: Dashed Line= mode (1, 1) — — — —
Doc. No. 1001, Rev. J
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
7
CAT25C32/64
Byte Write
are internally incremented by one; the high order bits of
address will remain constant. The only restriction is that the
64 bytes must reside on the same page. If the address
counter reaches the end of the page and clock continues,
the counter will “roll over” to the first address of the page
and overwrite any data that may have been written. The
CAT25C32/64 is automatically returned to the write disable
state at the completion of the write cycle. Figure 8 illustrates
the page write sequence.
Once the device is in a Write Enable state, the user
may proceed with a write sequence by setting the CS
low, issuing a write instruction via the SI line, followed
by the 16-bit address (the three Most Significant Bits
are don’t care for 25C64 and four most significant bits
are don't care for 25C32), and then the data to be
written. ProgrammingwillstartaftertheCSisbrought
high. Figure 6 illustrates byte write sequence.
During an internal write cycle, all commands will be
ignored except the RDSR (Read Status Register)
instruction.
To write to the status register, the WRSR instruction should
be sent. Only Bit 2, Bit 3 and Bit 7 of the status register can
be written using the WRSR instruction. Figure 7 illustrates
the sequence of writing to status register.
The Status Register can be read to determine if the
write cycle is still in progress. If Bit 0 of the Status
Register is set at 1, write cycle is in progress. If Bit 0
is set at 0, the device is ready for the next instruction.
DESIGN CONSIDERATIONS
The CAT25C32/64 powers up in a write disable state and
in a low power standby mode. A WREN instruction must be
issued to perform any writes to the device after power up.
Also,onpowerupCSshouldbebroughtlowtoenteraready
state and receive an instruction. After a successful byte/
page write or status register write the CAT25C32/64 goes
into a write disable mode. CS must be set high after the
Page Write
The CAT25C32/64 features page write capability.
After the first initial byte the host may continue to write
upto64bytesof datatotheCAT25C32/64.Aftereach
byte of data is received, six lower order address bits
Figure 6. Write Instruction Timing
CS
0
1
2
3
4
5
6
7
8
21 22 23 24 25 26 27 28 29 30 31
SK
SI
OPCODE
DATA IN
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
1
0
ADDRESS
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) – – – –
Figure 7. WRSR Instruction Timing
CS
0
1
2
3
4
5
6
7
1
8
7
9
6
10
5
11
4
12
13
2
14
1
15
0
SCK
OPCODE
DATA IN
SI
0
0
0
0
0
0
0
3
MSB
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) — — — —
Doc. No. 1001, Rev. J
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
8
CAT25C32/64
proper number of clock cycles to start an internal write When powering down, the supply should be taken down
cycle. Access to the array during an internal write cycle to 0V, so that the CAT25C32/64 will be reset when
is ignored and program-ming is continued. On power up, power is ramped back up. If this is not possible, then,
SO is in a high impedance.
following a brown-out episode, the CAT25C32/64 can
be reset by refreshing the contents of the Status Regis-
ter (See Application Note AN10).
Figure 8. Page Write Instruction Timing
CS
24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1
0
1
2
3
4
5
6
7
8
21 22 23
32-39
24-31
SK
SI
DATA IN
Data Data
Byte 2 Byte 3
OPCODE
Data
Byte 1
Data Byte N
0
0
0
0
0
0
1
0
ADDRESS
0
7..1
HIGH IMPEDANCE
SO
Note: Dashed Line = mode (1, 1) – – – –
Figure 9. HOLD Timing
CS
t
t
CD
CD
SCK
t
HD
t
HD
HOLD
SO
t
HZ
HIGH IMPEDANCE
t
LZ
Note: Dashed Line= mode (1, 1) — — — —
Doc. No. 1001, Rev. J
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
9
CAT25C32/64
ORDERING INFORMATION
Prefix
Device #
25C64
Suffix
-1.8
S
CAT
TE13
I
Product
Temperature Range
Tape & Reel
Optional
Company ID
Number
Blank = Commercial (0°C to +70°C)
I = Industrial (-40°C to +85°C)
A = Automotive (-40°C to +105°C)
25C32: 32K
25C64: 64K
E = Extended (-40°C to +125°C)
Operating Voltage
Blank = 2.5 to 6.0V
1.8 = 1.8 to 6.0V
Package
P: PDIP
S: SOIC
U14: 14-pin TSSOP
L: PDIP (Lead free, Halogen free)
V: SOIC, JEDEC (Lead free, Halogen free)
Y14: 14-pin TSSOP (Lead free, Halogen free)
GL: PDIP (Lead-free, Halogen-free, NiPdAu lead plating)
GV: SOIC, JEDEC (Lead-free, Halogen-free, NiPdAu lead plating)
Notes:
(1) The device used in the above example is a 25C64SI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating Voltage,
Tape & Reel)
Doc. No. 1001, Rev. J
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
10
REVISION HISTORY
Date
Rev.
Reason
8/4/2004
F
Updated Features
Updated DC Operating Characteristics table & notes
03/29/05
07/08/05
G
H
Update Reliability Characteristics
Update Instruction Set - Power-Up Timing
Update Features
Update Pin Configuation
Update Ordering Information
09/22/05
08/22/08
I
Update Pin Configuation
Archived data sheet.
J
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Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Publication #: 1001
Phone: 408.542.1000
Revison:
J
Fax: 408.542.1200
Issue date:
08/22/08
www.caalyst-semiconductor.com
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