CAT25M01 [ONSEMI]
1 Mb SPI Serial CMOS EEPROM; 有1 Mb SPI串行EEPROM CMOS
| 型号： | CAT25M01 |
| 厂家： | 
ONSEMI |
| 描述： | 1 Mb SPI Serial CMOS EEPROM |
| 文件： | 总14页 (文件大小：180K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT25M01
1 Mb SPI Serial CMOS
EEPROM
Description
The CAT25M01 is a 1M−bit Serial CMOS EEPROM device
internally organized as 128Kx8 bits. This features a 256−byte page
write buffer and supports the Serial Peripheral Interface (SPI)
protocol. The device is enabled through a Chip Select (CS) input. In
addition, the required bus signals are clock input (SCK), data input
(SI) and data output (SO) lines. The HOLD input may be used to pause
any serial communication with the CAT25M01 device. The device
features software and hardware write protection, including partial as
well as full array protection.
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TSSOP−8
Y SUFFIX
CASE 948AL
SOIC−8
V SUFFIX
SOIC−8
X SUFFIX
CASE 751BD
CASE 751BE
On−Chip ECC (Error Correction Code) makes the device suitable
for high reliability applications.
PIN CONFIGURATION
Features
• 10 MHz SPI Compatible
• 1.8 V to 5.5 V Supply Voltage Range
• SPI Modes (0,0) & (1,1)
V
CS
SO
WP
1
CC
HOLD
SCK
SI
V
SS
• 256−byte Page Write Buffer
• Additional Identification Page with Permanent Write Protection
• Self−timed Write Cycle
SOIC (V, X),
TSSOP (Y)
(Top View)
• Hardware and Software Protection
• Block Write Protection –
PIN FUNCTION
Protect 1/4, 1/2 or Entire EEPROM Array
• Low Power CMOS Technology
Pin Name
CS
Function
Chip Select
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
SO
Serial Data Output
Write Protect
• Industrial and Extended Temperature Range
• 8 lead SOIC and TSSOP Packages
WP
V
SS
Ground
• This Device is Pb−Free, Halogen Free/BFR Free and is RoHS
SI
Serial Data Input
Serial Clock
Compliant
SCK
V
CC
HOLD
Hold Transmission Input
Power Supply
V
CC
SI
CS
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
CAT25M01
SO
WP
HOLD
SCK
V
SS
Figure 1. Functional Symbol
© Semiconductor Components Industries, LLC, 2012
1
Publication Order Number:
October, 2012 − Rev. 0
CAT25M01/D
CAT25M01
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter
Ratings
Units
°C
Operating Temperature
−45 to +130
−65 to +150
−0.5 to +6.5
Storage Temperature
°C
Voltage on any Pin with Respect to Ground (Note 1)
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than V + 0.5 V. During transitions, the voltage on any pin may
CC
undershoot to no less than −1.5 V or overshoot to no more than V + 1.5 V, for periods of less than 20 ns.
CC
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol
(Note 3)
Parameter
Min
1,000,000
100
Units
Program / Erase Cycles
Years
N
Endurance
END
T
DR
Data Retention
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, V = 5 V, 25°C
CC
4. The device uses ECC (Error Correction Code) logic with 6 ECC bits to correct one bit error in 4 data bytes. Therefore, when a single byte
has to be written, 4 bytes (including the ECC bits) are re−programmed. It is recommended to write by multiple of 4 bytes in order to benefit
from the maximum number of write cycles.
Table 3. D. C. OPERATING CHARACTERISTICS
(V = 1.8 V to 5.5 V, T = −40°C to +85°C and V = 2.5 V to 5.5 V, T = −40°C to +125°C, unless otherwise specified)
CC
A
CC
A
Symbol
Parameter
Test Conditions
Min
Max
1.2
1.8
3
Units
mA
I
Supply Current
(Read Mode)
Read, SO open /
−40°C to +85°C
V
CC
= 1.8 V, f
= 5 MHz
= 10 MHz
= 10 MHz
CCR
SCK
SCK
SCK
V
= 2.5 V, f
= 5.5 V, f
mA
CC
CC
V
mA
Read, SO open /
−40°C to +125°C
2.5 V < V < 5.5 V,
3
mA
CC
f
= 10 MHz
SCK
I
Supply Current
(Write Mode)
Write, CS = V
/
1.8 V < V < 5.5 V
3
3
mA
mA
mA
CCW
CC
CC
−40°C to +85°C
Write, CS = V
/
2.5 V < V < 5.5 V
CC
CC
−40°C to +125°C
I
Standby Current
Standby Current
V
= GND or V
,
T = −40°C to +85°C
A
1
3
3
5
SB1
IN
CC
CS = V , WP = V
,
CC
CC
HOLD = V
,
CC
T = −40°C to +125°C
A
V
CC
= 5.5 V
I
V
= GND or V
,
T = −40°C to +85°C
A
mA
mA
SB2
IN
CC
CS = V , WP = GND,
CC
HOLD = GND,
T = −40°C to +125°C
A
V
CC
= 5.5 V
I
Input Leakage Current
V
= GND or V
CC
−2
−2
2
2
mA
mA
L
IN
I
Output Leakage
Current
CS = V
CC
LO
V
OUT
= GND or V
CC
V
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
V
V
V
V
≥ 2.5 V
≥ 2.5 V
< 2.5 V
< 2.5 V
−0.5
0.3V
CC
V
V
V
V
V
V
V
V
IL1
CC
CC
CC
CC
V
IH1
0.7V
V
CC
+ 0.5
CC
V
−0.5
0.75V
0.25V
CC
IL2
IH2
V
V
CC
+ 0.5
CC
V
V
≥ 2.5 V, I = 3.0 mA
0.4
OL1
OH1
CC
OL
V
V
CC
≥ 2.5 V, I = −1.6 mA
V
V
− 0.8V
− 0.2V
OH
CC
V
V
CC
< 2.5 V, I = 150 mA
0.2
OL2
OH2
OL
V
V
< 2.5 V, I = −100 mA
CC OH
CC
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2
CAT25M01
Table 4. PIN CAPACITANCE (T = 25°C, f = 1.0 MHz, V = +5.0 V) (Note 5)
A
CC
Symbol
Test
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI, WP, HOLD)
Conditions
= 0 V
Min
Typ
Max
8
Units
pF
C
V
OUT
OUT
C
V
IN
= 0 V
8
pF
IN
5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
Table 5. A.C. CHARACTERISTICS (T = −40°C to +125°C, unless otherwise specified.) (Note 6)
A
V
CC
= 1.8 V − 5.5 V
V
CC
= 2.5 V − 5.5 V
−405C to +855C
−405C to +1255C
Min
DC
20
Max
Min
DC
10
Max
Symbol
Parameter
Units
MHz
ns
f
Clock Frequency
Data Setup Time
Data Hold Time
SCK High Time
SCK Low Time
5
10
SCK
t
SU
t
H
20
10
ns
t
75
40
ns
WH
t
75
40
ns
WL
t
HOLD to Output Low Z
Input Rise Time
Input Fall Time
50
2
25
2
ns
LZ
t
RI
(Note 8)
(Note 8)
ms
t
FI
2
2
ms
t
t
HOLD Setup Time
HOLD Hold Time
0
0
ns
HD
CD
10
10
ns
t
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD to Output High Z
CS High Time
75
40
ns
V
t
0
0
ns
HO
t
50
20
25
ns
DIS
t
HZ
100
ns
t
80
60
60
60
60
10
10
40
30
30
30
30
10
10
ns
CS
t
CS Setup Time
ns
CSS
CSH
CNS
CNH
WPS
WPH
t
t
CS Hold Time
ns
CS Inactive Setup Time
CS Inactive Hold Time
WP Setup Time
t
t
ns
ns
t
WP Hold Time
t
(Note 7)
Write Cycle Time
5
5
ms
WC
6. AC Test Conditions:
Input Pulse Voltages: 0.3 V to 0.7 V
CC
CC
Input rise and fall times: ≤ 10 ns
Input and output reference voltages: 0.5 V
CC
Output load: current source I
/I
; C = 30 pF
OL max OH max L
7. t
is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
WC
Table 6. POWER−UP TIMING (Notes 8 and 9)
Symbol
Parameter
Max
1
Units
ms
t
Power−up to Read Operation
Power−up to Write Operation
PUR
t
1
ms
PUW
8. This parameter is tested initially and after a design or process change that affects the parameter.
9. t and t are the delays required from the time V is stable until the specified operation can be initiated.
PUR
PUW
CC
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3
CAT25M01
Pin Description
Functional Description
The CAT25M01 device supports the Serial Peripheral
Interface (SPI) bus protocol, modes (0,0) and (1,1). The
device contains an 8−bit instruction register. The instruction
set and associated op−codes are listed in Table 7.
Reading data stored in the CAT25M01 is accomplished by
simply providing the READ command and an address.
Writing to the CAT25M01, in addition to a WRITE
command, address and data, also requires enabling the
device for writing by first setting certain bits in a Status
Register, as will be explained later.
SI: The serial data input pin accepts op−codes, addresses
and data. In SPI modes (0,0) and (1,1) input data is latched
on the rising edge of the SCK clock input.
SO: The serial data output pin is used to transfer data out of
the device. In SPI modes (0,0) and (1,1) data is shifted out
on the falling edge of the SCK clock.
SCK: The serial clock input pin accepts the clock provided
by the host and used for synchronizing communication
between host and CAT25M01.
CS: The chip select input pin is used to enable/disable the
CAT25M01. When CS is high, the SO output is tri−stated
(high impedance) and the device is in Standby Mode (unless
an internal write operation is in progress). Every
communication session between host and CAT25M01 must
be preceded by a high to low transition and concluded with
a low to high transition of the CS input.
After a high to low transition on the CS input pin, the
CAT25M01 will accept any one of the six instruction
op−codes listed in Table 7 and will ignore all other possible
8−bit combinations. The communication protocol follows
the timing from Figure 2.
The CAT25M01 features an additional Identification
Page (256 bytes) which can be accessed for Read and Write
operations when the IPL bit from the Status Register is set
to “1”. The user can also choose to make the Identification
Page permanent write protected.
WP: The write protect input pin will allow all write
operations to the device when held high. When WP pin is
tied low and the WPEN bit in the Status Register (refer to
Status Register description, later in this Data Sheet) is set to
“1”, writing to the Status Register is disabled.
Table 7. INSTRUCTION SET
Instruction
WREN
WRDI
Opcode
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Operation
HOLD: The HOLD input pin is used to pause transmission
between host and CAT25M01, without having to retransmit
the entire sequence at a later time. To pause, HOLD must be
taken low and to resume it must be taken back high, with the
SCK input low during both transitions. When not used for
pausing, it is recommended the HOLD input to be tied to
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
RDSR
WRSR
READ
V , either directly or through a resistor.
CC
WRITE
t
CS
CS
t
t
WL
t
WH
CSS
t
t
t
CNS
CNH
CSH
SCK
t
H
t
RI
t
t
SU
FI
VALID
IN
SI
t
V
t
V
t
DIS
t
HO
HI− Z
HI− Z
VALID
OUT
SO
Figure 2. Synchronous Data Timing
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4
CAT25M01
Status Register
The Status Register, as shown in Table 8, contains a
number of status and control bits.
prevents writing to the status register and to the block
protected sections of memory. While hardware write
protection is active, only the non−block protected memory
can be written. Hardware write protection is disabled when
the WP pin is high or the WPEN bit is 0. The WPEN bit, WP
pin and WEL bit combine to either permit or inhibit Write
operations, as detailed in Table 10.
The IPL (Identification Page Latch) bit determines
whether the additional Identification Page (IPL = 1) or main
memory array (IPL = 0) can be accessed both for Read and
Write operations. The IPL bit is set by the user with the
WRSR command and is volatile. The IPL bit is
automatically reset after read/write operations.
The LIP bit is set by the user with the WRSR command
and is non−volatile. When set to 1, the Identification Page is
permanently write protected (locked in Read−only mode).
Note: The IPL and LIP bits cannot be set to 1 using the
same WRSR instruction. If the user attempts to set (“1”)
both the IPL and LIP bit in the same time, these bits cannot
be written and therefore they will remain unchanged.
The RDY (Ready) bit indicates whether the device is busy
with a write operation. This bit is automatically set to 1
during an internal write cycle, and reset to 0 when the device
is ready to accept commands. For the host, this bit is read
only.
The WEL (Write Enable Latch) bit is set/reset by the
WREN/WRDI commands. When set to 1, the device is in a
Write Enable state and when set to 0, the device is in a Write
Disable state.
The BP0 and BP1 (Block Protect) bits determine which
blocks are currently write protected. They are set by the user
with the WRSR command and are non−volatile. The user is
allowed to protect a quarter, one half or the entire memory,
by setting these bits according to Table 9. The protected
blocks then become read−only.
The WPEN (Write Protect Enable) bit acts as an enable for
the WP pin. Hardware write protection is enabled when the
WP pin is low and the WPEN bit is 1. This condition
Table 8. STATUS REGISTER
7
6
5
4
3
2
1
0
WPEN
IPL
0
LIP
BP1
BP0
WEL
RDY
Table 9. BLOCK PROTECTION BITS
Status Register Bits
BP1
BP0
Array Address Protected
None
Protection
0
0
1
1
0
1
0
1
No Protection
18000h−1FFFFh
10000h−1FFFFh
00000h−1FFFFh
Quarter Array Protection
Half Array Protection
Full Array Protection
Table 10. WRITE PROTECT CONDITIONS
WPEN
WP
X
WEL
Protected Blocks
Protected
Unprotected Blocks
Protected
Status Register
Protected
Writable
0
0
1
1
X
X
0
1
0
1
0
1
X
Protected
Writable
Low
Low
High
High
Protected
Protected
Protected
Protected
Protected
Writable
Protected
Writable
Protected
Protected
Protected
Writable
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CAT25M01
Write Enable and Write Disable
Write Operations
The internal Write Enable Latch and the correspon–ding
Status Register WEL bit are set by sending the WREN
instruction to the CAT25M01. Care must be taken to take the
CS input high after the WREN instruction, as otherwise the
Write Enable Latch will not be properly set. WREN timing
is illustrated in Figure 3. The WREN instruction must be
sent prior any WRITE or WRSR instruction.
The CAT25M01 device powers up into a write disable
state. The device contains a Write Enable Latch (WEL)
which must be set before attempting to write to the memory
array or to the status register. In addition, the address of the
memory location(s) to be written must be outside the
protected area, as defined by BP0 and BP1 bits from the
status register.
The internal write enable latch is reset by sending the
WRDI instruction as shown in Figure 4. Disabling write
operations by resetting the WEL bit, will protect the device
against inadvertent writes.
CS
SCK
1
1
0
SI
0
0
0
0
0
HIGH IMPEDANCE
SO
Note: Dashed Line = mode (1, 1)
Figure 3. WREN Timing
CS
SCK
1
0
0
SI
0
0
0
0
0
HIGH IMPEDANCE
SO
Note: Dashed Line = mode (1, 1)
Figure 4. WRDI Timing
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6
CAT25M01
Byte Write
Following completion of the write cycle, the CAT25M01 is
automatically returned to the write disable state.
Once the WEL bit is set, the user may execute a write
sequence, by sending a WRITE instruction, a 24−bit address
and a data byte as shown in Figure 5. Only 17 significant
address bits are used by the CAT25M01. The rest are don’t
care bits, as shown in Table 11. Internal programming will
start after the low to high CS transition. During an internal
write cycle, all commands, except for RDSR (Read Status
Register) will be ignored. The RDY bit will indicate if the
internal write cycle is in progress (RDY high), or the device
is ready to accept commands (RDY low).
Write Identification Page
The additional 256−byte Identification Page (IP) can be
written with user data using the same Write commands
sequence as used for Page Write to the main memory array
(Figure 6). The IPL bit from the Status Register must be set
(IPL = 1) using the WRSR instruction, before attempting
to write to the IP.
The address bits [A23:A8] are Don’t Care and the
[A7:A0] bits define the byte address within the
Identification Page. In addition, the Byte Address must point
to a location outside the protected area defined by the BP1,
BP0 bits from the Status Register. When the full memory
array is write protected (BP1, BP0 = 1,1), the write
instruction to the IP is not accepted and not executed.
Also, the write to the IP is not accepted if the LIP bit from
the Status Register is set to 1 (the page is locked in
Read−only mode).
Page Write
After sending the first data byte to the CAT25M01, the
host may continue sending data, up to a total of 256 bytes,
according to timing shown in Figure 6. After each data byte,
the lower order address bits are automatically incremented,
while the higher order address bits (page address) remain
unchanged. If during this process the end of page is
exceeded, then loading will “roll over” to the first byte in the
page, thus possibly overwriting previoualy loaded data.
Table 11. BYTE ADDRESS
Device
Address Significant Bits
A16 − A0
Address Don’t Care Bits
A23 – A17
# Address Clock Pulses
Main Memory Array
Identification Page
24
24
A7 − A0
A23 – A8
CS
0
1
2
3
4
5
6
7
8
29 30 31 32 33 34 35 36 37 38 39
SCK
SI
OPCODE
BYTE ADDRESS*
DATA IN
A
N
A
0
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
1
0
HIGH IMPEDANCE
SO
* Please check the Byte Address Table (Table 11)
Note: Dashed Line = mode (1, 1)
Figure 5. Byte WRITE Timing
CS
0
1
2
3
4
5
6
7
8
29 30 31 32−39 40−47 32+(N−1)x8−1....32+(N−1)x8
32+Nx8−1
SCK
SI
BYTE ADDRESS*
OPCODE
DATA IN
Data Data
Data Byte N
0
0
0
0
0
0
1
0
A
N
A
0
Byte 1
Byte 2
0
7..1
HIGH IMPEDANCE
SO
* Please check the Byte Address Table (Table 11)
Note: Dashed Line = mode (1, 1)
Figure 6. Page WRITE Timing
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7
CAT25M01
Write Status Register
Write Protection
The Status Register is written by sending a WRSR
instruction according to timing shown in Figure 7. Only bits
2, 3, 4, 6 and 7 can be written using the WRSR command.
The Write Protect (WP) pin can be used to protect the
Block Protect bits BP0 and BP1 against being inadvertently
altered. When WP is low and the WPEN bit is set to “1”,
write operations to the Status Register are inhibited. WP
going low while CS is still low will interrupt a write to the
status register. If the internal write cycle has already been
initiated, WP going low will have no effect on any write
operation to the Status Register. The WP pin function is
blocked when the WPEN bit is set to “0”. The WP input
timing is shown in Figure 8.
CS
0
1
2
3
4
5
6
7
1
8
9
6
10
5
11
4
12
13
2
14
1
15
0
SCK
SI
OPCODE
0
DATA IN
3
0
0
0
0
0
0
7
MSB
HIGH IMPEDANCE
Note: Dashed Line = mode (1, 1)
SO
Figure 7. WRSR Timing
t
t
WPH
WPS
CS
SCK
WP
WP
Note: Dashed Line = mode (1, 1)
Figure 8. WP Timing
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8
CAT25M01
Read Operations
for Read from main memory array (Figure 9). The IPL bit
from the Status Register must be set (IPL = 1) before
attempting to read from the IP. The [A7:A0] are the address
significant bits that point to the data byte shifted out on the
SO pin. If the CS continues to be held low, the internal
address register defined by [A7:A0] bits is automatically
incremented and the next data byte from the IP is shifted out.
The byte address must not exceed the 256−byte page
boundary.
Read from Memory Array
To read from memory, the host sends a READ instruction
followed by a 24−bit address (see Table 11 for the number
of significant address bits).
After receiving the last address bit, the CAT25M01 will
respond by shifting out data on the SO pin (as shown in
Figure 9). Sequentially stored data can be read out by simply
continuing to run the clock. The internal address pointer is
automatically incremented to the next higher address as data
is shifted out. After reaching the highest memory address,
the address counter “rolls over” to the lowest memory
address, and the read cycle can be continued indefinitely.
The read operation is terminated by taking CS high.
Read Status Register
To read the status register, the host simply sends a RDSR
command. After receiving the last bit of the command, the
CAT25M01 will shift out the contents of the status register
on the SO pin (Figure 10). The status register may be read
at any time, including during an internal write cycle.
Read Identification Page
Reading the additional 256−byte Identification Page (IP)
is achieved using the same Read command sequence as used
CS
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38
SCK
OPCODE
BYTE ADDRESS*
A
0
A
N
1
1
SI
0
0
0
0
0
0
DATA OUT
HIGH IMPEDANCE
SO
7
6
5
4
3
2
1
0
MSB
* Please check the Byte Address Table (Table 11).
Note: Dashed Line = mode (1, 1)
Figure 9. READ Timing
CS
0
1
2
3
4
5
6
0
7
1
8
9
10
11
12
13
14
SCK
OPCODE
0
0
0
0
0
1
SI
DATA OUT
HIGH IMPEDANCE
Note: Dashed Line = mode (1, 1)
5
SO
7
6
4
3
2
1
0
MSB
Figure 10. RDSR Timing
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9
CAT25M01
Hold Operation
below the POR trigger level. This bi−directional POR
behavior protects the device against ‘brown−out’ failure
following a temporary loss of power.
The CAT25M01 device powers up in a write disable state
and in a low power standby mode. A WREN instruction
must be issued prior any writes to the device.
After power up, the CS pin must be brought low to enter
a ready state and receive an instruction. After a successful
byte/page write or status register write, the device goes into
a write disable mode. The CS input must be set high after the
proper number of clock cycles to start the internal write
cycle. Access to the memory array during an internal write
cycle is ignored and programming is continued. Any invalid
op−code will be ignored and the serial output pin (SO) will
remain in the high impedance state.
The HOLD input can be used to pause communication
between host and CAT25M01. To pause, HOLD must be
taken low while SCK is low (Figure 11). During the hold
condition the device must remain selected (CS low). During
the pause, the data output pin (SO) is tri−stated (high
impedance) and SI transitions are ignored. To resume
communication, HOLD must be taken high while SCK is
low.
Design Considerations
The CAT25M01 device incorporates Power−On Reset
(POR) circuitry which protects the internal logic against
powering up in the wrong state. The device will power up
into Standby mode after V exceeds the POR trigger level
and will power down into Reset mode when V drops
CC
CC
CS
t
CD
t
CD
SCK
t
HD
t
HD
HOLD
SO
t
HZ
HIGH IMPEDANCE
t
LZ
Note: Dashed Line = mode (1, 1)
Figure 11. HOLD Timing
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10
CAT25M01
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
SYMBOL
MIN
NOM
MAX
1.35
A
A1
b
1.75
0.25
0.51
0.25
0.10
0.33
0.19
c
E1
E
D
E
E1
e
4.80
5.80
3.80
5.00
6.20
4.00
1.27 BSC
h
0.25
0.40
0º
0.50
1.27
8º
L
PIN # 1
IDENTIFICATION
θ
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
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11
CAT25M01
PACKAGE DIMENSIONS
SOIC−8, 208 mils
CASE 751BE−01
ISSUE O
SYMBOL
MIN
NOM
MAX
A
A1
b
2.03
0.25
0.48
0.25
5.33
8.26
5.38
0.05
0.36
0.19
5.13
7.75
5.13
c
E
E1
D
E
E1
e
1.27 BSC
0.51
0.76
L
0º
8º
θ
PIN#1 IDENTIFICATION
TOP VIEW
D
A
q
e
b
L
c
A1
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with EIAJ EDR-7320.
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12
CAT25M01
PACKAGE DIMENSIONS
TSSOP8, 4.4x3
CASE 948AL−01
ISSUE O
b
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
1.20
0.15
1.05
0.30
0.20
3.10
6.50
4.50
0.05
0.80
0.19
0.09
2.90
6.30
4.30
0.90
E
c
E1
D
3.00
6.40
E
E1
e
4.40
0.65 BSC
1.00 REF
0.60
L
L1
0.50
0.75
0º
8º
θ
e
TOP VIEW
D
c
A2
A
q1
A1
L1
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
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13
CAT25M01
ORDERING INFORMATION (Note 10)
Specific Device
Package
Type
Lead
Finish
Marking
Device Order Number
Temperature Range
Shipping (Note 11)
CAT25M01VI−GT3
25M01A
SOIC−8,
I = Industrial (−40°C to +85°C)
E = Extended (−40°C to +125°C)
I = Industrial (−40°C to +85°C)
I = Industrial (−40°C to +85°C)
E = Extended (−40°C to +125°C)
NiPdAu
NiPdAu
Matte−Tin
NiPdAu
NiPdAu
Tape & Reel,
JEDEC
3,000 Units / Reel
CAT25M01VE−GT3
CAT25M01XI−T2
25M01A
25M01A
SM1A
SOIC−8,
JEDEC
Tape & Reel,
3,000 Units / Reel
SOIC−8,
EIAJ
Tape & Reel,
2,000 Units / Reel
CAT25M01YI−GT3
CAT25M01YE−GT3
TSSOP−8
Tape & Reel,
3,000 Units / Reel
SM1A
TSSOP−8
Tape & Reel,
3,000 Units / Reel
10.For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.
11. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
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CAT25M01/D
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