CAT28C16AKA-90T [ONSEMI]
16 kb CMOS Parallel EEPROM; 16 kb的CMOS并行EEPROM
| 型号： | CAT28C16AKA-90T |
| 厂家： | 
ONSEMI |
| 描述： | 16 kb CMOS Parallel EEPROM |
| 文件： | 总10页 (文件大小：127K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT28C16A
16 kb CMOS Parallel
EEPROM
Description
The CAT28C16A is a fast, low power, 5V−only CMOS Parallel
EEPROM organized as 2K x 8−bits. It requires a simple interface for
in−system programming. On−chip address and data latches,
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self−timed write cycle with auto−clear and V power up/down write
CC
protection eliminate additional timing and protection hardware. DATA
Polling signals the start and end of the self−timed write cycle.
Additionally, the CAT28C16A features hardware write protection.
The CAT28C16A is manufactured using ON Semiconductor’s
advanced CMOS floating gate technology. It is designed to endure
100,000 program/erase cycles and has a data retention of 100 years.
The device is available in JEDEC approved 24−pin DIP and SOIC or
32−pin PLCC packages.
SOIC−24
J, K, W, X SUFFIX
CASE 751BK
Features
• Fast Read Access Times: 90 ns, 120 ns, 200 ns
• Low Power CMOS Dissipation:
PDIP−24
L SUFFIX
CASE 646AD
PLCC−32
N, G SUFFIX
CASE 776AK
– Active: 25 mA Max.
– Standby: 100 mA Max.
• Simple Write Operation:
– On−chip Address and Data Latches
– Self−timed Write Cycle with Auto−clear
PIN FUNCTION
Pin Name
Function
Address Inputs
• Fast Write Cycle Time: 10 ms Max
• End of Write Detection: DATA Polling
• Hardware Write Protection
• CMOS and TTL Compatible I/O
• 100,000 Program/Erase Cycles
• 100 Year Data Retention
• Commercial, Industrial and Automotive Temperature Ranges
A −A
0
10
I/O −I/O
Data Inputs/Outputs
Chip Enable
Output Enable
Write Enable
5 V Supply
0
7
CE
OE
WE
V
CC
V
Ground
SS
PIN CONFIGURATION
NC
No Connect
DIP Package (L)
SOIC Package (J, K, W, X)
PLCC Package (N, G)
1
2
3
24
23
22
A
A
V
A
A
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
7
CC
4
3
2
1 32 31 30
29
6
8
5
6
7
8
A
A
A
A
A
A
A
A
A
NC
NC
OE
A
10
CE
I/O
6
5
4
3
2
1
0
8
A
5
9
28
27
26
25
24
23
22
21
9
4
5
6
7
8
21
20
19
18
17
A
4
WE
OE
A
3
A
2
A
10
9
TOP VIEW
A
1
CE
I/O
10
11
12
13
A
0
7
9
16
15
14
13
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
0
6
5
4
3
7
I/O
10
11
12
0
6
1
14 15 16 17 18 19 20
2
V
SS
©
Semiconductor Components Industries, LLC, 2009
1
Publication Order Number:
October, 2009 − Rev. 6
CAT28C16A/D
CAT28C16A
2,048 x 8
EEPROM
ARRAY
ROW
DECODER
ADDR. BUFFER
& LATCHES
A −A
4
10
INADVERTENT
WRITE
PROTECTION
HIGH VOLTAGE
GENERATOR
V
CC
CE
OE
WE
CONTROL
LOGIC
I/O BUFFERS
TIMER
DATA POLLING
I/O −I/O
0
7
ADDR. BUFFER
& LATCHES
A −A
0
3
COLUMN
DECODER
Figure 1. Block Diagram
Table 1. MODE SELECTION
Mode
Read
CE
L
WE
OE
L
I/O
Power
ACTIVE
ACTIVE
H
D
OUT
Byte Write (WE Controlled)
L
H
D
IN
Byte Write (CE Controlled)
L
H
D
IN
ACTIVE
Standby, and Write Inhibit
Read and Write Inhibit
H
X
X
H
X
H
High−Z
High−Z
STANDBY
ACTIVE
Table 2. CAPACITANCE (T = 25°C, f = 1.0 MHz, V = 5 V)
A
CC
Symbol
(Note 1)
Test
Max
10
6
Conditions
Units
pF
C
Input/Output Capacitance
Input Capacitance
V
I/O
= 0 V
= 0 V
I/O
C
(Note 1)
V
IN
pF
IN
1. This parameter is tested initially and after a design or process change that affects the parameter.
Table 3. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
°C
°C
V
Temperature Under Bias
Storage Temperature
–55 to +125
–65 to +150
Voltage on Any Pin with Respect to Ground (Note 2)
with Respect to Ground
–2.0 V to +V + 2.0 V
CC
V
CC
−2.0 to +7.0
1.0
V
Package Power Dissipation Capability (T = 25°C)
W
A
Lead Soldering Temperature (10 secs)
Output Short Circuit Current (Note 3)
300
°C
mA
100
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. The minimum DC input voltage is −0.5 V. During transitions, inputs may undershoot to −2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is V + 0.5 V, which may overshoot to V + 2.0 V for periods of less than 20 ns.
CC
CC
3. Output shorted for no more than one second. No more than one output shorted at a time.
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2
CAT28C16A
Table 4. RELIABILITY CHARACTERISTICS (Note 4)
Symbol Parameter
(Note 5)
Min
100,000
100
Max
Units
Cycles/Byte
Years
N
T
Endurance
END
(Notes 5)
Data Retention
ESD Susceptibility
Latch−Up
DR
V
ZAP
2,000
100
V
I
(Note 6)
mA
LTH
4. This parameter is tested initially and after a design or process change that affects the parameter.
5. For the CAT28C16A−20, the minimum endurance is 10,000 cycles and the minimum data retention is 10 years.
6. Latch−up protection is provided for stresses up to 100 mA on address and data pins from −1 V to V + 1 V.
CC
Table 5. D.C. OPERATING CHARACTERISTICS (V = 5 V 10%, unless otherwise specified.)
CC
Limits
Min
Typ
Max
Symbol
Parameter
Test Conditions
CE = OE = V ,
Units
I
V
V
Current (Operating, TTL)
35
mA
CC
CC
IL
f = 1/t min, All I/O’s Open
RC
I
(Note 7)
Current (Operating, CMOS)
CE = OE = V
,
25
mA
CCC
CC
ILC
f = 1/t min, All I/O’s Open
RC
I
V
V
Current (Standby, TTL)
CE = V , All I/O’s Open
1
mA
mA
mA
mA
SB
CC
IH
I
(Note 8)
Current (Standby, CMOS)
CE = V , All I/O’s Open
100
10
SBC
CC
IHC
I
Input Leakage Current
Output Leakage Current
V
V
= GND to V
CC
−10
−10
LI
IN
I
LO
= GND to V ,
CC
10
OUT
CE = V
IH
V
(Note 8)
(Note 7)
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Write Inhibit Voltage
2
V
CC
+ 0.3
V
V
V
V
V
IH
V
−0.3
2.4
0.8
0.4
IL
V
OH
I
I
= −400 mA
OH
V
OL
= 2.1 mA
OL
V
WI
3.0
7. V
8. V
= −0.3 V to +0.3 V
ILC
IHC
= V − 0.3 V to V + 0.3 V
CC
CC
Table 6. A.C. CHARACTERISTICS, READ CYCLE (V = 5 V 10%, unless otherwise specified.)
CC
28C16A−90
Min Max
28C16A−12
Min Max
28C16A−20
Min Max
Symbol
Parameter
Read Cycle Time
Units
ns
t
90
120
200
RC
t
CE Access Time
90
90
50
120
120
60
200
200
80
ns
CE
t
Address Access Time
OE Access Time
ns
AA
OE
t
ns
t
(Note 9)
(Note 9)
CE Low to Active Output
OE Low to Active Output
CE High to High−Z Output
OE High to High−Z Output
0
0
0
0
0
0
ns
LZ
t
ns
OLZ
t
(Notes 9, 10)
50
50
50
50
55
55
ns
HZ
t
(Notes 9,
10)
ns
OHZ
t
(Note 9)
Output Hold from Address Change
0
0
0
ns
OH
9. This parameter is tested initially and after a design or process change that affects the parameter.
10.Output floating (High−Z) is defined as the state when the external data line is no longer driven by the output buffer.
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3
CAT28C16A
2.4 V
2.0 V
0.8 V
INPUT PULSE LEVELS
REFERENCE POINTS
0.45 V
Figure 2. A.C. Testing Input/Output Waveform (Note 11)
11. Input rise and fall times (10% and 90%) < 10 ns.
1.3V
1N914
3.3K
DEVICE
UNDER
TEST
OUT
C = 100 pF
L
C INCLUDES JIG CAPACITANCE
L
Figure 3. A.C. Testing Load Circuit (example)
Table 7. A.C. CHARACTERISTICS, WRITE CYCLE (V = 5 V 10%, unless otherwise specified.)
CC
28C16A−90
Min Max
28C16A−12
Min Max
28C16A−20
Min Max
10
Symbol
Parameter
Write Cycle Time
Units
ms
ns
t
5
5
WC
t
Address Setup Time
Address Hold Time
CE Setup Time
0
100
0
0
100
0
10
100
0
AS
AH
CS
CH
t
ns
t
ns
t
CE Hold Time
0
0
0
ns
t
(Note 12)
CE Pulse Time
110
0
110
0
150
15
15
150
50
10
50
5
ns
CW
t
OE Setup Time
ns
OES
OEH
t
OE Hold Time
0
0
ns
t
(Note 12)
WE Pulse Width
Data Setup Time
Data Hold Time
110
60
0
110
60
0
ns
WP
t
ns
DS
DH
t
ns
t
DL
Data Latch Time
Write Inhibit Period After Power−up
5
10
5
10
ns
t
(Note 13)
0.05
100
0.05
100
20
ms
INIT
12.A write pulse of less than 20 ns duration will not initiate a write cycle.
13.This parameter is tested initially and after a design or process change that affects the parameter.
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4
CAT28C16A
DEVICE OPERATION
Read
Data stored in the CAT28C16A is transferred to the data bus when WE is held high, and both OE and CE are held low. The
data bus is set to a high impedance state when either CE or OE goes high. This 2−line control architecture can be used to
eliminate bus contention in a system environment.
t
RC
ADDRESS
CE
t
CE
t
OE
OE
t
OLZ
V
IH
WE
t
LZ
t
OHZ
t
AA
t
HZ
t
OH
HIGH−Z
DATA OUT
DATA VALID
DATA VALID
Figure 4. Read Cycle
t
WC
ADDRESS
t
AS
t
AH
t
t
CH
CS
CE
OE
WE
t
t
t
OES
OEH
WP
t
DL
HIGH−Z
DATA OUT
DATA IN
DATA VALID
t
t
DH
DS
Figure 5. Byte Write Cycle [WE Controlled]
Byte Write
edge of WE or CE, whichever occurs last. Data, conversely,
is latched on the rising edge of WE or CE, whichever occurs
first. Once initiated, a byte write cycle automatically erases
the addressed byte and the new data is written within 10 ms.
A write cycle is executed when both CE and WE are low,
and OE is high. Write cycles can be initiated using either WE
or CE, with the address input being latched on the falling
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5
CAT28C16A
DATA Polling
complement of that data on I/O (I/O –I/O are
7
0
6
DATA polling is provided to indicate the completion of a
byte write cycle. Once a byte write cycle is initiated,
attempting to read the last byte written will output the
indeterminate) until the programming cycle is complete.
Upon completion of the self−timed byte write cycle, all I/O’s
will output true data during a read cycle.
t
WC
ADDRESS
t
AS
t
t
DL
AH
t
CW
CE
OE
t
OEH
t
OES
t
CH
t
CS
WE
HIGH−Z
DATA OUT
DATA IN
DATA VALID
t
t
DS
DH
Figure 6. Byte Write Cycle [CE Controlled]
ADDRESS
CE
WE
OE
t
OEH
t
OES
t
OE
t
WC
I/O
7
D
OUT
= X
D
OUT
= X
D
IN
= X
Figure 7. DATA Polling
Hardware Data Protection
The following is a list of hardware data protection features
that are incorporated into the CAT28C16A.
a write sequence, after V has reached 3.0 V
min.
CC
1. V sense provides for write protection when V
3. Write inhibit is activated by holding any one of
OE low, CE high or WE high.
CC
CC
falls below 3.0 V min.
2. A power on delay mechanism, t
(see AC
4. Noise pulses of less than 20 ns on the WE or CE
inputs will not result in a write cycle.
INIT
characteristics), provides a 5 to 20 ms delay before
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6
CAT28C16A
PACKAGE DIMENSIONS
PLCC 32
CASE 776AK−01
ISSUE O
PIN#1 IDENTIFICATION
E1
E
E2
D1
D
A2
A3
TOP VIEW
END VIEW
SYMBOL
MIN
NOM
MAX
b1
A2
A3
b
0.38
2.54
2.80
0.54
0.33
b1
D
0.66
0.82
12.32
11.36
9.56
12.57
11.50
11.32
15.11
14.04
13.86
b
e
D1
D2
E
D2
SIDE VIEW
14.86
13.90
12.10
E1
E2
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-016.
e
1.27 BSC
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7
CAT28C16A
PACKAGE DIMENSIONS
SOIC−24, 300 mils
CASE 751BK−01
ISSUE O
SYMBOL
MIN
NOM
MAX
2.65
0.30
2.55
0.51
0.33
15.40
10.51
7.60
2.35
A
A1
A2
b
0.10
2.05
0.31
0.20
15.20
10.11
7.34
E1
E
c
D
E
E1
e
1.27 BSC
h
0.25
0.40
0º
0.75
1.27
8º
L
b
e
θ
PIN#1 IDENTIFICATION
5º
15º
θ1
TOP VIEW
h
D
h
q1
A2
q
A
q1
L
c
A1
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-013.
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8
CAT28C16A
PACKAGE DIMENSIONS
PDIP−24, 600 mils
CASE 646AD−01
ISSUE A
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
6.35
0.39
3.18
0.36
4.95
0.55
1.77
0.38
32.25
E1
E
b1
c
0.77
0.21
D
31.50
E
E1
e
15.24
12.32
15.87
14.73
D
2.54 BSC
TOP VIEW
15.24
2.93
17.78
5.08
eB
L
A2
A
c
L
A1
b1
e
b
eB
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-011.
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9
CAT28C16A
Example of Ordering Information
Prefix
Device #
Suffix
CAT
28C16A
N
I
− 20
T
Temperature Range
Speed
Tape & Reel (Note 15)
Company ID
(Optional)
Product Number
T: Tape & Reel
28C16A
Blank = Commercial (0°C to +70°C)
I = Industrial (−40°C to +85°C)
A = Automotive (−40°C to +105°C)
−90: 90 ns
−12: 120 ns
−20: 200 ns
Package
N: PLCC
J: SOIC (JEDEC)
K: SOIC (EIAJ)
L: PDIP (Lead Free, Halogen Free)
G: PLCC (Lead Free, Halogen Free)
W: SOIC (JEDEC) (Lead Free, Halogen Free)
X: SOIC (EIAJ) (Lead Free, Halogen Free)
14.The device used in the above example is a CAT28C16ANI−20T (PLCC, Industrial Temperature, 200 ns Access Time, Tape & Reel).
15.For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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CAT28C16A/D
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