CAT28C256HT13I-25TE13 [ONSEMI]
32KX8 EEPROM 5V, 250ns, PDSO28, 8 X 13.40 MM, TSOP-28;
| 型号： | CAT28C256HT13I-25TE13 |
| 厂家： | 
ONSEMI |
| 描述： | 32KX8 EEPROM 5V, 250ns, PDSO28, 8 X 13.40 MM, TSOP-28 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 内存集成电路 |
| 文件： | 总14页 (文件大小：138K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT28C256
256 kb Parallel EEPROM
Description
The CAT28C256 is a fast, low power, 5 V−only CMOS Parallel
EEPROM organized as 32K x 8−bits. It requires a simple interface for
in−system programming. On−chip address and data latches,
self−timed write cycle with auto−clear and V power up/down write
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CC
protection eliminate additional timing and protection hardware. DATA
Polling and Toggle status bits signal the start and end of the self−timed
write cycle. Additionally, the CAT28C256 features hardware and
software write protection.
The CAT28C256 is manufactured using ON Semiconductor’s
advanced CMOS floating gate technology. It is designed to endure
100,000 program/erase cycles and has a data retention of 100 years.
The device is available in JEDEC approved 28−pin DIP, 28−pin TSOP
or 32−pin PLCC packages.
TSOP−28
T13, H13 SUFFIX
CASE 318AE
Features
• Fast Read Access Times: 120/150 ns
• Low Power CMOS Dissipation:
– Active: 25 mA Max.
– Standby: 150 mA Max.
PDIP−28
P, L SUFFIX
CASE 646AE
PLCC−32
N, G SUFFIX
CASE 776AK
• Simple Write Operation:
– On−chip Address and Data Latches
– Self−timed Write Cycle with Auto−clear
• Fast Write Cycle Time:
PIN FUNCTION
− 5 ms Max.
Pin Name
Function
Address Inputs
• CMOS and TTL Compatible I/O
• Hardware and Software Write Protection
• Automatic Page Write Operation:
− 1 to 64 Bytes in 5 ms
− Page Load Timer
A −A
0
14
I/O −I/O
Data Inputs/Outputs
Chip Enable
Output Enable
Write Enable
5 V Supply
0
7
CE
OE
• End of Write Detection:
WE
− Toggle Bit
V
CC
− DATA Polling
V
Ground
SS
• 100,000 Program/Erase Cycles
• 100 Year Data Retention
• Commercial, Industrial and Automotive Temperature Ranges
NC
No Connect
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
©
Semiconductor Components Industries, LLC, 2009
1
Publication Order Number:
December, 2009 − Rev. 6
CAT28C256/D
CAT28C256
PIN CONFIGURATION
DIP Package (P, L)
PLCC Package (N, G)
TSOP Package (8 mm X 13.4 mm) (T13, H13)
OE
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
10
CE
1
2
28
27
26
25
24
23
22
21
20
V
A
A
CC
14
12
A
11
2
A
WE
9
3
I/O
I/O
I/O
I/O
I/O
4 3 2 1 32 31 30
29
7
6
5
4
3
3
4
5
6
7
8
A
A
13
4
A
8
5
6
7
8
7
6
5
4
3
2
1
0
0
1
2
A
A
A
A
A
A
A
A
A
A
8
9
11
NC
6
5
4
3
2
1
0
A
5
13
A
8
28
27
26
A
A
A
A
A
A
A
6
WE
A
11
9
V
7
CC
14
12
A
8
A
GND
9
25
24
23
22
21
OE
9
A
I/O
OE
2
A
10
10
11
12
13
10
11
12
13
14
I/O
A
A
10
1
0
7
6
5
4
3
I/O
A
A
CE
9
CE
I/O
I/O
I/O
I/O
I/O
A
A
A
0
I/O
NC
10 19
11
12 17
13
14 15
7
6
7
A
A
1
2
I/O
I/O
0
18
I/O
I/O
I/O
V
6
5
4
3
14151617181920
16
SS
(Top Views)
32,768 x 8
EEPROM
ARRAY
ROW
DECODER
ADDR. BUFFER
& LATCHES
A −A
6
14
INADVERTENT
WRITE
PROTECTION
HIGH VOLTAGE
GENERATOR
V
CC
64 BYTE PAGE
REGISTER
CE
OE
WE
CONTROL
LOGIC
I/O BUFFERS
DATA POLLING
AND
TIMER
TOGGLE BIT
I/O −I/O
0
7
ADDR. BUFFER
& LATCHES
A −A
0
5
COLUMN
DECODER
Figure 1. Block Diagram
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CAT28C256
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
°C
°C
V
Temperature Under Bias
–55 to +125
–65 to +150
Storage Temperature
Voltage on Any Pin with Respect to Ground (Note 1)
–2.0 V to +V + 2.0 V
CC
V
with Respect to Ground
−2.0 to +7.0
1.0
V
CC
Package Power Dissipation Capability (T = 25°C)
W
A
Lead Soldering Temperature (10 secs)
Output Short Circuit Current (Note 2)
300
°C
mA
100
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The minimum DC input voltage is −0.5 V. During transitions, inputs may undershoot to −2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is V + 0.5 V, which may overshoot to V + 2.0 V for periods of less than 20 ns.
CC
CC
2. Output shorted for no more than one second. No more than one output shorted at a time.
Table 2. RELIABILITY CHARACTERISTICS (Note 3)
Symbol
Parameter
Endurance
Test Method
Min
100,000
100
Max
Units
Cycles/Byte
Years
N
END
MIL−STD−883, Test Method 1033
MIL−STD−883, Test Method 1008
MIL−STD−883, Test Method 3015
JEDEC Standard 17
T
Data Retention
ESD Susceptibility
Latch−Up
DR
V
ZAP
2,000
100
V
I
(Note 4)
mA
LTH
3. These parameters are tested initially and after a design or process change that affects the parameters.
4. Latch−up protection is provided for stresses up to 100 mA on address and data pins from −1 V to V + 1 V.
CC
Table 3. D.C. OPERATING CHARACTERISTICS (V = 5 V 10%, unless otherwise specified.)
CC
Limits
Min
Typ
Max
Symbol
Parameter
Test Conditions
Units
I
V
V
Current (Operating, TTL)
CE = OE = V ,
30
mA
CC
CC
IL
f = 8 MHz, All I/O’s Open
I
(Note 5)
Current (Operating, CMOS)
CE = OE = V
,
25
mA
CCC
CC
ILC
f = 8 MHz, All I/O’s Open
I
V
V
Current (Standby, TTL)
CE = V , All I/O’s Open
1
mA
mA
mA
mA
SB
CC
IH
I
(Note 6)
Current (Standby, CMOS)
CE = V , All I/O’s Open
150
10
SBC
CC
IHC
I
Input Leakage Current
Output Leakage Current
V
V
= GND to V
CC
−10
−10
LI
IN
I
LO
= GND to V ,
CC
10
OUT
CE = V
IH
V
(Note 6)
(Note 5)
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Write Inhibit Voltage
2
V
CC
+ 0.3
V
V
V
V
V
IH
V
−0.3
2.4
0.8
0.4
IL
V
OH
I
I
= −400 mA
OH
V
OL
= 2.1 mA
OL
V
WI
3.5
5. V
6. V
= −0.3 V to +0.3 V.
ILC
IHC
= V −0.3 V to V + 0.3 V.
CC
CC
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CAT28C256
Table 4. MODE SELECTION
Mode
Read
CE
L
WE
OE
L
I/O
Power
ACTIVE
ACTIVE
H
D
OUT
Byte Write (WE Controlled)
L
H
D
IN
Byte Write (CE Controlled)
L
H
D
IN
ACTIVE
Standby and Write Inhibit
Read and Write Inhibit
H
X
X
H
X
H
High−Z
High−Z
STANDBY
ACTIVE
Table 5. CAPACITANCE (T = 25°C, f = 1.0 MHz, V = 5 V)
A
CC
Symbol
(Note 7)
Test
Max
10
6
Conditions
Units
pF
C
Input/Output Capacitance
Input Capacitance
V
I/O
= 0 V
= 0 V
I/O
C
(Note 7)
V
IN
pF
IN
7. This parameter is tested initially and after a design or process change that affects the parameter.
Table 6. A.C. CHARACTERISTICS, READ CYCLE (V = 5 V 10%, unless otherwise specified.)
CC
28C256−12
28C256−15
Min
Max
Min
Max
Symbol
Parameter
Units
t
Read Cycle Time
CE Access Time
Address Access Time
OE Access Time
120
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
t
120
120
50
150
150
70
CE
t
AA
OE
t
t
(Note 8)
(Note 8)
CE Low to Active Output
0
0
0
0
LZ
t
OE Low to Active Output
OLZ
t
(Notes 8, 9)
(Notes 8, 9)
CE High to High−Z Output
OE High to High−Z Output
Output Hold from Address Change
50
50
50
50
HZ
t
OHZ
t
(Note 8)
0
0
OH
8. This parameter is tested initially and after a design or process change that affects the parameter.
9. Output floating (High−Z) is defined as the state when the external data line is no longer driven by the output buffer.
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CAT28C256
Table 7. A.C. CHARACTERISTICS, WRITE CYCLE (V = 5 V 10%, unless otherwise specified.)
CC
28C256−12
28C256−15
Min Max
Min
Max
Symbol
Parameter
Units
ms
ns
t
Write Cycle Time
Address Setup Time
Address Hold Time
CE Setup Time
CE Hold Time
5
5
WC
t
0
50
0
0
50
0
AS
AH
CS
CH
t
ns
t
ns
t
0
0
ns
t
(Note 10)
CE Pulse Time
OE Setup Time
OE Hold Time
100
0
100
0
ns
CW
t
ns
OES
OEH
t
0
0
ns
t
(Note 10)
WE Pulse Width
Data Setup Time
Data Hold Time
100
50
10
5
100
50
10
5
ns
WP
t
ns
DS
DH
t
ns
t
(Note 11)
Write Inhibit Period After Power−up
10
10
ms
ms
INIT
t
(Notes 11, 12)
Byte Load Cycle Time
0.1
100
0.1
100
BLC
10.A write pulse of less than 20 ns duration will not initiate a write cycle.
11. This parameter is tested initially and after a design or process change that affects the parameter.
12.A timer of duration t max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin; however
BLC
a transition from HIGH to LOW within t
max. stops the timer.
BLC
V
CC
− 0.3 V
2.0 V
0.8 V
INPUT PULSE LEVELS
REFERENCE POINTS
0.0 V
Figure 2. A.C. Testing Input/Output Waveform (Note 13)
13.Input rise and fall times (10% and 90%) < 10 ns.
1.3 V
1N914
3.3 K
DEVICE
UNDER
TEST
OUT
C = 100 pF
L
C INCLUDES JIG CAPACITANCE
L
Figure 3. A.C. Testing Load Circuit (example)
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CAT28C256
Byte Write
DEVICE OPERATION
A write cycle is executed when both CE and WE are low,
and OE is high. Write cycles can be initiated using either WE
or CE, with the address input being latched on the falling
edge of WE or CE, whichever occurs last. Data, conversely,
is latched on the rising edge of WE or CE, whichever occurs
first. Once initiated, a byte write cycle automatically erases
the addressed byte and the new data is written within 5 ms.
Read
Data stored in the CAT28C256 is transferred to the data
bus when WE is held high, and both OE and CE are held low.
The data bus is set to a high impedance state when either CE
or OE goes high. This 2−line control architecture can be used
to eliminate bus contention in a system environment.
t
RC
ADDRESS
CE
t
CE
t
OE
OE
t
OLZ
V
IH
WE
t
LZ
t
OHZ
t
AA
t
HZ
t
OH
HIGH−Z
DATA OUT
DATA VALID
DATA VALID
Figure 4. Read Cycle
t
WC
ADDRESS
t
AS
t
AH
t
t
CH
CS
CE
OE
WE
t
t
t
OEH
OES
WP
t
BLC
HIGH−Z
DATA OUT
DATA IN
DATA VALID
t
t
DH
DS
Figure 5. Byte Write Cycle [WE Controlled]
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CAT28C256
Page Write
in any order) during the first and subsequent write cycles.
Each successive byte load cycle must begin within t
of the rising edge of the preceding WE pulse. There is no
page write window limitation as long as WE is pulsed low
The page write mode of the CAT28C256 (essentially an
extended BYTE WRITE mode) allows from 1 to 64 bytes of
data to be programmed within a single EEPROM write
cycle. This effectively reduces the byte−write time by a
factor of 64.
BLCMAX
within t
.
BLC MAX
Upon completion of the page write sequence, WE must
stay high a minimum of t for the internal automatic
Following an initial WRITE operation (WE pulsed low,
BLC MAX
for t , and then high) the page write mode can begin by
program cycle to commence. This programming cycle
consists of an erase cycle, which erases any data that existed
in each addressed cell, and a write cycle, which writes new
data back into the cell. A page write will only write data to
the locations that were addressed and will not rewrite the
entire page.
WP
issuing sequential WE pulses, which load the address and
data bytes into a 64 byte temporary buffer. The page address
where data is to be written, specified by bits A to A , is
latched on the last falling edge of WE. Each byte within the
page is defined by address bits A to A (which can be loaded
6
14
0
5
t
WC
ADDRESS
t
AS
t
t
BLC
AH
t
CW
CE
OE
t
OEH
t
OES
t
CH
t
CS
WE
HIGH−Z
DATA OUT
DATA IN
DATA VALID
t
t
DH
DS
Figure 6. Byte Write Cycle [CE Controlled]
OE
CE
t
t
BLC
WP
WE
ADDRESS
I/O
t
WC
LAST BYTE
BYTE n+2
BYTE n+1
BYTE 0 BYTE 1
BYTE 2
BYTE n
Figure 7. Page Mode Write Cycle
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7
CAT28C256
DATA Polling
Toggle Bit
DATA polling is provided to indicate the completion of
write cycle. Once a byte write or page write cycle is initiated,
attempting to read the last byte written will output the
In addition to the DATA Polling feature of the
CAT28C256, the device offers an additional method for
determining the completion of a write cycle. While a write
cycle is in progress, reading data from the device will result
complement of that data on I/O (I/O –I/O are
7
0
6
indeterminate) until the programming cycle is complete.
Upon completion of the self−timed write cycle, all I/O’s will
output true data during a read cycle.
in I/O toggling between one and zero. However, once the
6
write is complete, I/O stops toggling and valid data can be
6
read from the device.
ADDRESS
CE
WE
t
OEH
t
OES
t
OE
OE
t
WC
I/O
D
OUT
= X
D
OUT
= X
D
IN
= X
7
Figure 8. DATA Polling
WE
CE
OE
t
OEH
t
OES
t
OE
I/O
6
(Note 14)
(Note 14)
t
WC
Figure 9. Toggle Bit
14.Beginning and ending state of I/O is indeterminate.
6
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CAT28C256
Hardware Data Protection
The following is a list of hardware data protection features
that are incorporated into the CAT28C256.
4. Noise pulses of less than 20 ns on the WE or CE
inputs will not result in a write cycle.
Software Data Protection
1. V sense provides for write protection when V
CC
CC
The CAT28C256 features a software controlled data
protection scheme which, once enabled, requires a data
algorithm to be issued to the device before a write can be
performed. The device is shipped from ON Semiconductor
with the software protection NOT ENABLED (the
CAT28C256 is in the standard operating mode).
falls below 3.5 V min.
2. A power on delay mechanism, t
(see AC
INIT
characteristics), provides a 5 to 10 ms delay before
a write sequence, after V has reached 3.5 V
min.
CC
3. Write inhibit is activated by holding any one of
OE low, CE high or WE high.
WRITE DATA:
ADDRESS:
AA
WRITE DATA:
ADDRESS:
AA
5555
5555
WRITE DATA:
ADDRESS:
55
WRITE DATA:
ADDRESS:
55
2AAA
2AAA
WRITE DATA:
ADDRESS:
80
WRITE DATA:
ADDRESS:
A0
5555
5555
WRITE DATA:
ADDRESS:
AA
SOFTWARE DATA
PROTECTION ACTIVATED (Note 15)
5555
WRITE DATA:
ADDRESS:
55
WRITE DATA:
XX
2AAA
TO ANY ADDRESS
20
WRITE DATA:
ADDRESS:
WRITE LAST BYTE
TO
LAST ADDRESS
5555
Figure 10. Write Sequence for Activating
Software Data Protection
Figure 11. Write Sequence for Deactivating
Software Data Protection
15.Write protection is activated at this point whether or not any more writes are completed. Writing to addresses must occur within t
after SDP activation.
Max.,
BLC
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9
CAT28C256
To activate the software data protection, the device must
To allow the user the ability to program the device with an
EEPROM programmer (or for testing purposes) there is a
software command sequence for deactivating the data
protection. The six step algorithm (Figure 11) will reset the
internal protection circuitry, and the device will return to
standard operating mode (Figure 13 provides reset timing).
After the sixth byte of this reset sequence has been issued,
standard byte or page writing can commence.
be sent three write commands to specific addresses with
specific data (Figure 10). This sequence of commands
(along with subsequent writes) must adhere to the page write
timing specifications (Figure 12). Once this is done, all
subsequent byte or page writes to the device must be
preceded by this same set of write commands. The data
protection mechanism is activated until a deactivate
sequence is issued regardless of power on/off transitions.
This gives the user added inadvertent write protection on
power−up in addition to the hardware protection provided.
t
DATA
ADDRESS
AA
5555
55
2AAA
A0
5555
WC
BYTE OR
PAGE
CE
WRITES
ENABLED
t
t
BLC
WP
WE
Figure 12. Software Data Protection Timing
t
DATA
ADDRESS
AA
5555
55
2AAA
80
5555
AA
5555
55
2AAA
20
5555
SDP
RESET
WC
CE
DEVICE
UNPROTECTED
WE
Figure 13. Resetting Software Data Protection Timing
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CAT28C256
PACKAGE DIMENSIONS
PLCC 32
CASE 776AK−01
ISSUE O
PIN#1 IDENTIFICATION
E1
E
E2
D1
D
A2
A3
TOP VIEW
END VIEW
SYMBOL
MIN
NOM
MAX
b1
A2
A3
b
0.38
2.54
2.80
0.54
0.33
b1
D
0.66
0.82
12.32
11.36
9.56
12.57
11.50
11.32
15.11
14.04
13.86
b
e
D1
D2
E
D2
SIDE VIEW
14.86
13.90
12.10
E1
E2
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-016.
e
1.27 BSC
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CAT28C256
PACKAGE DIMENSIONS
TSOP 28, 8x13.4
CASE 318AE−01
ISSUE O
D1
A
PIN 1
b
E1
e
A1
A2
D
TOP VIEW
END VIEW
MIN
q1
L2
c
SYMBOL
NOM
MAX
A
A1
A2
b
1.00
0.05
0.90
0.17
0.10
13.20
11.70
7.90
1.10
1.20
0.15
1.05
0.27
0.20
13.60
11.90
8.10
q
L
L1
1.00
0.22
SIDE VIEW
c
0.15
D
13.40
11.80
8.00
D1
E
e
0.55 BSC
0.50
L
0.30
0.70
L1
L2
θ
0.675
0.25 BSC
3°
Notes:
0°
5°
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-183.
θ1
ꢀ10°
12°
16°
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CAT28C256
PACKAGE DIMENSIONS
PDIP−28, 600 mils
CASE 646AE−01
ISSUE A
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
6.35
0.39
3.18
0.36
4.95
0.55
1.77
0.38
39.70
E1
E
b1
c
0.77
0.21
D
35.10
E
E1
e
15.24
12.32
15.87
14.73
D
2.54 BSC
TOP VIEW
15.24
2.93
17.78
5.08
eB
L
A2
A1
A
c
L
e
b1
b
eB
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-011.
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CAT28C256
Example of Ordering Information (Note 16)
Prefix
Device #
Suffix
CAT
28C256
N
I
− 15
T
Temperature Range
Tape & Reel (Note 20)
Company ID
(Optional)
Product Number
T: Tape & Reel
28C256
Blank = Commercial (0°C to +70°C)
I = Industrial (−40°C to +85°C)
A = Automotive (−40°C to +105°C) (Note 18)
Package
Speed
P: PDIP (Note 17)
N: PLCC (Note 17)
T13: TSOP (8 mm x 13.4 mm) (Note 17)
12: 120 ns
15: 150 ns
L: PDIP (Lead Free, Halogen Free)
G: PLCC (Lead Free, Halogen Free)
H13: TSOP (8 mm x 13.4 mm) (Lead Free, Halogen Free) (Note 19)
16.The device used in the above example is a CAT28C256NI−15T (PLCC, Industrial Temperature, 150 ns Access Time, Tape & Reel).
17.Solder−plate (tin−lead) packages, contact Factory for availability.
18.−40°C to +125°C is available upon request.
19.For the TSOP package (H13), the orderable part number does not contain a hyphen, example: CAT28C256H13I15T.
20.For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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