CAT28LV65KI-20T [ONSEMI]
8KX8 EEPROM 3V, 200ns, PDSO28, EIAJ, SOIC-28;
| 型号： | CAT28LV65KI-20T |
| 厂家： | 
ONSEMI |
| 描述： | 8KX8 EEPROM 3V, 200ns, PDSO28, EIAJ, SOIC-28 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 内存集成电路 |
| 文件： | 总15页 (文件大小：148K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT28LV65
64 kb CMOS Parallel
EEPROM
Description
The CAT28LV65 is a low voltage, low power, CMOS Parallel
EEPROM organized as 8K x 8−bits. It requires a simple interface for
in−system programming. On−chip address and data latches,
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self−timed write cycle with auto−clear and V power up/down write
CC
protection eliminate additional timing and protection hardware. DATA
Polling, RDY/BUSY and Toggle status bit signal the start and end of
the self−timed write cycle. Additionally, the CAT28LV65 features
hardware and software write protection.
The CAT28LV65 is manufactured using ON Semiconductor’s
advanced CMOS floating gate technology. It is designed to endure
100,000 program/erase cycles and has a data retention of 100 years.
The device is available in JEDEC approved 28−pin DIP, 28−pin TSOP,
28−pin SOIC or 32−pin PLCC packages.
PDIP−28
P, L SUFFIX
CASE 646AE
SOIC−28
J, K, W, X SUFFIX
CASE 751BM
Features
• 3.0 V to 3.6 V Supply
• Read Access Times:
– 150/200/250 ns
PLCC−32
N, G SUFFIX
CASE 776AK
TSOP−28
H13 SUFFIX
CASE 318AE
• Low Power CMOS Dissipation:
– Active: 8 mA Max.
– Standby: 100 mA Max.
• Simple Write Operation:
– On−chip Address and Data Latches
– Self−timed Write Cycle with Auto−clear
• Fast Write Cycle Time:
– 5 ms Max.
PIN FUNCTION
Pin Name
Function
Address Inputs
A −A
0
12
• Commercial, Industrial and Automotive Temperature Ranges
• CMOS and TTL Compatible I/O
• Automatic Page Write Operation:
– 1 to 32 bytes in 5 ms
– Page Load Timer
I/O −I/O
Data Inputs/Outputs
Chip Enable
0
7
CE
OE
Output Enable
RDY/BSY
WE
Ready/BUSY Status
Write Enable
• End of Write Detection:
V
CC
3.0 V to 3.6 V Supply
Ground
– Toggle Bit
– DATA Polling
V
SS
– RDY/BUSY
NC
No Connect
• Hardware and Software Write Protection
• 100,000 Program/Erase Cycles
• 100 Year Data Retention
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 15 of this data sheet.
©
Semiconductor Components Industries, LLC, 2009
1
Publication Order Number:
October, 2009 − Rev. 7
CAT28LV65/D
CAT28LV65
PIN CONFIGURATIONS
DIP Package (P, L)
SOIC Package (J, K, W, X)
28
1
28
1
RDY/BUSY
V
CC
RDY/BUSY
V
CC
27
26
25
24
27
2
26
3
2
3
A
WE
NC
A
WE
NC
12
12
A
A
7
7
25
A
A
8
A
4
5
6
7
8
A
8
4
6
6
24
5
A
A
9
A
A
A
A
9
5
5
4
3
23
22
21
20
19
A
A
A
11
A
11
6
7
8
23
22
21
20
19
4
OE
OE
3
A
A
10
A
A
A
A
10
2
2
1
0
0
1
2
9
A
A
CE
I/O
CE
I/O
1
9
10
11
12
0
7
7
10
11
12
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
V
18
17
16
15
I/O
I/O
I/O
I/O
0
6
5
4
3
6
5
4
3
18
17
16
15
I/O
1
13
14
I/O
V
2
13
14
SS
SS
PLCC Package (N, G)
TSOP Package (8 mm x 13.4 mm) (H13)
OE
A
10
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
CE
2
4
3
2
1 32 31 30
29
11
9
8
A
3
I/O
A
A
A
A
A
A
A
A
A
A
5
6
7
8
7
6
5
4
3
2
1
0
8
A
4
I/O
I/O
I/O
I/O
6
5
4
3
28
27
26
25
24
23
22
21
9
NC
5
11
WE
6
V
CC
NC
7
8
OE RDY/BUSY
GND
9
9
A
12
I/O
2
A
10
10
11
12
13
10
11
12
13
14
A
A
A
A
A
I/O
I/O
7
6
5
4
3
1
CE
I/O
I/O
0
A
A
A
NC
I/O
0
1
2
7
0
6
14 15 16 17 18 19 20
(Top Views)
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CAT28LV65
8,192 x 8
E PROM
ARRAY
ROW
DECODER
ADDR. BUFFER
& LATCHES
A −A
2
5
12
INADVERTENT
WRITE
PROTECTION
HIGH VOLTAGE
GENERATOR
32 BYTE PAGE
REGISTER
V
CC
CE
OE
WE
CONTROL
LOGIC
I/O BUFFERS
DATA POLLING
RDY/BUSY &
TOGGLE BIT
TIMER
I/O −I/O
0
7
ADDR. BUFFER
& LATCHES
A −A
0
4
COLUMN
DECODER
RDY/BUSY
Figure 1. Block Diagram
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
°C
°C
V
Temperature Under Bias
–55 to +125
–65 to +150
Storage Temperature
Voltage on Any Pin with Respect to Ground (Note 1)
–2.0 V to +V + 2.0 V
CC
V
with Respect to Ground
−2.0 to +7.0
1.0
V
CC
Package Power Dissipation Capability (T = 25°C)
W
A
Lead Soldering Temperature (10 secs)
Output Short Circuit Current (Note 2)
300
°C
mA
100
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The minimum DC input voltage is −0.5 V. During transitions, inputs may undershoot to −2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is V + 0.5 V, which may overshoot to V + 2.0 V for periods of less than 20 ns.
CC
CC
2. Output shorted for no more than one second. No more than one output shorted at a time.
Table 2. RELIABILITY CHARACTERISTICS (Note 3)
Symbol
Parameter
Endurance
Test Method
Min
Max
Units
Cycles/Byte
Years
5
N
END
MIL−STD−883, Test Method 1033
MIL−STD−883, Test Method 1008
MIL−STD−883, Test Method 3015
JEDEC Standard 17
10
T
Data Retention
ESD Susceptibility
Latch−Up
100
2,000
100
DR
V
ZAP
V
I
(Note 4)
mA
LTH
3. These parameters are tested initially and after a design or process change that affects the parameters.
4. Latch−up protection is provided for stresses up to 100 mA on address and data pins from −1 V to V + 1 V.
CC
Table 3. MODE SELECTION
Mode
CE
L
WE
OE
L
I/O
Power
ACTIVE
ACTIVE
Read
H
D
OUT
Byte Write (WE Controlled)
Byte Write (CE Controlled)
L
H
D
IN
L
H
D
IN
ACTIVE
Standby and Write Inhibit
Read and Write Inhibit
H
X
X
H
X
H
High−Z
High−Z
STANDBY
ACTIVE
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3
CAT28LV65
Table 4. CAPACITANCE (T = 25°C, f = 1.0 MHz)
A
Symbol
(Note 5)
Test
Max
10
6
Conditions
Units
pF
C
C
Input/Output Capacitance
Input Capacitance
V
I/O
= 0 V
= 0 V
I/O
(Note 5)
V
IN
pF
IN
5. This parameter is tested initially and after a design or process change that affects the parameter.
Table 5. D.C. OPERATING CHARACTERISTICS (V = 3.0 V to 3.6 V, unless otherwise specified.)
CC
Limits
Typ
Min
Max
Symbol
Parameter
Test Conditions
CE = OE = V ,
Units
I
V
V
Current (Operating, TTL)
8
mA
CC
CC
IL
f = 1/t min, All I/O’s Open
RC
I
(Note 6)
Current (Standby, CMOS)
CE = V , All I/O’s Open
100
1
mA
mA
mA
SBC
CC
IHC
I
LI
Input Leakage Current
Output Leakage Current
V
V
= GND to V
CC
−1
−5
IN
I
LO
= GND to V ,
CC
5
OUT
CE = V
IH
V
IH
(Note 6)
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Write Inhibit Voltage
2
−0.3
2
V
CC
+ 0.3
V
V
V
V
V
V
IL
0.6
0.3
V
OH
I
I
= −100 mA
OH
V
OL
= 1.0 mA
OL
V
WI
2
6. V
= V − 0.3 V to V + 0.3 V.
CC CC
IHC
Table 6. A.C. CHARACTERISTICS, READ CYCLE (V = 3.0 V to 3.6 V, unless otherwise specified.)
CC
28LV65−15
28LV65−20
28LV65−25
Min
Max
Min
Max
Min
Max
Symbol
Parameter
Units
ns
t
Read Cycle Time
150
200
250
RC
t
CE Access Time
150
150
70
200
200
80
250
250
100
ns
CE
t
Address Access Time
OE Access Time
ns
AA
OE
t
ns
t
(Note 7)
(Note 7)
CE Low to Active Output
OE Low to Active Output
CE High to High−Z Output
OE High to High−Z Output
0
0
0
0
0
0
ns
LZ
t
ns
OLZ
t
(Notes 7, 8)
(Notes 7, 8)
50
50
50
50
55
55
ns
HZ
t
ns
OHZ
t
(Note 7)
Output Hold from Address
Change
0
0
0
ns
OH
7. This parameter is tested initially and after a design or process change that affects the parameter.
8. Output floating (High−Z) is defined as the state when the external data line is no longer driven by the output buffer.
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CAT28LV65
V
CC
− 0.3 V
2.0 V
0.6 V
INPUT PULSE LEVELS
REFERENCE POINTS
0.0 V
Figure 2. A.C. Testing Input/Output Waveform (Note 9)
9. Input rise and fall times (10% and 90%) < 10 ns.
V
CC
1.8 K
DEVICE
UNDER
TEST
OUTPUT
1. 3 K
C = 100 pF
L
C INCLUDES JIG CAPACITANCE
L
Figure 3. A.C. Testing Load Circuit (example)
Table 7. A.C. CHARACTERISTICS, WRITE CYCLE (V = 3.0 V to 3.6 V, unless otherwise specified.)
CC
28LV65−15
Min Max
28LV65−20
Min Max
28LV65−25
Min Max
Symbol
Parameter
Write Cycle Time
Units
ms
ns
t
5
5
5
WC
t
Address Setup Time
Address Hold Time
CE Setup Time
0
100
0
0
100
0
0
100
0
AS
AH
CS
CH
t
ns
t
ns
t
CE Hold Time
0
0
0
ns
t
(Note 10)
CE Pulse Time
110
0
150
10
10
150
100
0
150
10
10
150
100
0
ns
CW
t
OE Setup Time
ns
OES
OEH
t
OE Hold Time
0
ns
t
(Note 10)
WE Pulse Width
110
60
0
ns
WP
t
Data Setup Time
ns
DS
DH
t
Data Hold Time
ns
t
(Note 11)
Write Inhibit Period After Power−up
Byte Load Cycle Time
WE Low to RDY/BUSY Low
5
10
5
10
5
10
ms
ms
INIT
t
(Notes 11, 12)
0.05
100
220
0.1
100
220
0.1
100
220
BLC
t
ns
RB
10.A write pulse of less than 20 ns duration will not initiate a write cycle.
11. This parameter is tested initially and after a design or process change that affects the parameter.
12.A timer of duration t max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin; however
BLC
a transition from HIGH to LOW within t
max. stops the timer.
BLC
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5
CAT28LV65
Byte Write
DEVICE OPERATION
A write cycle is executed when both CE and WE are low,
and OE is high. Write cycles can be initiated using either WE
or CE, with the address input being latched on the falling
edge of WE or CE, whichever occurs last. Data, conversely,
is latched on the rising edge of WE or CE, whichever occurs
first. Once initiated, a byte write cycle automatically erases
the addressed byte and the new data is written within 5 ms.
Read
Data stored in the CAT28LV65 is transferred to the data
bus when WE is held high, and both OE and CE are held low.
The data bus is set to a high impedance state when either CE
or OE goes high. This 2−line control architecture can be used
to eliminate bus contention in a system environment.
t
RC
ADDRESS
CE
t
CE
t
OE
OE
t
OLZ
V
IH
WE
t
LZ
t
OHZ
t
AA
t
HZ
t
OH
HIGH−Z
DATA OUT
DATA VALID
DATA VALID
Figure 4. Read Cycle
t
WC
ADDRESS
t
AS
t
AH
t
t
CH
CS
CE
OE
WE
t
t
t
OES
OEH
WP
t
t
BLC
RB
HIGH−Z
HIGH−Z
RDY/BUSY
DATA OUT
HIGH−Z
DATA IN
DATA VALID
t
t
DH
DS
Figure 5. Byte Write Cycle [WE Controlled]
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CAT28LV65
Page Write
in any order) during the first and subsequent write cycles.
Each successive byte load cycle must begin within t
of the rising edge of the preceding WE pulse. There is no
page write window limitation as long as WE is pulsed low
The page write mode of the CAT28LV65 (essentially an
extended BYTE WRITE mode) allows from 1 to 32 bytes of
data to be programmed within a single EEPROM write
cycle. This effectively reduces the byte−write time by a
factor of 32.
BLCMAX
within t
.
BLC MAX
Upon completion of the page write sequence, WE must
stay high a minimum of t for the internal automatic
Following an initial WRITE operation (WE pulsed low,
BLC MAX
for t , and then high) the page write mode can begin by
program cycle to commence. This programming cycle
consists of an erase cycle, which erases any data that existed
in each addressed cell, and a write cycle, which writes new
data back into the cell. A page write will only write data to
the locations that were addressed and will not rewrite the
entire page.
WP
issuing sequential WE pulses, which load the address and
data bytes into a 32 byte temporary buffer. The page address
where data is to be written, specified by bits A to A , is
latched on the last falling edge of WE. Each byte within the
page is defined by address bits A to A (which can be loaded
5
12
0
4
t
WC
ADDRESS
t
AS
t
t
BLC
AH
t
CW
CE
OE
WE
t
OEH
t
OES
t
CH
t
CS
t
RB
HIGH−Z
HIGH−Z
RDY/BUSY
DATA OUT
HIGH−Z
DATA VALID
DATA IN
t
t
DS
DH
Figure 6. Byte Write Cycle [CE Controlled]
OE
CE
t
t
BLC
WP
WE
ADDRESS
I/O
t
WC
LAST BYTE
BYTE n+2
BYTE 0
BYTE 1
BYTE 2
BYTE n
BYTE n+1
Figure 7. Page Mode Write Cycle
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CAT28LV65
DATA Polling
write cycle. While a write cycle is in progress, reading data
from the device will result in I/O toggling between one and
DATA polling is provided to indicate the completion of
write cycle. Once a byte write or page write cycle is initiated,
attempting to read the last byte written will output the
6
zero. However, once the write is complete, I/O stops
6
toggling and valid data can be read from the device.
complement of that data on I/O (I/O –I/O are
7
0
6
Ready/BUSY (RDY/BUSY)
indeterminate) until the programming cycle is complete.
Upon completion of the self−timed write cycle, all I/O’s will
output true data during a read cycle.
The RDY/BUSY pin is an open drain output which
indicates device status during programming. It is pulled low
during the write cycle and released at the end of
programming. Several devices may be OR−tied to the same
RDY/BUSY line.
Toggle Bit
In addition to the DATA Polling feature, the device offers
an additional method for determining the completion of a
ADDRESS
CE
WE
t
OEH
t
OES
t
OE
OE
t
WC
I/O
D
OUT
= X
D
OUT
= X
D
IN
= X
7
Figure 8. DATA Polling
WE
CE
OE
t
OEH
t
OES
t
OE
I/O
6
(Note 13)
(Note 13)
t
WC
Figure 9. Toggle Bit
13.Beginning and ending state of I/O is indeterminate.
6
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CAT28LV65
Hardware Data Protection
4. Noise pulses of less than 20 ns on the WE or CE
inputs will not result in a write cycle.
The following is a list of hardware data protection features
that are incorporated into the CAT28LV65.
Software Data Protection
1. V sense provides for write protection when V
CC
CC
The CAT28LV65 features a software controlled data
protection scheme which, once enabled, requires a data
algorithm to be issued to the device before a write can be
performed. The device is shipped from ON Semiconductor
with the software protection NOT ENABLED (the
CAT28LV65 is in the standard operating mode).
falls below 2.0 V min.
2. A power on delay mechanism, t
(see AC
INIT
characteristics), provides a 5 to 10 ms delay before
a write sequence, after V has reached 2.40 V
min.
CC
3. Write inhibit is activated by holding any one of
OE low, CE high or WE high.
WRITE DATA:
ADDRESS:
AA
WRITE DATA:
ADDRESS:
AA
1555
1555
WRITE DATA:
ADDRESS:
55
WRITE DATA:
ADDRESS:
55
0AAA
0AAA
WRITE DATA:
ADDRESS:
A0
WRITE DATA:
ADDRESS:
80
1555
1555
WRITE DATA:
ADDRESS:
AA
SOFTWARE DATA
PROTECTION ACTIVATED (Note 14)
1555
WRITE DATA:
XX
WRITE DATA:
ADDRESS:
55
TO ANY ADDRESS
0AAA
WRITE LAST BYTE
TO
LAST ADDRESS
WRITE DATA:
ADDRESS:
20
1555
Figure 10. Write Sequence for Activating Software
Data Protection
Figure 11. Write Sequence for Deactivating
Software Data Protection
14.Write protection is activated at this point whether or not any more writes are completed. Writing to addresses must occur within t
after SDP activation.
Max.,
BLC
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CAT28LV65
Software Data Protection
This gives the user added inadvertent write protection on
power−up in addition to the hardware protection provided.
To allow the user the ability to program the device with an
EEPROM programmer (or for testing purposes) there is a
software command sequence for deactivating the data
protection. The six step algorithm (Figure 11) will reset the
internal protection circuitry, and the device will return to
standard operating mode (Figure 13 provides reset timing).
After the sixth byte of this reset sequence has been issued,
standard byte or page writing can commence.
To activate the software data protection, the device must
be sent three write commands to specific addresses with
specific data (Figure 10). This sequence of commands
(along with subsequent writes) must adhere to the page write
timing specifications (Figure 12). Once this is done, all
subsequent byte or page writes to the device must be
preceded by this same set of write commands. The data
protection mechanism is activated until a deactivate
sequence is issued regardless of power on/off transitions.
t
DATA
ADDRESS
AA
1555
55
0AAA
A0
1555
WC
BYTE OR
PAGE
CE
WRITES
t
t
BLC
WP
ENABLED
WE
Figure 12. Software Data Protection Timing
AA
1555
55
0AAA
80
1555
AA
1555
55
0AAA
20
1555
t
DATA
ADDRESS
SDP
RESET
WC
CE
DEVICE
UNPROTECTED
WE
Figure 13. Resetting Software Data Protection Timing
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CAT28LV65
PACKAGE DIMENSIONS
PLCC 32
CASE 776AK−01
ISSUE O
PIN#1 IDENTIFICATION
E1
E
E2
D1
D
A2
A3
TOP VIEW
END VIEW
SYMBOL
MIN
NOM
MAX
b1
A2
A3
b
0.38
2.54
2.80
0.54
0.33
b1
D
0.66
0.82
12.32
11.36
9.56
12.57
11.50
11.32
15.11
14.04
13.86
b
e
D1
D2
E
D2
SIDE VIEW
14.86
13.90
12.10
E1
E2
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-016.
e
1.27 BSC
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CAT28LV65
PACKAGE DIMENSIONS
SOIC−28, 300 mils
CASE 751BM−01
ISSUE O
SYMBOL
MIN
NOM
MAX
2.65
0.30
2.55
0.51
0.33
18.03
10.51
7.60
2.35
A
A1
A2
b
0.10
2.05
0.31
0.20
17.78
10.11
7.34
E
c
D
E
E1
e
1.27 BSC
h
0.25
0.40
0º
0.75
1.27
8º
b
e
L
θ
PIN #1
IDENTIFICATION
5º
15º
θ1
TOP VIEW
h
D
h
q1
A2
A
q
q1
L
c
A1
E1
END VIEW
SIDE VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-013.
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CAT28LV65
PACKAGE DIMENSIONS
PDIP−28, 600 mils
CASE 646AE−01
ISSUE A
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
6.35
0.39
3.18
0.36
4.95
0.55
1.77
0.38
39.70
E1
E
b1
c
0.77
0.21
D
35.10
E
E1
e
15.24
12.32
15.87
14.73
D
2.54 BSC
TOP VIEW
15.24
2.93
17.78
5.08
eB
L
A2
A1
A
c
L
e
b1
b
eB
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-011.
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CAT28LV65
PACKAGE DIMENSIONS
TSOP 28, 8x13.4
CASE 318AE−01
ISSUE O
D1
A
PIN 1
b
E1
e
A1
A2
D
TOP VIEW
END VIEW
MIN
q1
L2
c
SYMBOL
NOM
MAX
A
A1
A2
b
1.00
0.05
0.90
0.17
0.10
13.20
11.70
7.90
1.10
1.20
0.15
1.05
0.27
0.20
13.60
11.90
8.10
q
L
L1
1.00
0.22
SIDE VIEW
c
0.15
D
13.40
11.80
8.00
D1
E
e
0.55 BSC
0.50
L
0.30
0.70
L1
L2
θ
0.675
0.25 BSC
3°
Notes:
0°
5°
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-183.
θ1
ꢀ10°
12°
16°
http://onsemi.com
14
CAT28LV65
Example of Ordering Information (Note 15)
Prefix
Device #
Suffix
CAT
28LV65
N
I
− 25
T
Tape & Reel (Note 18)
Temperature Range
Company ID
(Optional)
Product Number
T: Tape & Reel
28LV65
Blank = Commercial (0°C to +70°C)
I = Industrial (−40°C to +85°C)
A = Automotive (−40°C to +105°C) (Note 17)
Package
Speed
P: PDIP (Note 16)
15: 150 ns
20: 200 ns
25: 250 ns
J: SOIC (JEDEC) (Note 16)
K: SOIC (EIAJ) (Note 16)
N: PLCC (Note 16)
L: PDIP (Lead Free, Halogen Free)
W: SOIC (JEDEC) (Lead Free, Halogen Free)
X: SOIC (EIAJ) (Lead Free, Halogen Free)
G: PLCC (Lead Free, Halogen Free)
H13: TSOP (8 mm x 13.4 mm) (Lead Free, Halogen Free)
15.The device used in the above example is a CAT28LV65NI−25T (PLCC, Industrial temperature, 250 ns Access Time, Tape & Reel).
16.Solder−plate (tin−lead) packages, contact Factory for availability.
17.−40°C to +125°C is available upon request.
18.For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
ORDERING INFORMATION
Orderable Part Numbers (for Pb−Free Devices)
CAT28LV65GI−15T
CAT28LV65GI−20T
CAT28LV65GI−25T
CAT28LV65GA−15T
CAT28LV65GA−20T
CAT28LV65GA−25T
CAT28LV65H13I15T
CAT28LV65H13I20T
CAT28LV65H13I25T
CAT28LV65H13A15T
CAT28LV65H13A20T
CAT28LV65H13A25T
CAT28LV65LI15
CAT28LV65WI−15T
CAT28LV65WI−20T
CAT28LV65WI−25T
CAT28LV65WA−15T
CAT28LV65WA−20T
CAT28LV65WA−25T
CAT28LV65XI−15T
CAT28LV65XI−20T
CAT28LV65XI−25T
CAT28LV65XA−15T
CAT28LV65XA−20T
CAT28LV65XA−25T
CAT28LV65LI20
CAT28LV65LI25
CAT28LV65LA15
CAT28LV65LA20
CAT28LV65LA25
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
CAT28LV65/D
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