CAT4103V-T2 [ONSEMI]
LED DISPLAY DRIVER, PDSO16, ROHS COMPLIANT, MO-012, SOIC-16;
| 型号： | CAT4103V-T2 |
| 厂家： | 
ONSEMI |
| 描述： | LED DISPLAY DRIVER, PDSO16, ROHS COMPLIANT, MO-012, SOIC-16 驱动 光电二极管 接口集成电路 |
| 文件： | 总13页 (文件大小：147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT4103
3-Channel Constant-Current
RGB LED Driver
Description
The CAT4103 is a 3−channel, linear based constant−current LED
driver designed for RGB LED control, requiring no inductor and
provides a low noise operation. LED channel currents up to 175 mA
are programmed independently via separate external resistors. Low
output voltage operation of 0.4 V at 175 mA allows for more power
efficient designs across wider supply voltage range. The three LED
pins are compatible with high voltage up to 25 V supporting
applications with long strings of LEDs.
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A high−speed 4−wire 25 MHz serial interface controls each
individual channel using a shift register and latch configuration.
Output data pins allow multiple devices to be cascaded and
programmed via one serial interface with no need for external drivers
or timing considerations. The device also includes a blanking control
pin (BIN) that can be used to disable all channels independently of the
interface.
Thermal shutdown protection is incorporated in the device to
disable the LED outputs whenever the die temperature exceeds 150°C.
The device is available in a 16−lead SOIC package.
SOIC−16
V SUFFIX
CASE 751BG
PIN CONNECTIONS
1
VDD
GND
BIN
BOUT
LOUT
SOUT
COUT
LED1
LED2
LED3
LIN
SIN
Features
CIN
• 3 Independent Current Sinks Rated to 25 V
• LED Current to 175 mA per Channel Set by Separate External
Resistors
RSET3
RSET2
RSET1
• High−speed 25 MHz 4−wire Serial Interface
(Top View)
• Buffered Output Drivers to Ensure Data Integrity
• Cascadable Devices
MARKING DIAGRAM
• Low Dropout Current Source (0.4 V at 175 mA)
• 3 V to 5.5 V Logic Supply
L4A
CAT4103VB
YMXXXX
• Thermal Shutdown Protection
• 16−lead SOIC Package
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
L = Assembly Location
4 = Lead Finish − NiPdAu
Applications
A = Product Revision (Fixed as “A”)
CAT4103V = Device Code
B = Leave Blank
Y = Production Year (Last Digit)
M = Production Month (1−9, A, B, C)
XXXX = Last Four Digits of Assembly Lot Number
• Multi−color, Intelligent LED, Architectural Lighting
• High−visual Impact LED Signs and Displays
• LCD Backlight
ORDERING INFORMATION
Device
Package
Shipping
CAT4103V−GT2
(Note 1)
SOIC−16
(Pb−Free)
2,000/
Tape & Reel
1. Lead Finish NiPdAu
© Semiconductor Components Industries, LLC, 2010
1
Publication Order Number:
March, 2010 − Rev. 1
CAT4103/D
CAT4103
VIN
5 V to 25 V
VDD
3 V to 5.5 V
C1
1 mF
RED
GREEN
LED2
BLUE
LED3
VDD
LED1
BIN
LIN
SIN
CIN
BOUT
LOUT
SOUT
COUT
NEXT
CAT4103
DEVICE
CONTROLLER
CAT4103
GND RSET1
R1
RSET2
R2
RSET3
R3
Figure 1. Typical Application Circuit
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Units
V
VDD Voltage
6
Input Voltage Range (SIN, BIN, CIN, LIN)
Output voltage range (SOUT, BOUT, COUT, LOUT)
LED1, LED2, LED3 Voltage
−0.3 V to VDD+0.3 V
V
−0.3 V to VDD+0.3 V
V
25
200
V
DC Output Current on LED1 to LED3
Storage Temperature Range
mA
_C
_C
_C
V
−55 to +160
−40 to +150
300
Junction Temperature Range
Lead Soldering Temperature (10 sec.)
ESD Rating: All Pins
Human Body Model
Machine Model
2000
200
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 2. RECOMMENDED OPERATING CONDITIONS
Parameter
Range
3.0 to 5.5
Units
V
VDD
Voltage applied to LED1 to LED3, outputs off
Voltage applied to LED1 to LED3, outputs on
Output Current on LED1 to LED3
up to 25
V
up to 6 (Note 2)
2 to 175
V
mA
_C
Ambient Temperature Range
−40 to +85
2. Keeping the LEDx pin voltage below 6 V in operation is recommended to minimize thermal dissipation in the package.
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CAT4103
Table 3. ELECTRICAL OPERATING CHARACTERISTICS (Min and Max values are over recommended operating conditions
unless specified otherwise. Typical values are at V = 5.0 V, T
= 25°C.)
IN
AMB
Symbol
Name
Conditions
Min
Typ
Max
Units
DC CHARACTERISTICS
I
I
I
I
I
Supply Current Outputs Off
Supply Current Outputs Off
Supply Current Outputs On
Supply Current Outputs On
LED Output Leakage
V
V
V
V
V
= 5 V, R
= 24.9 kW
2
4
2
4
5
10
5
mA
mA
mA
mA
mA
kW
kW
V
DD1
DD2
DD3
DD4
LKG
LED
SET
= 5 V, R
= 5.23 kW
LED
LED
LED
LED
SET
= 0.5 V, R
= 0.5 V, R
= 24.9 kW
= 5.23 kW
SET
SET
10
1
= 5 V, Outputs Off
−1
140
R
LIN Pull−down Resistance
BIN Pull−up Resistance
180
180
250
250
LIN
R
140
BIN
V
V
SIN, BIN, CIN, LIN logic high level
SIN, BIN, CIN, LIN logic low level
0.7x V
IH
DD
0.3x V
5
IL
DD
I
IL
Logic Input Leakage Current (CIN, SIN)
V = V or GND
I
−5
0
mA
DD
V
V
xOUT Logic High Output Voltage
xOUT Logic Low Output Voltage
I
I
= −1 mA
= 1 mA
V − 0.3 V
CC
V
OH
OH
0.3
OL
OL
V
RSETx Regulated Voltage
Thermal Shutdown
1.17
1.2
150
20
1.23
V
RSET
T
°C
°C
SD
T
Thermal Hysteresis
HYS
I
/I
RSET to LED Current Gain ratio
Undervoltage Lockout (UVLO) Threshold
100 mA LED Current
400
1.8
LED RSET
V
V
UVLO
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CAT4103
Table 4. TIMING CHARACTERISTICS (Min and Max values are over recommended operating conditions unless specified
otherwise. Typical values are at V = 5.0 V, T
= 25°C.)
IN
AMB
Symbol
CIN
Name
Conditions
Min
Typ
Max
Units
f
CIN Clock Frequency
CIN Pulse Width High
CIN Pulse Width Low
25
MHz
ns
cin
t
18
18
cwh
t
ns
cwl
SIN
t
Setup time SIN to CIN
Hold time SIN to CIN
4
4
ns
ns
ssu
t
sh
LIN
T
LIN Pulse width
20
4
ns
ns
ns
lwh
t
Hold time LIN to CIN
Setup time LIN to CIN
lchd
t
8
lcsu
LEDn
t
t
Turn on Propagation delay LIN
Turn off Propagation delay LIN
LIN to LED(n) on
380
130
380
130
160
140
ns
ns
ns
ns
ns
ns
ledplon
ledploff
LIN to LED(n) off
t
Turn on Propagation delay BIN
Turn off Propagation delay BIN
LED rise time (10% to 90%)
LED fall time (90% to 10%)
BIN to LED(n) on
ledpbon
ledpboff
t
BIN to LED(n) off
t
Pullup resistor = 50 W to 3.0 V
Pullup resistor = 50 W to 3.0 V
ledr
t
ledf
SOUT
t
SOUT rise time (10% to 90%)
SOUT fall time (90% to 10%)
Propagation delay time SOUT
Propagation delay time SOUT
C = 15 pF
5
5
6
6
ns
ns
ns
ns
sr
L
t
C = 15 pF
L
sf
t
CIN falling to SOUT falling
CIN falling to SOUT rising
18
18
sdf
sdr
t
COUT
t
COUT rise time (10% to 90%)
COUT fall time (90% to 10%)
Propagation delay time COUT
Propagation delay time COUT
C = 15 pF
5
5
4
4
ns
ns
ns
ns
cr
L
t
C = 15 pF
L
cf
t
CIN falling to COUT falling
CIN rising to COUT rising
10
10
cdf
cdr
t
LOUT
t
LOUT rise time (10% to 90%)
LOUT fall time (90% to 10%)
Propagation delay time LOUT
Propagation delay time LOUT
C = 15 pF
5
5
4
5
ns
ns
ns
ns
lr
L
t
C = 15 pF
L
lf
t
LIN falling to LOUT falling
LIN rising to LOUT rising
10
10
ldf
ldr
t
BOUT
t
BOUT rise time (10% to 90%)
BOUT fall time (90% to 10%)
Propagation delay time BOUT
Propagation delay time BOUT
C = 15 pF
5
5
6
8
ns
ns
ns
ns
br
L
t
C = 15 pF
L
bf
t
BIN falling to BOUT falling
BIN rising to BOUT rising
20
20
bdf
bdr
t
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CAT4103
1/f
cin
CIN
SIN
t
t
sh
t
t
cwh
ssu
cwl
t
sdf
t
t
lcsu
lchd
t
sdr
SOUT
LIN
t
lwd
Figure 2. Timing Diagram A
t
t
ledplon
ledploff
LIN
t
ledpboff
BIN
t
ledpbon
LED(n)
Figure 3. Timing Diagram B
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CAT4103
TYPICAL PERFORMANCE CHARACTERISTICS
(V = 5 V, V = 5 V, C1 = 1 mF, T
= 25°C unless otherwise specified.)
IN
DD
AMB
1.2
1.0
0.8
8.0
No Load
6.0
4.0
0.6
0.4
2.0
0
3.0
3.5
4.0
4.5
5.0
5.5
0
100
200
300
400
INPUT VOLTAGE (V)
RSET CURRENT (mA)
Figure 4. Quiescent Current vs. Input Voltage
(ILED = 0 mA)
Figure 5. Quiescent Current vs. RSET Current
6.0
5.5
200
160
120
80
Full Load
5.0
4.5
4.0
40
0
3.0
3.5
4.0
4.5
5.0
5.5
0
0.2
0.4
0.6
0.8
1.0
INPUT VOLTAGE (V)
LED PIN VOLTAGE (V)
Figure 6. Quiescent Current vs. Input Voltage
(ILED = 175 mA)
Figure 7. LED Current vs. LED Pin Voltage
200
160
120
80
200
160
120
80
40
0
40
0
3.0
3.5
4.0
4.5
5.0
5.5
−40
0
40
80
120
INPUT VOLTAGE (V)
TEMPERATURE (°C)
Figure 8. LED Current Change vs. Input
Voltage
Figure 9. LED Current Change vs.
Temperature
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CAT4103
TYPICAL PERFORMANCE CHARACTERISTICS
(V = 5 V, V = 5 V, C = 1 mF, T = 25°C unless otherwise specified.)
IN
DD
1
AMB
1.30
1.25
1.20
1.30
1.25
1.20
1.15
1.10
1.15
1.10
3.0
3.5
4.0
4.5
5.0
5.5
−40
0
40
80
120
INPUT VOLTAGE (V)
TEMPERATURE (°C)
Figure 10. RSET Pin Voltage vs. Input Voltage
Figure 11. RSET Pin Voltage vs. Temperature
200
160
120
80
40
0
0
15
30
45
60
RSET (kW)
Figure 12. LED Current vs. RSET Resistor
Figure 13. BIN Transient Response
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CAT4103
Table 5. PIN DESCRIPTIONS
Name
GND
Pin Number
Function
1
2
Ground Reference
Blank input pin
BIN
LIN
3
Latch Data input pin
Serial Data input pin
Serial Clock input pin
SIN
4
CIN
5
RSET3
RSET2
RSET1
LED3
LED2
LED1
COUT
SOUT
LOUT
BOUT
VDD
6
LED current set pin for LED3
LED current set pin for LED2
LED current set pin for LED1
LED channel 3 cathode terminal
LED channel 2 cathode terminal
LED channel 1 cathode terminal
Serial Clock output pin
7
8
9
10
11
12
13
14
15
16
Serial Data output pin
Latch Data output pin
Blank output pin
Device Supply pin
Pin Function
GND is the ground reference pin for the entire device. This
pin must be connected to the ground plane on the PCB.
LED1 to LED3 are the LED current sink inputs. These pins
are connected to the bottom cathodes of the LED strings.
The current sinks bias the LEDs with a current equal to 400
times the RSET pin current. For the LED sink to operate
correctly, the voltage on the LED pin must be above 0.4 V.
Each LED channel can withstand and operate with voltages
up to 25 V.
BIN is the blank input used to disable all channels. When
low, all LED channels are enabled according to the output
latch content. When high, all LED channels are turned off.
This pin can be used to turn all the LEDs off while preserving
the data in the output latches.
COUT is a driven output of CIN and can be connected to the
next device in the cascade.
LIN is the latch data input. On the rising edge of LIN, data
is loaded from the 3−bit serial shift register into the output
register latch. On the falling edge of LIN the data is latched
in the output register and isolated from the state of the serial
shift register.
SOUT is the output of the 3−bit serial shift register. Connect
to SIN of the next device in the cascade. SOUT is clocked
on the falling edge of CIN.
SIN is the serial data input. Data is loaded into the internal
LOUT is a driven output of LIN and can be connected to the
register on each rising edge of CIN.
next chip in the cascade.
CIN is the serial clock input. On each rising CIN edge, data
is transferred from SIN to the internal 3−bit serial shift
register.
BOUT is a driven output of BIN and can be connected to the
next chip in the cascade.
VDD is the positive supply pin voltage for the entire device.
A small 1 mF ceramic capacitor is recommended close to the
pin.
RSET1 to RSET3 are the LED current set inputs. The
current pulled out of these pins will be mirrored in the
corresponding LED channel with a gain of 400.
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CAT4103
Block Diagram
LED1 LED2 LED3
1.2 V Ref
Current Setting
Current Setting
Current Setting
RSET1
RSET2
RSET3
VDD
CURRENT
SINKS
BIN
LIN
BOUT
BLANK
LATCH
L0
L1
L2
LOUT
SOUT
S0 S1 S2
SIN
CIN
D Q
CK
SHIFT
REGISTER
CLOCK
COUT
GND
Figure 14. CAT4103 Functional Block Diagram
Basic Operation
A high−speed 4−wire interface is provided to program the
state of each LED channel ON or OFF.
The CAT4103 uses 3 independent current sinks to
accurately regulate the current in each LED channel to 400
times the current sink from the corresponding RSET pin.
Each of the resistors tied to the RSET1, RSET2, RSET3 pins
set the current respectively in the LED1, LED2, and LED3
channels. Table 6 shows some standard resistor values for
RSET and the corresponding LED current.
The 4−wire interface contains a 3−bit serial−to−parallel
shift register (S0−S2) and a 3−bit latch (L0−L2). The shift
register operates on a first−in first−out (FIFO) basis. The
most significant bit S2 corresponds to the first data entered
in from SIN. Programming the serial−to−parallel register is
accomplished via SIN and CIN input pins. On each rising
edge of the CIN signal the data from SIN is moved through
the shift register serially. Data is also moved out of SOUT
to the next device if programming more than one device on
the same interface.
On the rising edge of LIN, the data content of the serial to
parallel shift register is reflected in the latches. On the falling
edge of LIN, the state of the serial−to−parallel register at that
particular time is saved in the latches and does not change
regardless of the content of the serial to parallel register.
BIN is used to disable all LEDs off at one time while still
maintaining the data contents of the latch register. BIN is an
active low input pin. When low the outputs reflect the data
in the latches. When high the outputs are all high impedance
(LEDs off).
Table 6. RSET RESISTOR SETTINGS
LED Current [mA]
RSET [kW]
24.9
20
60
8.45
100
175
5.23
3.01
Tight current regulation for all channels is possible over
a wide range of input and LED voltages due to independent
current sensing circuitry on each channel. The LED
channels have a low dropout of 0.4 V or less for all current
ranges and supply voltages. This helps improve heat
dissipation and efficiency over other competing solutions.
Upon power−up, an under−voltage lockout circuit clears
all latches and shift registers and sets all outputs to off. Once
the VDD supply voltage is greater than the under−voltage
lockout threshold, the device can be programmed.
All 4−wire inputs have a corresponding output driver for
cascaded systems (SOUT, COUT, LOUT, BOUT). These
output buffers allow many CAT4103 drivers to be cascaded
without signal and timing degradation due to long wire
interconnections.
Pull−up and pull−down resistors are internally provided to
set the state of the BIN and LIN pins to low current off state
when not externally driven.
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CAT4103
Application Information
Cascading Multiple Devices
The CAT4103 is designed to be cascaded for driving
multiple RGD LEDs. Figure 16 shows three CAT4103
drivers cascaded together. The programming data from the
controller travels serially through each device. Figure 15
shows a programming example turning on the following
LED channels: BLUE3, GREEN2 and RED1. The
programming waveforms are measured from the controller
to the inputs of the first CAT4103.
Figure 15. Programming Example
5 V
C1
C2
C3
1 mF
1 mF
1 mF
RED1 GREEN1 BLUE1
RED2 GREEN2 BLUE2
RED3 GREEN3 BLUE3
VDD LED1
LED2
LED3
VDD LED1
LED2
LED3
VDD LED1 LED2
BIN
LED3
BOUT
LOUT
SOUT
COUT
BIN
LIN
SIN
CIN
BOUT
LOUT
SOUT
COUT
BOUT
LOUT
SOUT
COUT
BIN
LIN
SIN
CIN
LIN
SIN
CIN
CAT4103
#1
CAT4103
#2
CAT4103
#3
RSET1 RSET2
RSET3
R3
GND RSET1 RSET2
R4 R5
RSET3
R6
GND RSET1 RSET2 RSET3
R7 R8 R9
GND
R1
R2
Figure 16. Three Cascaded CAT4103 Devices
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CAT4103
Power Dissipation
Recommended Layout
The power dissipation (P ) of the CAT4103 can be
calculated as follows:
Bypass capacitor C1 should be placed as close to the IC as
possible. RSET resistors should be directly connected to the
GND pin of the device. For better thermal dissipation,
multiple via can be used to connect the GND pad to a large
ground plane. It is also recommended to use large pads and
traces on the PCB wherever possible to spread out the heat.
The LEDs for this layout are driven from a separate supply
(VLED+), but they can also be driven from the same supply
connected to VDD.
D
P
D + (VDD IDD) ) S(VLEDN ILEDN
)
where V
is the voltage at the LED pin, and I
is the
LEDN
LEDN
associated LED current. Combinations of high V
LED
voltage or high ambient temperature can cause the CAT4103
to enter thermal shutdown. In applications where V is
LEDN
high, a resistor can be inserted in series with the LED string
to lower P .
D
Thermal dissipation of the junction heat consists
primarily of two paths in series. The first path is the junction
to the case (q ) thermal resistance which is defined by the
JC
package style, and the second path is the case to ambient
(q ) thermal resistance, which is dependent on board
CA
layout. The overall junction to ambient (q ) thermal
JA
resistance is equal to:
q
JA + qJC ) qCA
For a given package style and board layout, the operating
junction temperature T is a function of the power
J
dissipation P , and the ambient temperature, resulting in the
D
following equation:
TJ + TAMB ) PD (qJC ) qCA) + TAMB ) PD qJA
When mounted on a double−sided printed circuit board
with two square inches of copper allocated for “heat
Figure 17. Recommended Layout
spreading”, the resulting q is about 74°C/W.
JA
For example, at 60°C ambient temperature, the maximum
power dissipation is calculated as follow:
(TJmax * TAMB
)
(150 * 60)
PDmax
+
+
+ 1.2 W
qJA
74
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CAT4103
PACKAGE DIMENSIONS
SOIC−16, 150 mils
CASE 751BG−01
ISSUE O
SYMBOL
MIN
NOM
MAX
1.35
A
A1
b
1.75
0.25
0.51
0.25
0.10
0.33
0.19
c
D
E
E1
e
9.80
5.80
3.80
9.90
6.00
10.00
6.20
4.00
E1
E
3.90
1.27 BSC
h
0.25
0.40
0º
0.50
1.27
8º
L
θ
PIN#1 IDENTIFICATION
TOP VIEW
D
h
q
A
c
e
b
L
A1
END VIEW
SIDE VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
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CAT4103
Example of Ordering Information (Note 5)
Prefix
Device #
Suffix
CAT
4103
V
− G
T2
Company ID
(Optional)
Product Number
Package
V: SOIC
Lead Finish
G: NiPdAu
Tape & Reel (Note 7)
T: Tape & Reel
4103
Blank: Matte−Tin
2: 2,000 / Reel
3. All packages are RoHS−compliant (Lead−free, Halogen−free).
4. The standard plated finish is NiPdAu.
5. The device used in the above example is a CAT4103V−GT2 (SOIC, NiPdAu, Tape & Reel, 2,000/Reel).
6. For additional temperature options, please contact your nearest ON Semiconductor Sales office.
7. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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