CAT5241UI-25-TE13 [ONSEMI]
IC QUAD 2.5K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO20, 0.300 INCH, TSSOP-20, Digital Potentiometer;型号: | CAT5241UI-25-TE13 |
厂家: | ONSEMI |
描述: | IC QUAD 2.5K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO20, 0.300 INCH, TSSOP-20, Digital Potentiometer 光电二极管 转换器 电阻器 |
文件: | 总16页 (文件大小:189K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CAT5241
Quad Digital
Potentiometer (POT)
with 64 Taps
and I2C Interface
Description
http://onsemi.com
The CAT5241 is four Digital POTs integrated with control logic and
16 bytes of NVRAM memory. Each digital POT consists of a series of
63 resistive elements connected between two externally accessible end
points. The tap points between each resistive element are connected to
the wiper outputs with CMOS switches. A separate 6-bit control
register (WCR) independently controls the wiper tap switches for each
digital POT. Associated with each wiper control register are four 6-bit
non-volatile memory data registers (DR) used for storing up to four
wiper settings. Writing to the wiper control register or any of the
TSSOP−20
Y SUFFIX
CASE 948AQ
SOIC−20
W SUFFIX
CASE 751BJ
2
non-volatile data registers is via a I C serial bus. On power-up, the
PIN CONNECTIONS
contents of the first data register (DR0) for each of the four
potentiometers is automatically loaded into its respective wiper
control register (WCR).
The CAT5241 can be used as a potentiometer or as a two terminal,
variable resistor. It is intended for circuit level or system level
adjustments in a wide variety of applications.
V
CC
R
W0
1
R
R
R
R
W3
L3
L0
R
H0
A0
A2
H3
A1
A3
R
W1
CAT5241
Features
SCL
R
L1
Four Linear-taper Digital Potentiometers
64 Resistor Taps per Potentiometer
End to End Resistance 2.5 kW, 10 kW, 50 kW or 100 kW
Potentiometer Control and Memory Access via I C Interface
Low Wiper Resistance, Typically 80 W
R
W2
R
H1
R
SDA
GND
L2
R
H2
2
SOIC−20 (W)
TSSOP−20 (Y)
(Top View)
Nonvolatile Memory Storage for up to Four Wiper Settings for Each
Potentiometer
Automatic Recall of Saved Wiper Settings at Power Up
2.5 to 6.0 Volt Operation
Standby Current less than 1 mA
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
1,000,000 Nonvolatile WRITE Cycles
100 Year Nonvolatile Memory Data Retention
20-lead SOIC and TSSOP Packages
Industrial Temperature Range
These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS
Compliant
Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
July, 2013 − Rev. 20
CAT5241/D
CAT5241
MARKING DIAGRAMS
(SOIC−20)
(TSSOP−20)
L3B
CAT5241WT
−RRYMXXXX
RLB
CAT5241YT
3YMXXX
L = Assembly Location
3 = Lead Finish − Matte−Tin
B = Product Revision (Fixed as “B”)
CAT5241W = Device Code
T = Temperature Range (I = Industrial)
− = Dash
R = Resistance
1 = 2.5 KW
2 = 10 KW
4 = 50 KW
RR = Resistance
5 = 100 KW
25 = 2.5 KW
L = Assembly Location
10 = 10 KW
B = Product Revision (Fixed as “B”)
CAT5241Y = Device Code
T = Temperature Range (I = Industrial)
3 = Lead Finish − Matte−Tin
Y = Production Year (Last Digit)
M = Production Month (1−9, O, N, D)
XXX = Last Three Digits of Assembly Lot Number
50 = 50 KW
00 = 100 KW
Y = Production Year (Last Digit)
M = Production Month (1−9, O, N, D)
XXXX = Last Four Digits of Assembly Lot Number
http://onsemi.com
2
CAT5241
R
R
R
R
H3
H0
H1
H2
SCL
SDA
WIPER
2
I C BUS
CONTROL
R
W0
R
W1
R
W2
R
W3
INTERFACE
REGISTERS
A0
NONVOLATILE
DATA
REGISTERS
CONTROL
LOGIC
A1
A2
A3
R
R
R
R
L3
L0
L1
L2
Figure 1. Functional Diagram
SDA: Serial Data
Table 1. PIN DESCRIPTION
The CAT5241 bidirectional serial data pin is used to
transfer data into and out of the device. The SDA pin is an
open drain output and can be wire-OR’d with the other open
drain or open collector outputs.
Pin (SOIC)
Name
Function
1
2
R
W0
Wiper Terminal for Potentiometer 0
R
Low Reference Terminal for
Potentiometer 0
L0
A0, A1, A2, A3: Device Address Inputs
3
R
High Reference Terminal for
Potentiometer 0
H0
These inputs set the device address when addressing
multiple devices. A total of sixteen devices can be addressed
on a single bus. A match in the slave address must be made
with the address input in order to initiate communication
with the CAT5241.
4
5
6
7
A0
A2
Device Address, LSB
Device Address
R
W1
Wiper Terminal for Potentiometer 1
R
Low Reference Terminal for
Potentiometer 1
L1
RH, RL: Resistor End Points
The four sets of R and R pins are equivalent to the
terminal connections on a mechanical potentiometer.
8
R
High Reference Terminal for
Potentiometer 1
H
L
H1
9
SDA
GND
Serial Data Input/Output
Ground
RW: Wiper
10
11
The four R pins are equivalent to the wiper terminal of
a mechanical potentiometer.
W
R
High Reference Terminal for
Potentiometer 2
H2
Device Operation
The CAT5241 is four resistor arrays integrated with I C
12
R
Low Reference Terminal for
Potentiometer 2
L2
2
serial interface logic, four 6-bit wiper control registers and
sixteen 6-bit, non-volatile memory data registers. Each
resistor array contains 63 separate resistive elements
connected in series. The physical ends of each array are
equivalent to the fixed terminals of a mechanical
potentiometer (R and R ). R and R are symmetrical and
13
14
15
16
17
R
Wiper Terminal for Potentiometer 2
Bus Serial Clock
W2
SCL
A3
Device Address
A1
Device Address
R
High Reference Terminal for
Potentiometer 3
H3
H
L
H
L
may be interchanged. The tap positions between and at the
ends of the series resistors are connected to the output wiper
18
R
Low Reference Terminal for
Potentiometer 3
L3
terminals (R ) by a CMOS transistor switch. Only one tap
W
19
20
R
W3
Wiper Terminal for Potentiometer 3
Supply Voltage
point for each potentiometer is connected to its wiper
terminal at a time and is determined by the value of the wiper
control register. Data can be read or written to the wiper
control registers or the non-volatile memory data registers
V
CC
Pin Descriptions
SCL: Serial Clock
The CAT5241 serial clock input pin is used to clock all
data transfers into or out of the device.
2
via the I C bus. Additional instructions allow data to be
transferred between the wiper control registers and each
respective potentiometer’s non-volatile data registers. Also,
the device can be instructed to operate in an
“increment/decrement” mode.
http://onsemi.com
3
CAT5241
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter
Ratings
Units
C
C
V
Temperature Under Bias
−55 to +125
−65 to +150
Storage Temperature Range
Voltage on any Pin with Respect to V (Notes 1, 2)
−2.0 to +V +2.0
SS
CC
V
with Respect to Ground
−2.0 to +7.0
1.0
V
CC
Package Power Dissipation Capability (T = 25C)
W
A
Lead Soldering Temperature (10 s)
Wiper Current
300
C
mA
12
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The minimum DC input voltage is −0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is V + 0.5 V, which may overshoot to V + 2.0 V for periods of less than 20 ns.
CC
CC
2. Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1 V to V + 1 V.
CC
Table 3. RECOMMENDED OPERATING CONDITIONS
Parameter
Ratings
+2.5 to +6.0
−40 to +85
Units
V
V
CC
Operating Ambient Temperature (Industrial)
C
Table 4. POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Symbol
Parameter
Test Conditions
Min
Typ
100
50
Max
Units
kW
kW
kW
kW
%
R
R
R
R
Potentiometer Resistance (−00)
Potentiometer Resistance (−50)
Potentiometer Resistance (−10)
Potentiometer Resistance (−25)
Potentiometer Resistance Tolerance
POT
POT
POT
POT
10
2.5
20
1
R
Matching
%
POT
Power Rating
25C, each pot
50
mW
mA
W
I
W
Wiper Current
6
R
R
Wiper Resistance
Wiper Resistance
I
I
= 3 mA @ V = 3 V
300
150
W
W
CC
= 3 mA @ V = 5 V
80
W
W
W
CC
V
TERM
Voltage on any R or R Pin
V
SS
= 0 V
GND
V
CC
H
L
V
N
Noise
(Note 3)
TBD
1.6
nV/Hz
Resolution
%
Absolute Linearity (Note 4)
Relative Linearity (Note 5)
Temperature Coefficient of R
R
−R
1
LSB
W(n)(actual)
(n)(expected)
(Note 7)
(Note 6)
R
W(n+1)
−[R ]
W(n)+LSB
0.2
LSB
(Note 6)
(Note 7)
(Note 3)
(Note 3)
(Note 3)
TC
300
ppm/C
ppm/C
pF
RPOT
POT
TC
Ratiometric Temp. Coefficient
Potentiometer Capacitances
Frequency Response
20
RATIO
C /C /C
H
10/10/25
0.4
L
W
fc
R
= 50 kW (Note 3)
MHz
POT
3. This parameter is tested initially and after a design or process change that affects the parameter.
4. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
5. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer.
It is a measure of the error in step size.
6. LSB = R
/ 63 or (R − R ) / 63, single pot
TOT
H L
7. n = 0, 1, 2, ..., 63
http://onsemi.com
4
CAT5241
Table 5. D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Symbol
Parameter
Test Conditions
Min
Typ
Max
1
Units
mA
I
Power Supply Current
f
= 400 kHz
CC
SCL
I
SB
Standby Current (V = 5.0 V)
V
= GND or V ;
CC
1
mA
CC
IN
SDA = GND;
RWX = GND (Note 8)
I
Input Leakage Current
Output Leakage Current
Input Low Voltage
V
= GND to V
10
10
mA
mA
V
LI
IN
CC
I
LO
V
OUT
= GND to V
CC
V
−1
V
x 0.3
IL
CC
CC
V
Input High Voltage
V
x 0.7
V
+ 1.0
V
IH
CC
V
OL1
Output Low Voltage (V = 3.0 V)
I
OL
= 3 mA
0.4
V
CC
8. All four wiper terminals RW0, RW1, RW2, and RW3 are tied to ground.
Table 6. CAPACITANCE (Note 9) (T = 25C, f = 1.0 MHz, V = +5.0 V)
A
CC
Symbol
Parameter
Test Conditions
Min
Typ
Max
8
Units
pF
C
Input/Output Capacitance (SDA)
V
I/O
= 0 V
= 0 V
I/O
C
Input Capacitance (A0, A1, A2, A3, SCL)
V
IN
6
pF
IN
Table 7. A.C. CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Symbol
Parameter
Min
Typ
Max
400
50
Units
kHz
ns
f
Clock Frequency
SCL
T (Note 9)
I
Noise Suppression Time Constant at SCL, SDA Inputs
SLC Low to SDA Data Out and ACK Out
Time the Bus Must Be Free Before a New Transmission Can Start
Start Condition Hold Time
t
AA
0.9
ms
t
(Note 9)
1.2
0.6
1.2
0.6
0.6
0
ms
BUF
t
ms
HD:STA
t
Clock Low Period
ms
LOW
t
Clock High Period
ms
HIGH
t
Start Condition Setup Time (For a Repeated Start Condition)
Data in Hold Time
ms
SU:STA
HD:DAT
t
ns
t
Data in Setup Time
100
ns
SU:DAT
t
R
(Note 9)
SDA and SCL Rise Time
0.3
ms
t (Note 9)
F
SDA and SCL Fall Time
300
ns
t
Stop Condition Setup Time
0.6
50
ms
SU:STO
t
Data Out Hold Time
ns
DH
Table 8. POWER UP TIMING (Note 9) (Over recommended operating conditions unless otherwise stated.)
Symbol Parameter Min Typ
Power-up to Read Operation
Power-up to Write Operation
9. This parameter is tested initially and after a design or process change that affects the parameter.
Max
1
Units
ms
t
PUR
t
1
ms
PUW
Table 9. WRITE CYCLE LIMITS (Note 10) (Over recommended operating conditions unless otherwise stated.)
Symbol Parameter Min Typ
Max
Units
t
Write Cycle Time
5
ms
WR
10.The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write
cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
http://onsemi.com
5
CAT5241
Table 10. RELIABILITY CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Symbol
(Note 11)
Parameter
Endurance
Reference Test Method
MIL−STD−883, Test Method 1033
MIL−STD−883, Test Method 1008
MIL−STD−883, Test Method 3015
JEDEC Standard 17
Min
1,000,000
100
Typ
Max
Units
Cycles/Byte
Years
N
END
T
(Note 11)
(Note 11)
Data Retention
ESD Susceptibility
Latch-Up
DR
V
2000
Volts
ZAP
I
(Notes 11, 12)
100
mA
LTH
11. This parameter is tested initially and after a design or process change that affects the parameter.
12.t and t are the delays required from the time V is stable until the specified operation can be initiated.
PUR
PUW
CC
t
F
t
HIGH
t
R
t
t
LOW
LOW
SCL
t
t
HD:DAT
SU:STA
t
t
t
SU:STO
SU:DAT
HD:STA
SDA IN
t
BUF
t
t
AA
DH
SDA OUT
Figure 2. Bus Timing
SCL
SDA
8TH BIT
BYTE n
ACK
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 3. Write Cycle Timing
SDA
SCL
START BIT
STOP BIT
Figure 4. Start/Stop Timing
http://onsemi.com
6
CAT5241
Serial Bus Protocol
particular slave device it is requesting. The four most
significant bits of the 8-bit slave address are fixed as 0101
for the CAT5241 (see Figure 6). The next four significant
bits (A3, A2, A1, A0) are the device address bits and define
which device the Master is accessing. Up to sixteen devices
may be individually addressed by the system. Typically,
+5 V and ground are hard-wired to these pins to establish the
device’s address.
2
The following defines the features of the I C bus protocol:
1. Data transfer may be initiated only when the bus is
not busy.
2. During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock is high
will be interpreted as a START or STOP condition.
After the Master sends a START condition and the slave
address byte, the CAT5241 monitors the bus and responds
with an acknowledge (on the SDA line) when its address
matches the transmitted slave address.
The device controlling the transfer is a master, typically a
processor or controller, and the device being controlled is the
slave. The master will always initiate data transfers and
provide the clock for both transmit and receive operations.
Therefore, the CAT5241 will be considered a slave device
in all applications.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledging
device pulls down the SDA line during the ninth clock cycle,
signaling that it received the 8 bits of data.
The CAT5241 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation, it
responds with an acknowledge after receiving each 8-bit
byte.
When the CAT5241 is in a READ mode it transmits 8 bits
of data, releases the SDA line, and monitors the line for an
acknowledge. Once it receives this acknowledge, the
CAT5241 will continue to transmit data. If no acknowledge
is sent by the Master, the device terminates data transmission
and waits for a STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of SDA
when SCL is HIGH. The CAT5241 monitors the SDA and
SCL lines and will not respond until this condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
Device Addressing
The bus Master begins a transmission by sending a
START condition. The Master then sends the address of the
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 5. Acknowledge Timing
http://onsemi.com
7
CAT5241
Write Operation
Acknowledge Polling
In the Write mode, the Master device sends the START
condition and the slave address information to the Slave
device. After the Slave generates an acknowledge, the
Master sends the instruction byte that defines the requested
operation of CAT5241. The instruction byte consist of a
four-bit opcode followed by two register selection bits and
two pot selection bits. After receiving another acknowledge
from the Slave, the Master device transmits the data to be
written into the selected register. The CAT5241
acknowledges once more and the Master generates the
STOP condition, at which time if a non-volatile data register
is being selected, the device begins an internal programming
cycle to non-volatile memory. While this internal cycle is in
progress, the device will not respond to any request from the
Master device.
The disabling of the inputs can be used to take advantage
of the typical write cycle time. Once the stop condition is
issued to indicate the end of the host’s write operation, the
CAT5241 initiates the internal write cycle. ACK polling can
be initiated immediately. This involves issuing the start
condition followed by the slave address. If the CAT5241 is
still busy with the write operation, no ACK will be returned.
If the CAT5241 has completed the write operation, an ACK
will be returned and the host can then proceed with the next
instruction operation.
CAT5241
0
1
0
1
A3
A2
A1
A0
* A0, A1, A2 and A3 correspond to pin A0, A1, A2 and A3 of the device.
** A0, A1, A2 and A3 must compare to its corresponding hard wired input pins.
Figure 6. Slave Address Bits
INSTRUCTION
BYTE
S
T
A
R
T
SLAVE
S
T
O
P
ADDRESS
BUS ACTIVITY:
MASTER
Fixed Variable
DR WCR DATA
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
Figure 7. Write Timing
http://onsemi.com
8
CAT5241
Instruction Byte
Instructions and Register Description
The next byte sent to the CAT5241 contains the
instruction and register pointer information. The four most
significant bits used provide the instruction opcode I [3:0].
The P1 and P0 bits point to one of four Wiper Control
Registers. The least two significant bits, R1 and R0, point to
one of the four data registers of each associated
potentiometer. The format is shown in Figure 9.
Slave Address Byte
The first byte sent to the CAT5241 from the master/
processor is called the Slave Address Byte. The most
significant four bits of the slave address are a device type
identifier. These bits for the CAT5241 are fixed at 0101[B]
(refer to Figure 8).
The next four bits, A3 − A0, are the internal slave address
and must match the physical device address which is defined
by the state of the A3 − A0 input pins for the CAT5241 to
successfully continue the command sequence. Only the
device which slave address matches the incoming device
address sent by the master executes the instruction. The A3
− A0 inputs can be actively driven by CMOS input signals
Table 11. DATA REGISTER SELECTION
Data Register Selected
R1
0
R0
0
DR0
DR1
DR2
DR3
0
1
1
0
or tied to V or V
.
CC
SS
1
1
Device Type Identifier
Slave Address
ID3
0
ID2
1
ID1
ID0
A3
A2
A1
A0
0
1
(LSB)
(MSB)
Figure 8. Identification Byte Format
Data Register
Selection
Instruction
Opcode
WCR/Pot Selection
I3
I2
I1
I0
P1
P0
R1
R0
(LSB)
(MSB)
Figure 9. Instruction Byte Format
http://onsemi.com
9
CAT5241
Data Registers (DR)
Wiper Control and Data Registers
Each potentiometer has four 6-bit non-volatile Data
Registers. These can be read or written directly by the host.
Data can also be transferred between any of the four Data
Registers and the associated Wiper Control Register. Any
data changes in one of the Data Registers is a non-volatile
operation and will take a maximum of 5 ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can be used
as standard memory locations for system parameters or user
preference data.
Wiper Control Register (WCR)
The CAT5241 contains four 6-bit Wiper Control
Registers, one for each potentiometer. The Wiper Control
Register output is decoded to select one of 64 switches along
its resistor array. The contents of the WCR can be altered in
four ways: it may be written by the host via Write Wiper
Control Register instruction; it may be written by
transferring the contents of one of four associated Data
Registers via the XFR Data Register instruction, it can be
modified one step at a time by the Increment/decrement
instruction (see Instruction section for more details).
Finally, it is loaded with the content of its data register zero
(DR0) upon power-up.
Instructions
Four of the nine instructions are three bytes in length.
These instructions are:
The Wiper Control Register is a volatile register that loses
its contents when the CAT5241 is powered-down. Although
the register is automatically loaded with the value in DR0
upon power-up, this may be different from the value present
at power-down.
Read Wiper Control Register – read the current wiper
position of the selected potentiometer in the WCR
Write Wiper Control Register – change current wiper
position in the WCR of the selected potentiometer
Read Data Register – read the contents of the selected
Data Register
Write Data Register – write a new value to the
selected Data Register.
Table 12. INSTRUCTION SET (Note: 1/0 = data is one or zero)
Instruction Set
I3
I2
I1
I0
WCR1/P1
WCR0/P0
R1
R0
Instruction
Operations
Read Wiper Control
Register
1
0
0
1
1/0
1/0
0
0
Read the contents of the Wiper
Control Register pointed to by P1−P0
Write Wiper Control
Register
1
1
0
0
1
1
0
1
1/0
1/0
1/0
1/0
0
0
Write new value to the Wiper Control
Register pointed to by P1−P0
Read Data Register
1/0
1/0
Read the contents of the Data
Register pointed to by P1−P0 and
R1−R0
Write Data Register
1
1
1
1
0
0
0
1
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
Write new value to the Data Register
pointed to by P1−P0 and R1−R0
XFR Data Register to
Wiper Control Register
Transfer the contents of the Data
Register pointed to by P1−P0 and
R1−R0 to its associated Wiper Control
Register
XFR Wiper Control
Register to Data
Register
1
0
1
0
1
0
0
0
1
0
0
1
0
1
0
0
1/0
0
1/0
0
1/0
1/0
1/0
0
1/0
1/0
1/0
0
Transfer the contents of the Wiper
Control Register pointed to by P1−P0
to the Data Register pointed to by
R1−R0
Global XFR Data
Registers to Wiper
Control Registers
Transfer the contents of the Data
Registers pointed to by R1−R0 of all
four pots to their respective Wiper
Control Registers
Global XFR Wiper
Control Registers to
Data Register
0
0
Transfer the contents of both Wiper
Control Registers to their respective
data Registers pointed to by R1−R0 of
all four pots
Increment/Decrement
Wiper Control Register
1/0
1/0
Enable Increment/decrement of the
Control Latch pointed to by P1−P0
http://onsemi.com
10
CAT5241
The basic sequence of the three byte instructions is
Global XFR Data Register to Wiper Control
Register
This transfers the contents of all specified Data Registers
to the associated Wiper Control Registers.
Global XFR Wiper Counter Register to Data
Register
illustrated in Figure 11. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. The WCR controls the position of the wiper. The
response of the wiper to this action will be delayed by t
.
WRL
A transfer from the WCR (current wiper position), to a Data
Register is a write to non-volatile memory and takes a
This transfers the contents of all Wiper Control Registers
to the specified associated Data Registers.
maximum of t
to complete. The transfer can occur
WR
between one of the four potentiometers and one of its
associated registers; or the transfer can occur between all
potentiometers and one associated register.
Four instructions require a two-byte sequence to
complete, as illustrated in Figure 10. These instructions
transfer data between the host/processor and the CAT5241;
either between the host and one of the data registers or
directly between the host and the Wiper Control Register.
These instructions are:
Increment/Decrement Command
The final command is Increment/Decrement (Figures 6
and 12). The Increment/Decrement command is different
from the other commands. Once the command is issued and
the CAT5241 has responded with an acknowledge, the
master can clock the selected wiper up and/or down in one
segment steps; thereby providing a fine tuning capability to
the host. For each SCL clock pulse (t
) while SDA is
HIGH
HIGH, the selected wiper will move one resistor segment
XFR Data Register to Wiper Control Register
This transfers the contents of one specified Data
Register to the associated Wiper Control Register.
XFR Wiper Control Register to Data Register
This transfers the contents of the specified Wiper
Control Register to the specified associated Data
Register.
towards the R terminal. Similarly, for each SCL clock
H
pulse while SDA is LOW, the selected wiper will move one
resistor segment towards the R terminal.
L
See Instructions format for more detail.
0
1
0
1
SDA
ID3 ID2 ID1 ID0
S
T
A3 A2 A1 A0
A
C
K
S
T
A
R
T
A
C
K
I3 I2 I1 I0
R1 R0
P1 P0
O
P
Internal
Address
Instruction
Opcode
Device ID
Register
Address
Pot/WCR
Address
Figure 10. Two-Byte Instruction Sequence
SDA
0
1
0
1
S
T
A
R
T
A
ID3 ID2 ID1 ID0
Device ID
A
C
K
I3 I2 I1 I0 P1 P0 R1 R0
D7 D6 D5 D4 D3 D2 D1 D0
A
C
K
S
T
A3 A2 A1 A0
C
K
O
P
Internal
Address
WCR[7:0]
or
Instruction
Opcode
Pot/WCR
Address
Data
Register
Address
Data Register D[7:0]
Figure 11. Three-Byte Instruction Sequence
0
1
0
1
SDA
ID3 ID2 ID1 ID0
Device ID
I1
A3 A2 A1 A0
I3
I2
I0
A
C
K
P1 P0 R1 R0
S
A
C
K
I
I
D
E
C
1
S
I
D
E
C
n
T
A
R
T
T
O
P
N
C
1
N
C
2
N
C
n
Internal
Address
Instruction
Opcode
Data
Pot/WCR
Address
Register
Address
Figure 12. Increment/Decrement Instruction Sequence
http://onsemi.com
11
CAT5241
INC/DEC
Command
Issued
t
WRID
SCL
SDA
Voltage Out
R
W
Figure 13. Increment/Decrement Timing Limits
Instruction Format
Table 13. READ WIPER CONTROL REGISTER (WCR)
S
T
A
R
T
DEVICE ADDRESSES
A3 A2 A1 A0
A
C
K
INSTRUCTION
P1 P0
A
C
K
DATA
A
C
K
S
T
O
P
0
1
0
1
1
0
0
1
0
0
0
0
7
7
7
7
6
6
6
6
5
5
5
5
4
3
2
2
2
2
1
1
1
1
0
0
0
0
Table 14. WRITE WIPER CONTROL REGISTER (WCR)
S
T
A
R
T
DEVICE ADDRESSES
A3 A2 A1 A0
A
C
K
INSTRUCTION
P1 P0
A
C
K
DATA
A
C
K
S
T
O
P
0
1
0
1
1
1
1
0
0
1
1
1
0
0
4
3
Table 15. READ DATA REGISTER (DR)
S
T
A
R
T
DEVICE ADDRESSES
A3 A2 A1 A0
A
C
K
INSTRUCTION
P1 P0
A
C
K
DATA
A
C
K
S
T
O
P
0
1
0
1
1
R1 R0
4
3
Table 16. WRITE DATA REGISTER (DR)
S
T
A
R
T
DEVICE ADDRESSES
A3 A2 A1 A0
A
C
K
INSTRUCTION
P1 P0
A
C
K
DATA
A
C
K
S
T
O
P
0
1
0
1
0
R1 R0
4
3
http://onsemi.com
12
CAT5241
Instruction Format (continued)
Table 17. GLOBAL TRANSFER DATA REGISTER (DR)
TO WIPER CONTROL REGISTER (WCR)
S
T
A
R
T
DEVICE ADDRESSES
A3 A2 A1 A0
A
C
K
INSTRUCTION
A
C
K
S
T
O
P
0
1
0
1
0
0
0
1
0
0
R1 R0
Table 18. GLOBAL TRANSFER WIPER CONTROL REGISTER (WCR)
TO DATA REGISTER (DR)
S
T
A
R
T
DEVICE ADDRESSES
A3 A2 A1 A0
A
C
K
INSTRUCTION
A
C
K
S
T
O
P
0
1
0
1
1
0
0
0
0
0
R1 R0
R1 R0
R1 R0
Table 19. TRANSFER WIPER CONTROL REGISTER (WCR)
TO DATA REGISTER (DR)
S
T
A
R
T
DEVICE ADDRESSES
A3 A2 A1 A0
A
C
K
INSTRUCTION
P1 P0
A
C
K
S
T
O
P
0
1
0
1
1
1
1
0
Table 20. TRANSFER DATA REGISTER (DR)
TO WIPER CONTROL REGISTER (WCR)
S
T
A
R
T
DEVICE ADDRESSES
A3 A2 A1 A0
A
C
K
INSTRUCTION
P1 P0
A
C
K
S
T
O
P
0
1
0
1
1
1
0
1
Table 21. INCREMENT (I)/DECREMENT (D) WIPER CONTROL REGISTER (WCR)
S
T
A
R
T
DEVICE ADDRESSES
A3 A2 A1 A0
A
C
K
INSTRUCTION
P1 P0
A
C
K
DATA
S
T
O
P
0
1
0
1
0
0
1
0
0
0
I/D
I/D
. . .
I/D
I/D
NOTE: Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after a STOP has been issued.
http://onsemi.com
13
CAT5241
Table 22. ORDERING INFORMATION
†
Orderable Part Number
CAT5241WI−25−T1
CAT5241WI−10−T1
CAT5241WI−50−T1
CAT5241WI−00−T1
CAT5241YI−25−T2
CAT5241YI−10−T2
CAT5241YI−50−T2
CAT5241YI−00−T2
CAT5241WI25
Resistance (kW)
Lead Finish
Package
Shipping
2.5
10
SOIC
(Pb−Free)
1000 / Tape & Reel
2000 / Tape & Reel
36 Units / Tube
50
100
2.5
10
TSSOP
(Pb−Free)
50
100
2.5
10
Matte−Tin
CAT5241WI10
SOIC
(Pb−Free)
CAT5241WI50
50
CAT5241WI00
100
2.5
10
CAT5241YI25
CAT5241YI10
TSSOP
(Pb−Free)
74 Units / Tube
CAT5241YI50
50
CAT5241YI00
100
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
13.For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device
Nomenclature document, TND310/D, available at www.onsemi.com.
14.All packages are RoHS-compliant (Lead-free, Halogen-free).
15.The standard lead finish is Matte-Tin.
16.For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.
http://onsemi.com
14
CAT5241
PACKAGE DIMENSIONS
SOIC−20, 300 mils
CASE 751BJ
ISSUE O
SYMBOL
MIN
NOM
MAX
2.64
0.30
2.55
0.51
0.33
13.00
10.64
7.60
2.36
2.49
A
A1
A2
b
0.10
2.05
0.31
0.41
0.27
c
0.20
E1
E
D
12.60
10.01
7.40
12.80
10.30
7.50
E
E1
e
1.27 BSC
h
0.25
0.40
0º
0.75
1.27
8º
0.81
L
b
e
θ
5º
15º
θ1
PIN#1 IDENTIFICATION
TOP VIEW
D
h
h
q1
q
A2
A
q1
L
c
A1
END VIEW
SIDE VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-013.
http://onsemi.com
15
CAT5241
PACKAGE DIMENSIONS
TSSOP20, 4.4x6.5
CASE 948AQ
ISSUE A
b
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
1.20
0.15
1.05
0.30
0.20
6.60
6.50
4.50
0.05
0.80
0.19
0.09
6.40
6.30
4.30
E1
E
c
D
6.50
6.40
E
E1
e
4.40
0.65 BSC
0.60
L
0.45
0.75
L1
1.00 REF
0º
8º
θ
e
TOP VIEW
D
c
A2
A
θ1
L
A1
L1
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
CAT5241/D
相关型号:
CAT5241UI-50
Quad Digitally Programmable Potentiometers (DPP⑩) with 64 Taps and 2-wire Interface
CATALYST
CAT5241UI-50-TE13
Digital Potentiometer, 4 Func, 50000ohm, 2-wire Serial Control Interface, 64 Positions, PDSO20, 0.300 INCH, TSSOP-20
CATALYST
CAT5241W-00
IC QUAD 100K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO20, 0.300 INCH, LEAD AND HALOGEN FREE, SOIC-20, Digital Potentiometer
CATALYST
CAT5241W-00-TE13
QUAD 100K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO20, 0.300 INCH, LEAD AND HALOGEN FREE, SOIC-20
CATALYST
CAT5241W-00TE13
100K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO20, 0.300 INCH, LEAD FREE, HALOGEN FREE, SOIC-20
CATALYST
CAT5241W-10-TE13
QUAD 10K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO20, 0.300 INCH, LEAD AND HALOGEN FREE, SOIC-20
CATALYST
CAT5241W-10TE13
10K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO20, 0.300 INCH, LEAD FREE, HALOGEN FREE, SOIC-20
CATALYST
CAT5241W-50TE13
50K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO20, 0.300 INCH, LEAD FREE, HALOGEN FREE, SOIC-20
ONSEMI
CAT5241WI-00
Quad Digitally Programmable Potentiometers (DPP⑩) with 64 Taps and 2-wire Interface
CATALYST
CAT5241WI-00-T1
Quad Digitally Programmable Potentiometer (DPP™) with 64 Taps and I²C Interface
ONSEMI
CAT5241WI-00-T1
Digital Potentiometer, 4 Func, 100000ohm, 2-wire Serial Control Interface, 64 Positions, PDSO20, 0.300 INCH, ROHS COMPLIANT, MS-013, SOIC-20
CATALYST
©2020 ICPDF网 联系我们和版权申明