CAT64LC40Y [ONSEMI]
IC,SERIAL EEPROM,256X16,CMOS,TSSOP,8PIN,PLASTIC;
| 型号： | CAT64LC40Y |
| 厂家： | 
ONSEMI |
| 描述： | IC,SERIAL EEPROM,256X16,CMOS,TSSOP,8PIN,PLASTIC 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总12页 (文件大小：138K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT64LC40
4 kb SPI Serial EEPROM
Description
The CAT64LC40 is a 4 kb Serial EEPROM which is configured as
256 registers by 16 bits. Each register can be written (or read) serially
by using the DI (or DO) pin. The CAT64LC40 is manufactured using
ON Semiconductor’s advanced CMOS EEPROM floating gate
technology. It is designed to endure 1,000,000 program/erase cycles
and has a data retention of 100 years. The device is available in 8−pin
DIP, SOIC and TSSOP packages.
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Features
• SPI Bus Compatible
PDIP−8
P, L SUFFIX
CASE 646AA
• Low Power CMOS Technology
• 2.5 V to 6.0 V Operation
• Self−Timed Write Cycle with Auto−Clear
• Hardware Reset Pin
• Hardware and Software Write Protection
• Commercial, Industrial and Automotive Temperature Ranges
• Power−up Inadvertent Write Protection
• RDY/BSY Pin for End−of−Write Indication
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
SOIC−8
J, W, S, V SUFFIX
CASE 751BD
TSSOP−8
U, Y SUFFIX
CASE 948AL
• This Device is Pb−Free, Halogen Free/BFR Free and RoHS
Compliant*
GND
V
CC
PIN FUNCTION
Pin Name
Function
CS
SK
DI
Chip Select
ADDRESS
DECODER
MEMORY ARRAY
256 x 16
Clock Input
Serial Data Input
Serial Data Output
+2.5 V to +6.0 V Power Supply
Ground
DO
V
CC
DATA
REGISTER
GND
OUTPUT
BUFFER
DI
RESET
Reset
MODE DECODE
LOGIC
RDY/BUSY
Ready/BUSY Status
RESET
CS
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
CLOCK
GENERATOR
DO
RDY/BUSY
SK
Figure 1. Block Diagram
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2009
1
Publication Order Number:
September, 2009 − Rev. 4
CAT64LC40/D
CAT64LC40
PIN CONNECTIONS
1
2
3
4
8
7
6
5
V
CC
CS
SK
DI
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
CS
SK
DI
V
CC
RDY/BUSY
RESET
GND
DO
RDY/BUSY
RESET
GND
RDY/BUSY
RESET
GND
V
CC
CS
SK
DO
DO
DI
TSSOP−8 (U, Y)
PDIP−8 (P, L)
SOIC−8 (J, W)
1
2
3
4
8
7
6
5
V
CS
SK
CC
RDY/BUSY
RESET
GND
DI
DO
SOIC−8 (S, V)
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Unit
Temperature Under Bias
−55 to +125
−65 to +150
°C
°C
V
Storage Temperature
Voltage on any Pin with Respect to Ground (Note 1)
−2.0 to +V +2.0
CC
V
with Respect to Ground
−2.0 to +7.0
1.0
V
CC
Package Power Dissipation Capability (T = 25°C)
W
A
Lead Soldering Temperature (10 secs)
Output Short Circuit Current (Note 2)
300
°C
mA
100
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The minimum DC input voltage is −0.5 V. During transitions, inputs may undershoot to −2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is V + 0.5 V, which may overshoot to V + 2.0 V for periods of less than 20 ns.
CC
CC
2. Output shorted for no more than one second. No more than one output shorted at a time.
Table 2. RELIABILITY CHARACTERISTICS
Symbol
(Note 3)
Parameter
Min
1,000,000
100
Max
Units
Cycles/Byte
Years
N
Endurance
END
T
(Note 3)
(Note 3)
Data Retention
ESD Susceptibility
Latch−Up
DR
V
2000
V
ZAP
I
(Notes 3 and 4)
100
mA
LTH
3. This parameter is tested initially and after a design or process change that affects the parameter.
4. Latch−up protection is provided for stresses up to 100 mA on address and data pins from −1 V to V +1 V.
CC
Table 3. CAPACITANCE (T = 25°C, f = 1.0 MHz, V = 6.0 V)
A
CC
Symbol
(Note 5)
Test
Conditions
Max
8
Units
pF
C
C
Input/Output Capacitance (DO, RDY/BSY)
Input Capacitance (CS, SK, DI, RESET)
V
I/O
= 0 V
= 0 V
I/O
(Note 5)
V
IN
6
pF
IN
5. This parameter is tested initially and after a design or process change that affects the parameter.
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2
CAT64LC40
Table 4. D.C. OPERATING CHARACTERISTICS (V = +2.5 V to +6.0 V, unless otherwise specified.)
CC
Limits
Typ
Min
Max
0.4
1
Symbol
Parameter
Operating Current
Test Conditions
= 250 kHz
Units
mA
mA
mA
mA
mA
I
2.5 V
6.0 V
2.5 V
6.0 V
f
SK
CC
EWEN, EWDS, READ
Program Current
f
SK
= 1 MHz
I
2
CCP
3
I
(Note 6)
Standby Current
V
V
= GND or V
3
SB
IN
CC
CS = V
CC
I
LI
Input Leakage Current
= GND to V
2
mA
mA
V
IN
CC
I
LO
Output Leakage Current
Low Level Input Voltage, DI
High Level Input Voltage, DI
V
= GND to V
CC
10
OUT
V
IL
−0.1
V
x 0.3
CC
CC
V
IH
V
x 0.7
V
+ 0.5
x 0.2
+ 0.5
V
CC
V
IL
Low Level Input Voltage, CS, SK, RESET
High Level Input Voltage, CS, SK, RESET
−0.1
V
V
CC
CC
V
IH
V
V
V
x 0.8
V
V
CC
CC
CC
V
(Note 6)
(Note 6)
High Level Output Voltage
2.5 V
6.0 V
− 0.3
− 0.3
V
I
= −10 mA
OH
OH
I
= −10 mA
= −400 mA
= 10 mA
V
OH
I
2.4
V
OH
V
Low Level Output Voltage
2.5 V
6.0 V
0.4
V
I
OL
OL
I
OL
= 2.1 mA
0.4
V
6. V and V spec applies to READY/BUSY pin also.
OH
OL
Table 5. A.C. OPERATING CHARACTERISTICS (V = +2.5 V to +6.0 V, unless otherwise specified.)
CC
Limits
Typ
Min
100
100
200
200
Max
Symbol
Parameter
Units
ns
t
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
CSS
t
ns
CSH
t
ns
DIS
DIH
PD1
PD0
t
ns
t
t
Output Delay to 1
Output Delay to 0
300
300
500
ns
ns
t
(Note 7)
Output Delay to High Impedance
Minimum CS High Time
ns
HZ
t
250
1000
400
ns
CSMIN
t
Minimum SK High Time
2.5 V
ns
SKHI
4.5 V − 6.0 V
2.5 V
t
Minimum SK Low Time
1000
400
ns
SKLOW
4.5 V − 6.0 V
t
f
Output Delay to Status Valid
Maximum Clock Frequency
500
ns
SV
2.5 V
250
1000
0
kHz
SK
4.5 V − 6.0 V
t
Reset to CS Setup Time
Minimum RESET High Time
RESET to READY Hold Time
Write Recovery
ns
ns
ns
ns
RESS
t
250
0
RESMIN
t
RESH
t
100
RC
7. This parameter is sampled but not 100% tested.
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3
CAT64LC40
Table 6. POWER−UP TIMING (Notes 8 and 9)
Symbol
Parameter
Min
Max
10
1
Units
ms
t
Power−Up to Read Operation
PUR
t
Power−Up to Program Operation
ms
PUW
8. This parameter is tested initially and after a design or process change that affects the parameter.
9. t and t are the delays required from the time V is stable until the specified operation can be initiated.
PUR
PUW
CC
Table 7. WRITE CYCLE LIMITS
Symbol
Parameter
Min
Max
10
5
Units
t
Program Cycle Time
2.5 V
ms
WR
4.5 V − 6.0 V
Table 8. INSTRUCTION SET
Instruction
Opcode
Address
Data
Read
10101000
10100100
10100011
10100000
10100001
A7 A6 A5 A4 A3 A2 A1 A0
A7 A6 A5 A4 A3 A2 A1 A0
X X X X X X X X
D15 − D0
D15 − D0
Write
Write Enable
Write Disable
X X X X X X X X
[Write All Locations] (Note 10)
X X X X X X X X
D15 − D0
10.(Write All Locations) is a test mode operation and is therefore not included in the AC/DC Operations specifications.
V
V
x 0.8
x 0.2
CC
V
V
x 0.7
x 0.3
CC
INPUT PULSE LEVELS
REFERENCE POINTS
CC
CC
Figure 2. AC Testing Input/Output Waveform (Notes 11, 12 and 13) (C = 100 pF)
L
11. Input Rise and Fall Times (10% to 90%) < 10 ns.
12.Input Pulse Levels = V x 0.2 and V x 0.8.
CC
CC
13.Input and Output Timing Reference = V x 0.3 and V x 0.7.
CC
CC
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4
CAT64LC40
Device Operation
on the rising edge of the SK clock. The DO pin is normally
in a high impedance state except when outputting data in a
READ operation or outputting RDY/BSY status when
polled during a WRITE operation.
The format for all instructions sent to this device includes
a 4−bit start sequence, 1010, a 4−bit op code and an 8−bit
address field or dummy bits. For a WRITE operation, a
16−bit data field is also required following the 8−bit address
field.
The CAT64LC40 is a 4 kb nonvolatile memory intended
for use with all standard controllers. The CAT64LC40 is
organized in a 256 x 16 format. All instructions are based on
an 8−bit format. There are four 16−bit instructions: READ,
WRITE, EWEN, and EWDS. The CAT64LC40 operates on
a single power supply ranging from 2.5 V to 6.0 V and it has
an on−chip voltage generator to provide the high voltage
needed during a programming operation. Instructions,
addresses and data to be written are clocked into the DI pin
RESET
t
t
t
RESS
SKLOW
SKHI
SK
t
t
DIH
DIS
DI
CS
DO
t
t
t
CSMIN
CSS
CSH
t
SV
t
HZ
t
, t
PD0 PD1
t
t
SV
t
RESH
RC
RDY/BUSY
Figure 3. Synchronous Data Timing
RESET
SK
CS
DI
1
0
1
0
1
0
0
0
ADDRESS*
DO
D15 D14
D1 D0
HIGH
RDY/BUSY
Figure 4. Read Instruction Timing
*Please check the instruction set table for address
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5
CAT64LC40
Write
The CAT64LC40 requires an active LOW CS in order to
be selected. Each instruction must be preceded by a
HIGH−to−LOW transition of CS before the input of the
4−bit start sequence. Prior to the 4−bit start sequence (1010),
the device will ignore inputs of all other logical sequence.
After receiving a WRITE op code, address and data, the
device goes into the AUTO−Clear cycle and then the
WRITE cycle. The RDY/BSY pin will output the BUSY
status (LOW) one t after the rising edge of the 32 clock
nd
SV
(the last data bit) and will stay LOW until the write cycle is
complete. Then it will output a logical “1” until the next
WRITE cycle. The RDY/BSY output is not affected by the
input of CS.
Read
Upon receiving a READ command and address (clocked
into the DI pin), the DO pin will output data one t after the
falling edge of the 16th clock (the last bit of the address
field). The READ operation is not affected by the RESET
input.
PD
RESET
SK
CS
DI
ADDRESS*
D15
D0
1
0
1
0
0
1
0
0
DO
RDY/BUSY
Figure 5. Write Instruction Timing
*Please check instruction set table for address.
RESET
LOW
SK
CS
WRITE INSTRUCTION
NEXT INSTRUCTION
DI
DO
HIGH
RDY/BUSY
Figure 6. Ready/BUSY Status Instruction Timing
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6
CAT64LC40
An alternative to get RDY/BSY status is from the DO pin.
The WRITE operation can be halted anywhere in the
operation by the RESET input. If a RESET pulse occurs
during a WRITE operation, the device will abort the
operation and output a READY status.
During a write cycle, asserting a LOW input to the CS pin
will cause the DO pin to output the RDY/BSY status.
Bringing CS HIGH will bring the DO pin back to a high
impedance state again. After the device has completed a
WRITE cycle, the DO pin will output a logical “1” when the
device is deselected. The rising edge of the first “1” input on
the DI pin will reset DO back to the high impedance state
again.
NOTE: Data may be corrupted if a RESET occurs while the
device is BUSY. If the reset occurs before the BUSY period,
no writing will be initiated. However, if RESET occurs after
the BUSY period, new data will have been written over the
old data.
RESET
SK
CS
DI
1
0
1
0
0
1
0
0
ADDRESS*
D15
D0
DO
t
WR
RDY/BUSY
*Please check instruction set table for address.
Figure 7. RESET During BUSY Instruction Timing
RESET
SK
CS
DI
1
0
1
0
0
0
1
1
HIGH−Z
DO
HIGH
RDY/BUSY
Figure 8. EWEN Instruction Timing
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7
CAT64LC40
Reset
Erase/Write Enable and Disable
The RESET pin, when set to HIGH, will reset or abort a
The CAT64LC40 powers up in the erase/write disabled
state. After power−up or while the device is in an erase/write
disabled state, any write operation must be preceded by an
execution of the EWEN instruction. Once enabled, the
device will stay enabled until an EWDS has been executed
or a power−down has occurred. The EWDS is used to
prevent any inadvertent over−writing of the data. The
EWEN and EWDS instructions have no affect on the READ
operation and are not affected by the RESET input.
WRITE operation. When RESET is set to HIGH while the
WRITE instruction is being entered, the device will not
execute the WRITE instruction and will keep DO in High−Z
condition.
When RESET is set to HIGH, while the device is in a
clear/write cycle, the device will abort the operation and will
display READY status on the RDY/BSY pin and on the DO
pin if CS is low.
The RESET input affects only the WRITE and
WRITEALL operations. It does not reset any other
operations such as READ, EWEN and EWDS.
RESET
SK
CS
DI
1
0
1
0
0
0
0
0
HIGH−Z
DO
HIGH
RDY/BUSY
Figure 9. EWDS Instruction Timing
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8
CAT64LC40
PACKAGE DIMENSIONS
PDIP−8, 300 mils
CASE 646AA−01
ISSUE A
SYMBOL
MIN
NOM
MAX
A
5.33
A1
A2
b
0.38
2.92
0.36
3.30
0.46
1.52
0.25
9.27
4.95
0.56
1.78
0.36
10.16
b2
c
1.14
0.20
9.02
E1
D
E
E1
e
7.62
6.10
7.87
6.35
8.25
7.11
2.54 BSC
7.87
2.92
10.92
3.80
eB
L
PIN # 1
IDENTIFICATION
3.30
D
TOP VIEW
E
A2
A1
A
c
b2
L
eB
e
b
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.
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9
CAT64LC40
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
SYMBOL
MIN
NOM
MAX
1.35
A
A1
b
1.75
0.25
0.51
0.25
0.10
0.33
0.19
c
E1
E
D
E
E1
e
4.80
5.80
3.80
5.00
6.20
4.00
1.27 BSC
h
0.25
0.40
0º
0.50
1.27
8º
L
PIN # 1
IDENTIFICATION
θ
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
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10
CAT64LC40
PACKAGE DIMENSIONS
TSSOP8, 4.4x3
CASE 948AL−01
ISSUE O
b
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
1.20
0.15
1.05
0.30
0.20
3.10
6.50
4.50
0.05
0.80
0.19
0.09
2.90
6.30
4.30
0.90
E
c
E1
D
3.00
6.40
E
E1
e
4.40
0.65 BSC
1.00 REF
0.60
L
L1
0.50
0.75
0º
8º
θ
e
TOP VIEW
D
c
A2
A
q1
A1
L1
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
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11
CAT64LC40
Example of Ordering Information
Prefix
Device #
Suffix
CAT
64LC40
V
I
− G
T3
Temperature Range
Tape & Reel (Note 18)
Company ID
Blank = Commercial (0°C to +70°C)
I = Industrial (−40°C to +85°C)
A = Automotive (−40°C to +105°C)*
T3: 3,000 / Tape & Reel
Product Number
64LC40
Lead Finish
Package
G: NiPdAu
Blank: Matte−Tin
P: PDIP
S: SOIC (JEDEC)
J: SOIC (JEDEC)
U: TSSOP
L: PDIP (Lead free, Halogen free)
V: SOIC (JEDEC) (Lead free, Halogen free)
W: SOIC (JEDEC) (Lead free, Halogen free)
Y: TSSOP (Lead free, Halogen free)
*−40°C to +125°C is available upon request.
ORDERING INFORMATION
Orderable Part Number
(for Pb−Free Devices)
CAT64LC40LI−GT3
CAT64LC40VI−GT3
CAT64LC40WI−GT3
CAT64LC40YI−GT3
14.All packages are RoHS−compliant (Lead−free, Halogen−free).
15.The standard lead finish is NiPdAu.
16.The device used in the above example is a 64LC40VI−GT3 (SOIC, Industrial Temperature, Tape & Reel).
17.For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.
18.For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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CAT64LC40/D
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