CAT874-80ULGT3 [ONSEMI]

开关控制器;


型号：	CAT874-80ULGT3
厂家：	ONSEMI
描述：	开关控制器开关控制器
文件：	总8页 (文件大小：181K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CAT874

Smart Phone Battery Switch

Controller

Description

CAT874 is a switch controller designed to start/shut−off smart

phones with the push button input or by phone microcontroller unit.

CAT874 monitors two inputs and outputs an active high output after

PWR_ON input has been active (logic low) for a factory preset

minimum time. Releasing input from its active state before the

minimum timeout period resets the internal timer and must return to

being active before the timer will restart with a fresh count down. The

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output remains high until the next PWR_ON high−to−low or V

low−to−hightransition.

CHG

ULLGA−6

UL SUFFIX

CASE 613AF

CAT874’s push pull output is capable of sinking up to 3 mA of

current.

Features

MARKING DIAGRAM

• Operate on 1.8 V to 5.5 V Power Supplies

• Ultra Low Quiescent Current: 100 nA (typical)

• Schmitt Trigger Inputs

• Small mLLGA−6 Package: 1.45 x 1.0 x 0.4 mm

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

= Specific Device Code

= ( = CAT874)

= Date Code

“P” written at 180° clockwise rotation

Typical Applications

• Mobile Phones

• PDAs

PIN CONNECTIONS

• MP3 Players

PWR ON

VDD

OUT

GND

• Personal Navigation Devices

CHG

NIC

(Top View)

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 7 of this data sheet.

Figure 1. Application Schematic

Publication Order Number:

July, 2013 − Rev. 1

CAT874/D

CAT874

Figure 2. Functional Block Diagram

Description

Table 1. PIN FUNCTION DESCRIPTION

Pin No.

Pin Name

PWR_ON

Power ON, CMOS input.

CHG

Charger IN, CMOS input.

NIC

GND

OUT

VDD

No Internal Connection. A voltage or signal applied to this pin will have no effect on device operation.

System Ground.

Drive Output. Active−high push−pull output.

Positive Power Supply.

Table 2. ABSOLUTE MAXIMUM RATINGS

Rating

Symbol

Value

Unit

Input Voltage Range

−0.3 to 6

Output Voltage Range

OUT

−0.3 to 6 or (V + 0.3), whichever is lower

Input Voltage; PWR_ON, V

−0.3 to 6 or (V + 0.3), whichever is lower

CHG

Maximum Junction Temperature

Output Current; OUT

150

°C

J(max)

OUT

Storage Temperature Range

−65 to 150

STG

ESD Capability, Human Body Model (Note 1)

ESD Capability, Machine Model (Note 2)

ESD

HBM

ESD

150

Lead Temperature Soldering

Reflow (SMD Styles Only), Pb−Free Versions (Note 2)

SLD

260

°C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. This device series incorporates ESD protection and is tested by the following methods:

ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)

ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)

Latch−up Current Maximum Rating: ≤150 mA per JEDEC standard: JESD78

2. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D

Table 3. RECOMMENDED OPERATING CONDITIONS

Rating

Symbol

Min

1.8

Max

Unit

Input Voltage; VDD

5.5

Input Voltage; PWR_ON, V

Output Current; OUT

Ambient Temperature

CHG

°C

OUT

−40

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CAT874

Table 4. ELECTRICAL OPERATING CHARACTERISTICS

(V = 1.8 V to 5.5 V. For typical values T = 25°C, for min/max values T = −40°C to +85°C unless otherwise noted.)

Parameter

Test Conditions

Symbol

Min

Typ

Max

Unit

POWER

Supply Voltage

1.8

5.5

1000

Quiescent Supply Current

Operating Supply Current

PWR_ON = VDD, V

= 0 V

100

CHG

PWR_ON = 0 V, V

= 0 V

CHG

Measured during setup period.

Measurement includes current

through internal 200 kW pull−up

resistor on PWR_ON

LOGIC INPUTS AND OUTPUTS

Input Voltage; HIGH

Input Voltage; LOW

Hysteresis

PWR_ON, V

0.7 x V

CHG

0.25 x V

300

CHG

HYS

250

Input Current V

CHG

= 0 V; V = 5 V

CHG

IL1

(internal pull−down)

Input Current V

= 5 V; V = 5 V

CHG

IH1

(internal pull−down)

Input Current PWR_ON

PWR_ON = 0 V; V = 5 V

(internal 200 kW pull−up resistor)

IL2

PWR_ON = 5 V; V = 5 V

(internal 200 kW pull−up resistor)

300

0.4

IH2

Output Voltage; HIGH

Output Voltage; LOW

TIMING

= −0.1 mA, V = 1.8 V

V − 0.2

SOURCE

= 3 mA, V = 1.8 V

0.1

SINK

Input Delay PWR_ON

T = 25°C

6.56

6.00

8.00

9.44

low_delay

T = −40°C to +85°C

10.00

TEST MODE (V = 5 V, T = 25°C) (Note 3)

Start TEST Window

Test Mode Delay

PWR_ON = 0 V, V

→ 7

250

CHG

cycles, delay measured after 8th

rising edge of V clock pulse

CHG

Test Mode Clock Frequency

Clock applied to V

MHz

CHG

PWR_ON Test Mode Clock Setup

Time

Measured from PWR_ON falling

edge to first falling edge of V

CHG

Input Voltage; LOW

Pulse Width

V , Test Mode Operation

CHG

0.2 x V

IL_TM

500

3. “Test Mode” parameters are not tested in production.

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CAT874

TIMING WAVEFORMS

VBAT

CHG

PWRON

<8s

OUT

VBAT goes

After a H−to−L

transition on V

if VBAT is HIGH,

OUT remains

unchanged

if PWRON is

LOW for less

than 8s, OUT

After a H−to−L

After a L−to−H

transition on

, OUT

LOW & V

CHG

transition on

PWRON, OUT

goes LOW

CHG

is low the circuit

powers down

CHG

remains LOW

goes LOW

if PWRON is

A L−to−H transition

on V if VBAT

is LOW causes a

power−on and OUT

remains LOW

A L−to−H transition

on V if VBAT

is HIGH causes

nothing if OUT is

already LOW

LOW for more

than 8s, OUT

goes HIGH

low_delay

CHG

Figure 3. Timing Waveforms

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CAT874

SYSTEM DESCRIPTION AND APPLICATIONS INFORMATION

General

When PWR_ON goes low, an internal timing cycle is

CAT874 is designed for the manual switching of

initiated. If it goes high before the countdown timer has

concluded its cycle, the timer will reset and will restart from

the beginning when PWR_ON returns to being low.

microprocessors and microcontrollers. To prevent

accidental resets, CAT874 requires PWR_ON input be held

low for a prescribed period before an Active high output is

issued to the system processor.

Output (OUT)

CAT874 provides an active−high push pull output. This

output will sink up to 3 mA.

PWR_ON and V_CHGInputs

PWR_ON and V

PWR_ON must go low and stay low for a predetermined

period (t

output.

are Schmitt trigger CMOS inputs.

CHG

Delay Timer Testing:

A user test mode is provided to reduce the system test time

after the CAT874 is mounted on the board. Instead of

) to generate an Active high on the

LOW_DELAY

waiting t

for the output to go active.

LOW_DELAY

CHG

is a standard CMOS input with internal pull down

The user brings PWR_ON low, and sends seven positive

edges on the V pin in a window of time t . After a delay

resistor 200 kW to keep the input low when charger is not

plugged in and PWR_ON is also a CMOS input with an

internal 200 kW pull−up resistor, thus PWR_ON can be left

floating.

CHG

t , the device output will change state from low to high, and

will return to the low state only when there is a high−to−low

transition on PWR_ON.

PWR_ON

V_CHG

OUT

tST

Figure 4. TOC Mode

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CAT874

APPLICATION INFORMATION

Output Operation

An external resistor 1M should be used OUT, to discharge

the output when both sources turn off.

System with Two Different Power Supply Voltages

When both V

and VBAT are present, the following

Operation with Low VDD Voltage and Brownout

Condition

CHG

application can be adapted. Schottky diodes D1 and D2 can

be used to isolate the two sources. The higher source will

supply the VDD power.

The CAT874 requires a minimum supply voltage VDD of

1.8 V to guarantee the normal operation within the

specification. To prevent small VDD supply glitch, a small

ceramic capacitor can be added between the VDD pin and

GND.

If V

is not present then drop across D2 should be low

CHG

enough to turn off Q1. If both V

the timing waveforms should be used as shown in Figure 4.

and VBAT are present,

CHG

BAT

Battery

0.1 mF

NTLUS3A18P2

PWR_ON

OUT

CAT874

P−MOS

CHG

1 MW

GND

NTLUS3A18P2

P−MOS

DRV

V_SYS

PMU

PWR_ON

Figure 5. Application Schematic in Dual Supply System

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MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

ULLGA6, 1.45x1.0, 0.5P

CASE 613AF−01

ISSUE A

DATE 06 FEB 2008

SCALE 8:1

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED TERMINAL

AND IS MEASURED BETWEEN 0.15 AND

0.30 mm FROM THE TERMINAL TIP.

4. A MAXIMUM OF 0.05 PULL BACK OF THE

PLATED TERMINAL FROM THE EDGE OF THE

PACKAGE IS ALLOWED.

PIN ONE

REFERENCE

MILLIMETERS

DIM MIN

−−−

A1 0.00

MAX

0.40

0.05

0.25

0.10

TOP VIEW

SIDE VIEW

0.15

1.45 BSC

1.00 BSC

0.50 BSC

0.25

0.10

0.35

0.40

0.05

L1 0.30

SEATING

PLANE

MOUNTING FOOTPRINT

SOLDERMASK DEFINED*

0⁵.4^X9

0.30

NOTE 4

5X L

1.24

0.53

6X b

0.50

PITCH

PKG

OUTLINE

0.10

A B

DIMENSIONS: MILLIMETERS

NOTE 3

0.05

BOTTOM VIEW

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON24011D

ULLGA6, 1.45X1.0, 0.5P

PAGE 1 OF 1

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

CAT874-80ULGT3 [ONSEMI]

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