CAT93C46RXI-T2 [ONSEMI]
1 kb Microwire Serial EEPROM; 1 KB Microwire串行EEPROM
| 型号： | CAT93C46RXI-T2 |
| 厂家： | 
ONSEMI |
| 描述： | 1 kb Microwire Serial EEPROM |
| 文件： | 总13页 (文件大小：144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT93C46R
1 kb Microwire Serial
EEPROM
Description
The CAT93C46R is a 1 kb CMOS Serial EEPROM device which is
organized as either 64 registers of 16 bits or 128 registers of 8 bits, as
determined by the state of the ORG pin. The CAT93C46R features
sequential read and self−timed internal write with auto−clear. On−chip
Power−On Reset circuitry protects the internal logic against powering
up in the wrong state.
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In contrast to the CAT93C46, the CAT93C46R features an internal
instruction clock counter which provides improved noise immunity
for Write/Erase commands.
PDIP−8
L SUFFIX
CASE 646AA
TSSOP−8
Y SUFFIX
CASE 948AL
Features
• High Speed Operation: 4 MHz @ 5 V, 2 MHz @ 1.8 V
• 1.8 V to 5.5 V Supply Voltage Range
• Selectable x8 or x16 Memory Organization
• Sequential Read
SOIC−8
V SUFFIX
CASE 751BD
SOIC−8
X SUFFIX
CASE 751BE
TDFN−8
VP2 SUFFIX
CASE 511AK
• Software Write Protection
PIN CONFIGURATIONS
• Power−up Inadvertant Write Protection
• Low Power CMOS Technology
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
V
ORG
GND
DO
CS
SK
DI
NC
1
1
CC
NC
ORG
GND
V
CC
CS
SK
DO
DI
• Industrial Temperature Range
PDIP (L), SOIC (V, X),
TSSOP (Y),
SOIC (W)
• 8−pin PDIP, SOIC, TSSOP and 8−pad TDFN Packages
• This Device is Pb−Free, Halogen Free/BFR Free and RoHS
TDFN (VP2)
(Top Views)
Compliant*
V
CC
PIN FUNCTION
Pin Name
Function
CS
SK
DI
Chip Select
ORG
CS
SK
DI
DO
Clock Input
CAT93C46R
Serial Data Input
Serial Data Output
Power Supply
Ground
DO
V
CC
GND
GND
ORG
NC
Memory Organization
No Connection
Figure 1. Functional Symbol
Note: When the ORG pin is connected to V , the
CC
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
x16 organization is selected. When it is connected
to ground, the x8 pin is selected. If the ORG pin is
left unconnected, then an internal pull−up device will
select the x16 organization.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
©
Semiconductor Components Industries, LLC, 2009
1
Publication Order Number:
October, 2009 − Rev. 7
CAT93C46R/D
CAT93C46R
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter
Value
Units
°C
Storage Temperature
−65 to +150
−0.5 to +6.5
Voltage on Any Pin with Respect to Ground (Note 1)
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than V + 0.5 V. During transitions, the voltage on any pin may
CC
undershoot to no less than −1.5 V or overshoot to no more than V + 1.5 V, for periods of less than 20 ns.
CC
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol
(Note 3)
Parameter
Min
1,000,000
100
Units
Program / Erase Cycles
Years
N
Endurance
END
T
Data Retention
DR
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Block Mode, V = 5 V, T = 25°C
CC
A
Table 3. D.C. OPERATING CHARACTERISTICS (V = +1.8 V to +5.5 V, unless otherwise specified.)
CC
Symbol
Parameter
Test Conditions
Min
Max
Units
I
Power Supply Current (Write)
f
= 1 MHz
CC
1
mA
CC1
SK
V
= 5.0 V
I
Power Supply Current (Read)
f
= 1 MHz
CC
500
10
mA
mA
mA
CC2
SK
V
= 5.0 V
I
I
Power Supply Current (Standby) (x8 Mode)
Power Supply Current (Standby) (x16 Mode)
CS = 0 V
SB1
ORG = GND
CS = 0 V
10
SB2
ORG = Float or V
CC
I
Input Leakage Current
V
= 0 V to V
= 0 V to V
2
2
mA
mA
LI
IN
CC
I
LO
Output Leakage Current (Including ORG pin)
V
OUT
,
CC
CS = 0 V
V
V
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
4.5 V v V < 5.5 V
−0.1
2
0.8
V
V
V
V
V
IL1
CC
4.5 V v V < 5.5 V
V
+ 1
IH1
CC
CC
V
IL2
1.8 V v V < 4.5 V
0
V
x 0.2
CC
CC
V
V
1.8 V v V < 4.5 V
V
x 0.7
V
+ 1
IH2
CC
CC
CC
4.5 V v V < 5.5 V
0.4
OL1
CC
= 2.1 mA
I
OL
V
Output High Voltage
Output Low Voltage
Output High Voltage
4.5 V v V < 5.5 V
2.4
V
V
V
OH1
CC
I
= −400 mA
OH
V
V
1.8 V v V < 4.5 V
0.2
OL2
CC
= 1 mA
I
OL
1.8 V v V < 4.5 V
V
− 0.2
OH2
CC
= −100 mA
CC
I
OH
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2
CAT93C46R
Table 4. PIN CAPACITANCE
Symbol
Test
Conditions
= 0 V
Min
Typ
Max
5
Units
pF
C
OUT
(Note 4)
Output Capacitance (DO)
Input Capacitance (CS, SK, DI, ORG)
V
OUT
C
IN
(Note 4)
V
IN
= 0 V
5
pF
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
Table 5. A.C. CHARACTERISTICS (Note 5)
V
CC
= 1.8 V − 5.5 V
V
CC
= 4.5 V − 5.5 V
Min
50
Max
Min
50
0
Max
Symbol
Parameter
Units
ns
t
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
CSS
t
0
ns
CSH
t
100
100
50
50
ns
DIS
DIH
PD1
PD0
t
ns
t
t
Output Delay to 1
0.25
0.25
100
5
0.1
0.1
100
5
ms
Output Delay to 0
ms
t
(Note 6)
Output Delay to High−Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
ns
HZ
t
ms
ms
EW
t
0.25
0.25
0.25
0.1
0.1
0.1
CSMIN
t
ms
SKHI
t
ms
SKLOW
t
SV
0.25
2
0.1
4
ms
SK
DC
DC
MHz
MAX
5. Test conditions according to “A.C. Test Conditions” table.
6. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
Table 6. POWER−UP TIMING (Notes 4 and 7)
Symbol
Parameter
Max
1
Units
ms
t
Power−up to Read Operation
Power−up to Write Operation
PUR
t
1
ms
PUW
7. t
and t are the delays required from the time V is stable until the specified operation can be initiated.
PUW CC
PUR
Table 7. A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
v 50 ns
0.4 V to 2.4 V
0.8 V, 2.0 V
4.5 V v V v 5.5 V
CC
Timing Reference Voltages
Input Pulse Voltages
4.5 V v V v 5.5 V
CC
0.2 V to 0.7 V
1.8 V v V v 4.5 V
CC
CC
CC
Timing Reference Voltages
Output Load
0.5 V
1.8 V v V v 4.5 V
CC
CC
Current Source I
/I
; C = 100 pF
OLmax OHmax L
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3
CAT93C46R
Table 8. INSTRUCTION SET
Address
Data
x8
x16
x8
x16
Instruction
READ
Start Bit
Opcode
10
Comments
Read Address AN–A0
Clear Address AN–A0
Write Address AN–A0
Write Enable
1
1
1
1
1
1
1
A6−A0
A5−A0
ERASE
WRITE
EWEN
EWDS
ERAL
11
A6−A0
A5−A0
01
A6−A0
A5−A0
D7−D0
D15−D0
00
11XXXXX
00XXXXX
10XXXXX
01XXXXX
11XXXX
00XXXX
10XXXX
01XXXX
00
Write Disable
00
Clear All Addresses
Write All Addresses
WRAL
00
D7−D0
D15−D0
Read
Device Operation
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93C46R will
come out of the high impedance state and, after sending an
initial dummy zero bit, will begin shifting out the data
addressed (MSB first). The output data bits will toggle on
the rising edge of the SK clock and are stable after the
The CAT93C46R is a 1024−bit nonvolatile memory
intended for use with industry standard microprocessors.
The CAT93C46R can be organized as either registers of 16
bits or 8 bits. When organized as X16, seven 9−bit
instructions control the reading, writing and erase
operations of the device. When organized as X8, seven
10−bit instructions control the reading, writing and erase
operations of the device. The CAT93C46R operates on a
single power supply and will generate on chip the high
voltage required during any write operation.
Instructions, addresses, and write data are clocked into the
DI pin on the rising edge of the clock (SK). The DO pin is
normally in a high impedance state except when reading data
from the device, or when checking the ready/busy status
after a write operation.
The ready/busy status can be determined after the start of
a write operation by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that the
device is ready for the next instruction. If necessary, the DO
pin may be placed back into a high impedance state during
chip select by shifting a dummy “1” into the DI pin. The DO
pin will enter the high impedance state on the rising edge of
the clock (SK). Placing the DO pin into the high impedance
state is recommended in applications where the DI pin and
the DO pin are to be tied together to form a common DI/O
pin. The Ready/Busy flag can be disabled only in Ready
state; no change is allowed in Busy state.
specified time delay (t
or t ).
PD0
PD1
Sequential Read
After the 1st data word has been shifted out and CS
remains asserted with the SK clock continuing to toggle, the
CAT93C46R will automatically increment to the next
address and shift out the next data word. As long as CS is
continuously asserted and SK continues to toggle, the device
will keep incrementing to the next address automatically
until it reaches the end of the address space, then loops back
to address 0. In the sequential Read mode, only the initial
data word is preceeded by a dummy zero bit; all subsequent
data words will follow without a dummy zero bit.
Erase/Write Enable and Disable
The CAT93C46R powers up in the write disable state.
Any writing after power−up or after an EWDS (write
disable) instruction must first be preceded by the EWEN
(write enable) instruction. Once the write instruction is
enabled, it will remain enabled until power to the device is
removed, or the EWDS instruction is sent. The EWDS
instruction can be used to disable all CAT93C46R write and
erase instructions, and will prevent any accidental writing or
clearing of the device. Data can be read normally from the
device regardless of the write enable/disable status.
The format for all instructions sent to the device is a
logical “1” start bit, a 2−bit (or 4−bit) opcode, 6−bit address
(an additional bit when organized X8) and for write
operations a 16−bit data field (8−bit for X8 organization).
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CAT93C46R
t
t
t
SKHI
SKLOW
CSH
SK
t
t
DIS
DIH
VALID
VALID
DI
t
CSS
CS
t
t
, t
t
CSMIN
DIS
PD0 PD1
DO
DATA VALID
Figure 2. Synchronous Data Timing
SK
t
CSMIN
CS
DI
STANDBY
A
N
A
N−1
A
0
1
1
0
t
HZ
t
PD0
HIGH−Z
HIGH−Z
DO
0
D
N
D
N−1
D
1
D
0
Figure 3. Read Instruction Timing
SK
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CS
DI
Don’t Care
A
A
A
0
N
N−1
1
0
HIGH−Z
DO
Dummy 0
D
...D
Address + 1 Address + 2 Address + n
...D ...D ...
15
0
or
D ...D
D
15
D
15
D
15
0
0
or
D ...D
or
D ...D
or
D ...
7
0
7
0
7
0
7
Figure 4. Sequential Read Instruction Timing
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CAT93C46R
SK
CS
DI
STANDBY
1
0
0
*
* ENABLE = 11
DISABLE = 00
Figure 5. EWEN/EWDS Instruction Timing
Write
edge of CS will start the self clocking clear cycle of all
memory locations in the device. The clocking of the SK pin
is not necessary after the device has entered the self clocking
mode. The ready/busy status of the CAT93C46R can be
determined by selecting the device and polling the DO pin.
Once cleared, the contents of all memory bits return to a
logical “1” state.
After receiving a WRITE command, address and the data,
the CS (Chip Select) pin must be deselected for a minimum
of t
(See Design Note for details). The falling edge of
CSMIN
CS will start the self clocking clear and data store cycle of
the memory location specified in the instruction. The
clocking of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
CAT93C46R can be determined by selecting the device and
polling the DO pin. Since this device features Auto−Clear
before write, it is NOT necessary to erase a memory location
before it is written into.
Write All
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
t
. The falling edge of CS will start the self clocking
CSMIN
data write to all memory locations in the device. The
clocking of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
CAT93C46R can be determined by selecting the device and
polling the DO pin. It is not necessary for all memory
locations to be cleared before the WRAL command is
executed.
Erase
Upon receiving an ERASE command and address, the CS
(Chip Select) pin must be deasserted for a minimum of
t
after the proper number of clock pulses (See Design
CSMIN
Note). The falling edge of CS will start the self clocking
clear cycle of the selected memory location. The clocking of
the SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the
CAT93C46R can be determined by selecting the device and
polling the DO pin. Once cleared, the content of a cleared
location returns to a logical “1” state.
Design Note
With CAT93C46R, after the last data bit has been
sampled, Chip Select (CS) must be brought Low before the
next rising edge of the clock (SK) in order to start the
self−timed high voltage cycle. This is important because if
the CS is brought low before or after this specific frame
window, the addressed location will not be programmed or
erased.
Erase All
Upon receiving an ERAL command, the CS (Chip Select)
pin must be deselected for a minimum of t
. The falling
CSMIN
SK
t
CS MIN
CS
STATUS
VERIFY
STANDBY
A
N
A
N−1
D
0
A
0
D
N
DI
1
0
1
t
SV
t
HZ
BUSY
DO
HIGH−Z
READY
HIGH−Z
t
EW
Figure 6. Write Instruction Timing
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6
CAT93C46R
SK
STANDBY
CS
DI
STATUS VERIFY
t
CS MIN
A
N
A
N−1
A
0
1
1
1
t
SV
t
HZ
HIGH−Z
BUSY READY
DO
HIGH−Z
t
EW
Figure 7. Erase Instruction Timing
SK
STANDBY
CS
DI
STATUS VERIFY
t
CS MIN
1
0
0
1
0
t
SV
t
HZ
HIGH−Z
BUSY
READY
DO
HIGH−Z
t
EW
Figure 8. ERAL Instruction Timing
SK
CS
DI
STATUS VERIFY
STANDBY
t
CS MIN
D
N
D
0
1
0
0
0
1
t
SV
t
HZ
DO
BUSY
READY
HIGH−Z
t
EW
Figure 9. WRAL Instruction Timing
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CAT93C46R
PACKAGE DIMENSIONS
PDIP−8, 300 mils
CASE 646AA−01
ISSUE A
SYMBOL
MIN
NOM
MAX
A
5.33
A1
A2
b
0.38
2.92
0.36
3.30
0.46
1.52
0.25
9.27
4.95
0.56
1.78
0.36
10.16
b2
c
1.14
0.20
9.02
E1
D
E
E1
e
7.62
6.10
7.87
6.35
8.25
7.11
2.54 BSC
7.87
2.92
10.92
3.80
eB
L
PIN # 1
IDENTIFICATION
3.30
D
TOP VIEW
E
A2
A1
A
c
b2
L
eB
e
b
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.
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CAT93C46R
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
SYMBOL
MIN
NOM
MAX
1.35
A
1.75
A1
b
0.10
0.33
0.19
0.25
0.51
0.25
c
E1
E
D
E
E1
e
4.80
5.80
3.80
5.00
6.20
4.00
1.27 BSC
h
0.25
0.40
0º
0.50
1.27
8º
L
PIN # 1
IDENTIFICATION
θ
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
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CAT93C46R
PACKAGE DIMENSIONS
SOIC−8, 208 mils
CASE 751BE−01
ISSUE O
SYMBOL
MIN
NOM
MAX
A
2.03
A1
b
0.05
0.36
0.19
0.25
0.48
0.25
c
E
E1
D
5.13
7.75
5.13
5.33
8.26
5.38
E
E1
e
1.27 BSC
0.51
0.76
L
0º
8º
θ
PIN#1 IDENTIFICATION
TOP VIEW
D
A
q
L
e
b
c
A1
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with EIAJ EDR-7320.
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CAT93C46R
PACKAGE DIMENSIONS
TSSOP8, 4.4x3
CASE 948AL−01
ISSUE O
b
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
1.20
0.15
1.05
0.30
0.20
3.10
6.50
4.50
0.05
0.80
0.19
0.09
2.90
6.30
4.30
0.90
E
c
E1
D
3.00
6.40
E
E1
e
4.40
0.65 BSC
1.00 REF
L
L1
0.50
0.60
0.75
0º
8º
θ
e
TOP VIEW
D
c
A2
A
q1
A1
L1
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
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CAT93C46R
PACKAGE DIMENSIONS
TDFN8, 2x3
CASE 511AK−01
ISSUE A
D
A
e
b
E2
E
PIN#1
IDENTIFICATION
A1
PIN#1 INDEX AREA
D2
L
TOP VIEW
SIDE VIEW
BOTTOM VIEW
SYMBOL
MIN
NOM
MAX
A
A1
A2
A3
b
0.70
0.00
0.45
0.75
0.02
0.80
0.05
0.65
A2
0.55
0.20 REF
0.25
A3
0.20
1.90
1.30
2.90
1.20
0.30
2.10
1.50
3.10
1.40
D
2.00
FRONT VIEW
D2
E
1.40
3.00
E2
e
1.30
0.50 TYP
0.30
L
0.20
0.40
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MO-229.
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CAT93C46R
Example of Ordering Information (Note 8)
Prefix
Device #
Suffix
CAT
93C46R
V
I
− G
T3
Tape & Reel (Note 14)
Temperature Range
I = Industrial (−40°C to +85°C)
Lead Finish
Company ID
(Optional)
G: NiPdAu
Blank: Matte−Tin
T: Tape & Reel
2: 2,000 Units / Reel (Note 11)
3: 3,000 Units / Reel
Product Number
93C46R
Package
L: PDIP
V: SOIC, JEDEC
W: SOIC, JEDEC
X: SOIC, EIAJ (Note 11)
Y: TSSOP
VP2: TDFN (2 x 3 mm)
ORDERING INFORMATION
Orderable Part Numbers
CAT93C46RLI−G
CAT93C46RVI−GT3
CAT93C46RWI−GT3
CAT93C46RXI−T2
CAT93C46RYI−GT3
CAT93C46RVP2IGT3 (Note 13)
8. The device used in the above example is a CAT93C46RVI−GT3 (SOIC, Industrial Temperature, NiPdAu, Tape & Reel).
9. All packages are RoHS−compliant (Lead−free, Halogen−free).
10.The standard lead finish is NiPdAu.
11. For SOIC, EIAJ (X) package the standard lead finish is Matte−Tin. This package is available in 2,000 pcs/reel, i.e. CAT93C46RXI−T2.
12.For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.
13.Part number is not exactly the same as the “Example of Ordering Information” shown above. For this part number there is NO hyphen in
the orderable part number.
14.For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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