CAT93C46VIGT3 [ONSEMI]
1 Kb Microwire Serial EEPROM; 1 KB Microwire串行EEPROM
| 型号： | CAT93C46VIGT3 |
| 厂家： | 
ONSEMI |
| 描述： | 1 Kb Microwire Serial EEPROM |
| 文件： | 总13页 (文件大小：153K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT93C46
1 Kb Microwire Serial
EEPROM
Description
The CAT93C46 is a 1 Kb Serial EEPROM memory device which is
configured as either 64 registers of 16 bits (ORG pin at V ) or 128
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CC
registers of 8 bits (ORG pin at GND). Each register can be written (or
read) serially by using the DI (or DO) pin. The CAT93C46 features a
self−timed internal write with auto−clear. On−chip Power−On Reset
circuit protects the internal logic against powering up in the wrong
state.
PDIP−8
L SUFFIX
TSSOP−8
Y SUFFIX
Features
CASE 646AA
CASE 948AL
• High Speed Operation: 2 MHz
• 1.8 V to 5.5 V Supply Voltage Range
• Selectable x8 or x16 Memory Organization
• Self−Timed Write Cycle with Auto−Clear
• Software Write Protection
SOIC−8
SOIC−8
X SUFFIX
TDFN−8*
VP2 SUFFIX
CASE 511AK
V, W SUFFIX
CASE 751BD
CASE 751BE
• Power−up Inadvertant Write Protection
• Low Power CMOS Technology
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
PIN CONFIGURATIONS
V
ORG
GND
DO
CS
SK
DI
NC
1
1
CC
NC
ORG
GND
V
CC
CS
SK
• Industrial Temperature Range
• 8−pin PDIP, SOIC, TSSOP and 8−pad TDFN Packages
DO
DI
• This Device is Pb−Free, Halogen Free/BFR Free and RoHS
PDIP (L), SOIC (V, X),
TSSOP (Y), TDFN (VP2)*
(Top View)
SOIC (W)
(Top View)
Compliant*
V
CC
PIN FUNCTION
Pin Name
Function
ORG
CS
SK
CS
SK
DI
Chip Select
DO
CAT93C46
Clock Input
Serial Data Input
Serial Data Output
Power Supply
Ground
DI
DO
V
CC
GND
GND
ORG
NC
Figure 1. Functional Symbol
Memory Organization
No Connection
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Note: When the ORG pin is connected to V , the
CC
x16 organization is selected. When it is connected
to ground, the x8 organization is selected. If the
ORG pin is left unconnected, then an internal pullup
device will select the x16 organization.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
* Not Recommended for New Designs
© Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
October, 2013 − Rev. 10
CAT93C46/D
CAT93C46
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter
Value
Units
°C
Storage Temperature
−65 to +150
−0.5 to +6.5
Voltage on Any Pin with Respect to Ground (Note 1)
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than V + 0.5 V. During transitions, the voltage on any pin may
CC
undershoot to no less than −1.5 V or overshoot to no more than V + 1.5 V, for periods of less than 20 ns.
CC
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol
(Note 3)
Parameter
Min
1,000,000
100
Units
Program / Erase Cycles
Years
N
Endurance
END
T
DR
Data Retention
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Block Mode, V = 5 V, 25°C
CC
Table 3. D.C. OPERATING CHARACTERISTICS (V = +1.8 V to +5.5 V, T = −40°C to +85°C, unless otherwise specified.)
CC
A
Symbol
Parameter
Test Conditions
Min
Max
Units
I
Power Supply Current (Write)
f
= 1 MHz
CC
1
mA
CC1
SK
V
= 5.0 V
I
Power Supply Current (Read)
f
= 1 MHz
CC
500
2
mA
mA
CC2
SK
V
= 5.0 V
I
I
Power Supply Current (Standby) (x8 Mode)
Power Supply Current (Standby) (x16Mode)
V
V
= GND or V
CS = GND
ORG = GND
,
SB1
IN
CC
= GND or V
CS = GND
ORG = Float or V
,
1
mA
SB2
IN
CC
CC
I
Input Leakage Current
Output Leakage Current
V
= GND to V
CC
1
1
mA
mA
LI
IN
I
LO
V
OUT
= GND to V
,
CC
CS = GND
V
V
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
4.5 V v V < 5.5 V
−0.1
2
0.8
V
V
V
V
V
IL1
CC
4.5 V v V < 5.5 V
V
+ 1
IH1
CC
CC
V
IL2
1.8 V v V < 4.5 V
0
V
x 0.2
CC
CC
V
V
1.8 V v V < 4.5 V
V
x 0.7
V
+ 1
IH2
CC
CC
CC
4.5 V v V < 5.5 V
0.4
OL1
CC
= 2.1 mA
I
OL
V
Output High Voltage
Output Low Voltage
Output High Voltage
4.5 V v V < 5.5 V
2.4
V
V
V
OH1
CC
I
= −400 mA
OH
V
V
1.8 V v V < 4.5 V
0.2
OL2
CC
= 1 mA
I
OL
1.8 V v V < 4.5 V
V
− 0.2
OH2
CC
= −100 mA
CC
I
OH
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CAT93C46
Table 4. PIN CAPACITANCE (T = 25°C, f = 1 MHz, V = 5 V)
A
CC
Symbol
(Note 4)
Test
Conditions
= 0 V
Min
Typ
Max
5
Units
pF
C
Output Capacitance (DO)
V
OUT
OUT
C
(Note 4)
Input Capacitance (CS, SK, DI, ORG)
V
IN
= 0 V
5
pF
IN
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
Table 5. A.C. CHARACTERISTICS (V = +1.8 V to +5.5 V, T = −40°C to +85°C, unless otherwise specified.) (Note 5)
CC
A
Limits
Min
50
Max
Symbol
Parameter
Units
ns
t
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
CSS
t
0
ns
CSH
t
100
100
ns
DIS
DIH
PD1
PD0
t
ns
t
t
Output Delay to 1
Output Delay to 0
0.25
0.25
100
5
ms
ms
t
(Note 6)
(Note 7)
Output Delay to High−Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
ns
HZ
t
ms
ms
EW
t
0.25
0.25
0.25
CSMIN
t
ms
SKHI
t
ms
SKLOW
t
SV
0.25
ms
SK
DC
2000
kHz
MAX
5. Test conditions according to “AC Test Conditions” table.
6. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
7. t
is 10 ms max for ERAL and WRAL operations.
EW
Table 6. POWER−UP TIMING (Notes 8 and 9)
Symbol
Parameter
Max
1
Units
ms
t
Power−up to Read Operation
Power−up to Write Operation
PUR
t
1
ms
PUW
8. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
9. t
and t are the delays required from the time V is stable until the specified operation can be initiated.
PUW CC
PUR
Table 7. A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
v 50 ns
0.4 V to 2.4 V
0.8 V, 2.0 V
4.5 V v V v 5.5 V
CC
Timing Reference Voltages
Input Pulse Voltages
4.5 V v V v 5.5 V
CC
0.2 V to 0.7 V
1.8 V v V v 4.5 V
CC
CC
CC
Timing Reference Voltages
Output Load
0.5 V
1.8 V v V v 4.5 V
CC
CC
Current Source I
/I
; C = 100 pF
OLmax OHmax L
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CAT93C46
Device Operation
pin. The Ready/Busy flag can be disabled only in Ready
state; no change is allowed in Busy state.
The format for all instructions sent to the device is a
logical “1” start bit, a 2−bit (or 4−bit) opcode, 6−bit address
(an additional bit when organized X8) and for write
operations a 16−bit data field (8−bit for X8 organization).
The CAT93C46 is a 1024−bit nonvolatile memory
intended for use with industry standard microprocessors.
The CAT93C46 can be organized as either registers of 16
bits or 8 bits. When organized as X16, seven 9−bit
instructions control the reading, writing and erase
operations of the device. When organized as X8, seven
10−bit instructions control the reading, writing and erase
operations of the device. The CAT93C46 operates on a
single power supply and will generate on chip the high
voltage required during any write operation.
Instructions, addresses, and write data are clocked into the
DI pin on the rising edge of the clock (SK). The DO pin is
normally in a high impedance state except when reading data
from the device, or when checking the ready/busy status
during a write operation. The serial communication protocol
follows the timing shown in Figure 2.
The ready/busy status can be determined after the start of
internal write cycle by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that the
device is ready for the next instruction. If necessary, the DO
pin may be placed back into a high impedance state during
chip select by shifting a dummy “1” into the DI pin. The DO
pin will enter the high impedance state on the rising edge of
the clock (SK). Placing the DO pin into the high impedance
state is recommended in applications where the DI pin and
the DO pin are to be tied together to form a common DI/O
Read
Upon receiving a READ command (Figure 3) and an
address (clocked into the DI pin), the DO pin of the
CAT93C46 will come out of the high impedance state and,
after sending an initial dummy zero bit, will begin shifting
out the data addressed (MSB first). The output data bits will
toggle on the rising edge of the SK clock and are stable after
the specified time delay (t
or t ).
PD0
PD1
Erase/Write Enable and Disable
The CAT93C46 powers up in the write disable state. Any
writing after power−up or after an EWDS (write disable)
instruction must first be preceded by the EWEN (write
enable) instruction. Once the write instruction is enabled, it
will remain enabled until power to the device is removed, or
the EWDS instruction is sent. The EWDS instruction can be
used to disable all CAT93C46 write and erase instructions,
and will prevent any accidental writing or clearing of the
device. Data can be read normally from the device
regardless of the write enable/disable status. The EWEN and
EWDS instructions timing is shown in Figure 4.
Table 8. INSTRUCTION SET
Address
Data
x8
x16
x8
x16
Instruction
READ
Start Bit
Opcode
10
Comments
Read Address AN–A0
Clear Address AN–A0
Write Address AN–A0
Write Enable
1
1
1
1
1
1
1
A6−A0
A5−A0
ERASE
WRITE
EWEN
EWDS
ERAL
11
A6−A0
A5−A0
01
A6−A0
A5−A0
D7−D0
D15−D0
00
11XXXXX
00XXXXX
10XXXXX
01XXXXX
11XXXX
00XXXX
10XXXX
01XXXX
00
Write Disable
00
Clear All Addresses
Write All Addresses
WRAL
00
D7−D0
D15−D0
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CAT93C46
t
t
t
SKHI
SKLOW
CSH
SK
t
t
DIS
DIH
VALID
VALID
DI
t
CSS
CS
t
t
, t
t
CSMIN
DIS
PD0 PD1
DO
DATA VALID
Figure 2. Synchronous Data Timing
SK
t
CSMIN
CS
DI
STANDBY
A
N
A
N−1
A
0
1
1
0
t
HZ
t
PD0
HIGH−Z
HIGH−Z
DO
0
D
D
D
D
0
N
N−1
1
Figure 3. Read Instruction Timing
SK
STANDBY
CS
DI
1
0
0
*
* ENABLE = 11
DISABLE = 00
Figure 4. EWEN/EWDS Instruction Timing
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CAT93C46
Write
Erase All
After receiving a WRITE command (Figure 5), address
and the data, the CS (Chip Select) pin must be deselected for
a minimum of t . The falling edge of CS will start the
Upon receiving an ERAL command (Figure 7), the CS
(Chip Select) pin must be deselected for a minimum of
t
. The falling edge of CS will start the self clocking
CSMIN
CSMIN
self clocking for auto−clear and data store cycles on the
memory location specified in the instruction. The clocking
of the SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the CAT93C46
can be determined by selecting the device and polling the
DO pin. Since this device features Auto−Clear before write,
it is NOT necessary to erase a memory location before it is
written into.
clear cycle of all memory locations in the device. The
clocking of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
CAT93C46 can be determined by selecting the device and
polling the DO pin. Once cleared, the contents of all memory
bits return to a logical “1” state.
Write All
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
Erase
Upon receiving an ERASE command and address, the CS
(Chip Select) pin must be de−asserted for a minimum of
t
(Figure 8). The falling edge of CS will start the self
CSMIN
clocking data write to all memory locations in the device.
The clocking of the SK pin is not necessary after the device
has entered the self clocking mode. The ready/busy status of
the CAT93C46 can be determined by selecting the device
and polling the DO pin. It is not necessary for all memory
locations to be cleared before the WRAL command is
executed.
t
(Figure 6). The falling edge of CS will start the self
CSMIN
clocking clear cycle of the selected memory location. The
clocking of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
CAT93C46 can be determined by selecting the device and
polling the DO pin. Once cleared, the content of a cleared
location returns to a logical “1” state.
SK
CS
t
CSMIN
STANDBY
STATUS
VERIFY
A
N
A
N−1
A
0
D
D
0
N
DI
1
0
1
t
SV
t
HZ
HIGH−Z
DO
READY
HIGH−Z
BUSY
EW
t
Figure 5. Write Instruction Timing
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CAT93C46
SK
STANDBY
CS
DI
STATUS VERIFY
t
CS MIN
A
N
A
N−1
A
0
1
1
1
t
SV
t
HZ
HIGH−Z
DO
BUSY READY
HIGH−Z
t
EW
Figure 6. Erase Instruction Timing
SK
CS
DI
STATUS VERIFY
STANDBY
t
CS MIN
1
0
0
1
0
t
SV
t
HZ
HIGH−Z
DO
BUSY
READY
HIGH−Z
t
EW
Figure 7. ERAL Instruction Timing
SK
CS
DI
STATUS VERIFY
STANDBY
t
CSMIN
1
0
0
0
1
D
D
0
N
t
SV
t
HZ
BUSY
READY
DO
HIGH−Z
t
EW
Figure 8. WRAL Instruction Timing
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CAT93C46
PACKAGE DIMENSIONS
PDIP−8, 300 mils
CASE 646AA−01
ISSUE A
SYMBOL
MIN
NOM
MAX
A
5.33
A1
A2
b
0.38
2.92
0.36
3.30
0.46
1.52
0.25
9.27
4.95
0.56
1.78
0.36
10.16
b2
c
1.14
0.20
9.02
E1
D
E
E1
e
7.62
6.10
7.87
6.35
8.25
7.11
2.54 BSC
7.87
2.92
10.92
3.80
eB
L
PIN # 1
IDENTIFICATION
3.30
D
TOP VIEW
E
A2
A1
A
c
b2
L
eB
e
b
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.
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CAT93C46
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
SYMBOL
MIN
NOM
MAX
1.35
A
A1
b
1.75
0.25
0.51
0.25
0.10
0.33
0.19
c
E1
E
D
E
E1
e
4.80
5.80
3.80
5.00
6.20
4.00
1.27 BSC
h
0.25
0.40
0º
0.50
1.27
8º
L
PIN # 1
IDENTIFICATION
θ
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
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CAT93C46
PACKAGE DIMENSIONS
SOIC−8, 208 mils
CASE 751BE−01
ISSUE O
SYMBOL
MIN
NOM
MAX
A
A1
b
2.03
0.25
0.48
0.25
5.33
8.26
5.38
0.05
0.36
0.19
5.13
7.75
5.13
c
E
E1
D
E
E1
e
1.27 BSC
0.51
0.76
L
0º
8º
θ
PIN#1 IDENTIFICATION
TOP VIEW
D
A
q
e
b
L
c
A1
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with EIAJ EDR-7320.
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CAT93C46
PACKAGE DIMENSIONS
TSSOP8, 4.4x3
CASE 948AL−01
ISSUE O
b
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
1.20
0.15
1.05
0.30
0.20
3.10
6.50
4.50
0.05
0.80
0.19
0.09
2.90
6.30
4.30
0.90
E
c
E1
D
3.00
6.40
E
E1
e
4.40
0.65 BSC
1.00 REF
0.60
L
L1
0.50
0.75
0º
8º
θ
e
TOP VIEW
D
c
A2
A
q1
A1
L1
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
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CAT93C46
PACKAGE DIMENSIONS
TDFN8, 2x3
CASE 511AK−01
ISSUE A
D
A
e
b
E2
E
PIN#1
IDENTIFICATION
A1
PIN#1 INDEX AREA
D2
L
TOP VIEW
SIDE VIEW
BOTTOM VIEW
SYMBOL
MIN
0.70
0.00
0.45
NOM
MAX
0.80
0.05
0.65
A
A1
A2
A3
b
0.75
0.02
A2
0.55
0.20 REF
0.25
A3
0.20
1.90
1.30
2.90
1.20
0.30
2.10
1.50
3.10
1.40
D
2.00
FRONT VIEW
D2
E
1.40
3.00
E2
e
1.30
0.50 TYP
0.30
L
0.20
0.40
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MO-229.
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CAT93C46
Ordering Information
Specific
Device
marking
Lead
Finish
OPN
Pkg Type
Temperature Range
Shipping
CAT93C46LI−G
93C46L
93C46V
93C46V
EK
PDIP−8
I = Industrial
NiPdAu
NiPdAu
NiPdAu
NiPdAu
NiPdAu
NiPdAu
Matte−Tin
Matte−Tin
NiPdAu
NiPdAu
Tube, 50 Units / Tube
(−40°C to +85°C)
CAT93C46VI−G
SOIC−8, JEDEC
SOIC−8, JEDEC
TDFN−8
I = Industrial
(−40°C to +85°C)
Tube, 100 Units / Tube
Tape & Reel, 3000 Units / Reel
Tape & Reel, 3000 Units / Reel
Tube, 100 Units / Tube
CAT93C46VI−GT3
I = Industrial
(−40°C to +85°C)
CAT93C46VP2I−GT3
(Note 10)
I = Industrial
(−40°C to +85°C)
CAT93C46WI−G
CAT93C46WI−GT3
CAT93C46XI
93C46W
93C46W
93C46X
93C46X
M46
SOIC−8, JEDEC
SOIC−8, JEDEC
SOIC−8, EIAJ
SOIC−8, EIAJ
TSSOP−8
I = Industrial
(−40°C to +85°C)
I = Industrial
(−40°C to +85°C)
Tape & Reel, 3000 Units / Reel
Tube, 94 Units / Tube
I = Industrial
(−40°C to +85°C)
CAT93C46XI−T2
CAT93C46YI−G
CAT93C46YI−GT3
I = Industrial
(−40°C to +85°C)
Tape & Reel, 2000 Units / Reel
Tube, 100 Units / Tube
I = Industrial
(−40°C to +85°C)
M46
TSSOP−8
I = Industrial
(−40°C to +85°C)
Tape & Reel, 3000 Units / Reel
10.Not recommended for new designs.
11. All packages are RoHS−compliant (Lead−free, Halogen−free).
12.The standard lead finish is NiPdAu.
13.For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.
14.For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
15.For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device
Nomenclature document, TND310/D, available at www.onsemi.com
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
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