CAT93C76PA-1.8REVA [ONSEMI]
IC 512 X 16 MICROWIRE BUS SERIAL EEPROM, PDIP8, PLASTIC, DIP-8, Programmable ROM;
| 型号： | CAT93C76PA-1.8REVA |
| 厂家： | 
ONSEMI |
| 描述： | IC 512 X 16 MICROWIRE BUS SERIAL EEPROM, PDIP8, PLASTIC, DIP-8, Programmable ROM 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总12页 (文件大小：155K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT93C76
8-Kb Microwire Serial
EEPROM
Description
The CAT93C76 is an 8−Kb Serial EEPROM memory device which
is configured as either registers of 16 bits (ORG pin at V or Not
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CC
Connected) or 8 bits (ORG pin at GND). Each register can be written
(or read) serially by using the DI (or DO) pin. The CAT93C76 is
manufactured using ON Semiconductor’s advanced CMOS EEPROM
floating gate technology. The device is designed to endure 1,000,000
program/erase cycles and has a data retention of 100 years. The device
is available in 8−pin PDIP, SOIC, TSSOP and 8−pad TDFN packages.
SOIC−8
V SUFFIX
CASE 751BD
TDFN−8
ZD4 SUFFIX
CASE 511AL
Features
• High Speed Operation: 3 MHz @ V ≥ 2.5 V
CC
• Low Power CMOS Technology
• 1.8 to 5.5 Volt Operation
• Selectable x8 or x16 Memory Organization
• Self−timed Write Cycle with Auto−clear
• Software Write Protection
• Power−up Inadvertant Write Protection
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
• Industrial and Extended Temperature Ranges
• Sequential Read
PDIP−8
L SUFFIX
CASE 646AA
TSSOP−8
Y SUFFIX
CASE 948AL
PIN CONFIGURATION
1
V
CC
CS
SK
NC
DI
DO
ORG
GND
PDIP (L), SOIC (V),
TSSOP (Y), TDFN (ZD4)
• “Green” Package Option Available
• This Device is Pb−Free, Halogen Free/BFR Free and RoHS
Compliant
PIN FUNCTION
Pin Name
Function
Chip Select
V
CC
CS
SK
DI
Serial Clock Input
Serial Data Input
Serial Data Output
Power Supply
Ground
ORG
CS
DI
DO
DO
V
CC
SK
GND
ORG
NC
Memory Organization
No Connection
GND
Figure 1. Functional Symbol
NOTE: When the ORG pin is connected to V , the x16 organization is selected.
CC
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
When it is connected to ground, the x8 organization is selected. If the ORG pin
is left unconnected, then an internal pull−up device will select the x16 organization.
© Semiconductor Components Industries, LLC, 2009
1
Publication Order Number:
August, 2009 − Rev. 3
CAT93C76/D
CAT93C76
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
°C
Temperature Under Bias
−55 to +125
−65 to +150
Storage Temperature
°C
Voltage on any Pin with Respect to Ground (Note 1)
−2.0 to +V +2.0
V
CC
V
with Respect to Ground
−2.0 to +7.0
300
V
CC
Lead Soldering Temperature (10 seconds)
Output Short Circuit Current (Note 2)
°C
100
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The minimum DC input voltage is −0.5 V. During transitions, inputs may undershoot to −2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5 V, which may overshoot to V +2.0 V for periods of less than 20 ns.
CC
CC
2. Output shorted for no more than one second.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol
(Note 3)
Parameter
Endurance
Reference Test Method
MIL−STD−883, Test Method 1033
MIL−STD−883, Test Method 1008
MIL−STD−883, Test Method 3015
JEDEC Standard 17
Min
1,000,000
100
Units
Cycles / Byte
Years
N
END
T
(Note 3)
(Note 3)
Data Retention
ESD Susceptibility
Latch−Up
DR
V
2,000
100
V
ZAP
I
(Notes 3, 4)
mA
LTH
3. These parameters are tested initially and after a design or process change that affects the parameter.
4. Latch−up protection is provided for stresses up to 100 mA on I/O pins from −1 V to V + 1 V.
CC
Table 3. D.C. OPERATING CHARACTERISTICS (V = +1.8 V to +5.5 V unless otherwise specified.)
CC
Symbol
Parameter
Test Conditions
= 1 MHz, V = 5.0 V
Min
Typ
1
Max
Units
mA
mA
I
I
Power Supply Current (Write)
Power Supply Current (Read)
f
f
3
CC1
CC2
SK
CC
= 1 MHz, V = 5.0 V
300
2
500
10
SK
CC
I
Power Supply Current
(Standby) (x8 Mode)
CS = 0 V, ORG = GND
mA
SB1
I
Power Supply Current
(Standby) (x16 Mode)
CS = 0 V, ORG = Float or V
0 (Note 5)
10
mA
SB2
CC
I
Input Leakage Current
Output Leakage Current
ORG Pin Leakage Current
Input Low Voltage
V
= 0 V to V
CC
0 (Note 5)
0 (Note 5)
1
10
10
10
0.8
mA
mA
mA
V
LI
IN
I
LO
V
= 0 V to V , CS = 0 V
OUT CC
I
ORG = GND or ORG = V
LORG
CC
V
IL1
4.5 V v V v 5.5 V
−0.1
2
CC
V
IH1
Input High Voltage
4.5 V v V v 5.5 V
V + 1
CC
V
CC
V
IL2
Input Low Voltage
1.8 V v V < 4.5 V
0
V x 0.2
CC
V
CC
V
IH2
Input High Voltage
1.8 V v V < 4.5 V
V
V
x 0.7
V + 1
CC
V
CC
CC
V
V
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
4.5 V v V v 5.5 V, I = 2.1 mA
0.4
V
OL1
CC
OL
4.5 V v V v 5.5 V, I = −400 mA
2.4
V
OH1
CC
OH
V
OL2
OH2
1.8 V v V < 4.5 V, I = 100 mA
0.1
V
CC
OL
V
1.8 V v V < 4.5 V, I = −100 mA
− 0.2
CC
V
CC
OH
5. 0 mA is defined as less than 900 nA.
Table 4. PIN CAPACITANCE (Note 3)
Symbol
Test
Output Capacitance (DO)
Input Capacitance (CS, SK, DI, ORG)
Conditions
Min
Typ
Max
5
Units
C
V
OUT
= 0 V
pF
pF
OUT
C
V
IN
= 0 V
5
IN
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CAT93C76
Table 5. INSTRUCTION SET (Note 6)
Address
Data
Start
Bit
x8
x16
x8
x16
Instruction
READ
Opcode
10
Comments
Read Address AN– A0
Clear Address AN– A0
Write Address AN– A0
Write Enable
1
A10−A0
A9−A0
ERASE
WRITE
EWEN
EWDS
ERAL
1
11
A10−A0
A9−A0
1
01
A10−A0
A9−A0
D7−D0
D15−D0
D15−D0
1
00
11XXXXXXXXX
00XXXXXXXXX
10XXXXXXXXX
01XXXXXXXXX
11XXXXXXXX
00XXXXXXXX
10XXXXXXXX
01XXXXXXXX
1
00
Write Disable
1
00
Clear All Addresses
Write All Addresses
WRAL
1
00
D7−D0
6. Address bit A10 for the 1,024x8 org. and A9 for the 512x16 org. are “don’t care” bits, but must be kept at either a “1” or “0” for READ, WRITE
and ERASE commands.
Table 6. A.C. CHARACTERISTICS
Limits
V
CC
= 1.8 V − 2.5 V
V
CC
= 2.5 V − 5.5 V
Min
100
0
Max
Min
50
0
Max
Symbol
Parameter
CS Setup Time
Test Conditions
Units
ns
t
CSS
t
CS Hold Time
ns
CSH
t
DI Setup Time
100
100
50
50
ns
DIS
DIH
PD1
PD0
t
DI Hold Time
ns
t
t
Output Delay to 1
250
250
150
5
150
150
100
5
ns
Output Delay to 0
C = 100 pF (Note 7)
L
ns
t
(Note 8)
Output Delay to High−Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
ns
HZ
t
ms
ns
EW
t
200
250
250
150
150
150
CSMIN
t
ns
SKHI
t
ns
SKLOW
t
250
100
ns
SV
SK
DC
1000
DC
3000
kHz
MAX
7. The input levels and timing reference points are shown in the “AC Test Conditions” table.
8. These parameters are tested initially and after a design or process change that affects the parameter.
Table 7. POWER−UP TIMING (Notes 8, 9)
Symbol
Parameter
Max
Units
t
Power−up to Read Operation
Power−up to Write Operation
1
1
ms
ms
PUR
t
PUW
9. t
and t are the delays required from the time V is stable until the specified operation can be initiated.
PUW CC
PUR
Table 8. A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
≤ 50 ns
0.4 V to 2.4 V
0.8 V, 2.0 V
4.5 V v V v 5.5 V
CC
Timing Reference Voltages
Input Pulse Voltages
4.5 V v V v 5.5 V
CC
0.2 V to 0.7 V
1.8 V v V v 4.5 V
CC
CC
CC
Timing Reference Voltages
0.5 V
1.8 V v V v 4.5 V
CC
CC
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CAT93C76
Read
Device Operation
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93C76 will
come out of the high impedance state and, after sending an
initial dummy zero bit, will begin shifting out the data
addressed (MSB first). The output data bits will toggle on
the rising edge of the SK clock and are stable after the
The CAT93C76 is a 8192−bit nonvolatile memory
intended for use with industry standard microprocessors.
The CAT93C76 can be organized as either registers of 16
bits or 8 bits. When organized as X16, seven 13−bit
instructions control the read, write and erase operations of
the device. When organized as X8, seven 14−bit instructions
control the read, write and erase operations of the device.
The CAT93C76 operates on a single power supply and will
generate on chip, the high voltage required during any write
operation.
Instructions, addresses, and write data are clocked into the
DI pin on the rising edge of the clock (SK). The DO pin is
normally in a high impedance state except when reading data
from the device, or when checking the ready/busy status
after a write operation.
The ready/busy status can be determined after the start of
a write operation by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that the
device is ready for the next instruction. If necessary, the DO
pin may be placed back into a high impedance state during
chip select by shifting a dummy “1” into the DI pin. The DO
pin will enter the high impedance state on the falling edge of
the clock (SK). Placing the DO pin into the high impedance
state is recommended in applications where the DI pin and
the DO pin are to be tied together to form a common DI/O
pin.
The format for all instructions sent to the device is a
logical “1” start bit, a 2−bit (or 4−bit) opcode, 10−bit address
(an additional bit when organized X8) and for write
operations a 16−bit data field (8−bit for X8 organizations).
The most significant bit of the address is “don’t care” but it
must be present.
specified time delay (t
or t ).
PD0
PD1
For the CAT93C76, after the initial data word has been
shifted out and CS remains asserted with the SK clock
continuing to toggle, the device will automatically
increment to the next address and shift out the next data word
in a sequential READ mode. As long as CS is continuously
asserted and SK continues to toggle, the device will keep
incrementing to the next address automatically until it
reaches the end of the address space, then loops back to
address 0. In the sequential READ mode, only the initial data
word is preceeded by a dummy zero bit. All subsequent data
words will follow without a dummy zero bit.
Write
After receiving a WRITE command, address and the data,
the CS (Chip Select) pin must be deselected for a minimum
of t
. The falling edge of CS will start the self clocking
CSMIN
clear and data store cycle of the memory location specified
in the instruction. The clocking of the SK pin is not
necessary after the device has entered the self clocking
mode. The ready/busy status of the CAT93C76 can be
determined by selecting the device and polling the DO pin.
Since this device features Auto−Clear before write, it is
NOT necessary to erase a memory location before it is
written into.
t
t
SKLOW
t
SKHI
CSH
SK
t
t
DIH
DIS
VALID
VALID
DI
t
CSS
CS
t
t
, t
t
DIS
PD0 PD1
CSMN
DO
DATA VALID
Figure 2. Synchronous Data Timing
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CAT93C76
SK
CS
DI
Don’t Care
A
N
A
N−1
A
0
1
1
0
HIGH−Z
DO
Dummy 0
D
. . . D
Address + 1 Address + 2 Address + n
15
0
or
D . . . D
D
. . . D
D
. . . D
D
or
D . . .
. . .
15
0
15
0
15
or
D . . . D
or
D . . . D
7
0
7
0
7
0
7
Figure 3. READ Instruction Timing
SK
t
CSMIN
STANDBY
CS
DI
STATUS
VERIFY
A
N
A
N−1
A
0
D
D
0
N
1
0
1
t
SV
t
HZ
BUSY
HIGH−Z
DO
READY
HIGH−Z
t
EW
Figure 4. WRITE Instruction Timing
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CAT93C76
Erase
determined by selecting the device and polling the DO pin.
Upon receiving an ERASE command and address, the CS
(Chip Select) pin must be deasserted for a minimum of
. The falling edge of CS will start the self clocking
clear cycle of the selected memory location. The clocking of
the SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the CAT93C76
can be determined by selecting the device and polling the
DO pin. Once cleared, the content of a cleared location
returns to a logical “1” state.
Once cleared, the contents of all memory bits return to a
logical “1” state.
t
CSMIN
Write All
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
t
. The falling edge of CS will start the self clocking
CSMIN
data write to all memory locations in the device. The
clocking of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
CAT93C76 can be determined by selecting the device and
polling the DO pin. It is not necessary for all memory
locations to be cleared before the WRAL command is
executed.
Erase/Write Enable and Disable
The CAT93C76 powers up in the write disable state. Any
writing after power-up or after an EWDS (write disable)
instruction must first be preceded by the EWEN (write
enable) instruction. Once the write instruction is enabled, it
will remain enabled until power to the device is removed, or
the EWDS instruction is sent. The EWDS instruction can be
used to disable all CAT93C76 write and clear instructions,
and will prevent any accidental writing or clearing of the
device. Data can be read normally from the device
regardless of the write enable/disable status.
Note 1: After the last data bit has been sampled, Chip Select
(CS) must be brought Low before the next rising edge of the
clock (SK) in order to start the self-timed high voltage cycle.
This is important because if CS is brought low before or after
this specific frame window, the addressed location will not
be programmed or erased.
Power-On Reset (POR)
The CAT93C76 incorporates Power-On Reset (POR)
circuitry which protects the device against malfunctioning
Erase All
Upon receiving an ERAL command, the CS (Chip Select)
pin must be deselected for a minimum of t
edge of CS will start the self clocking clear cycle of all
memory locations in the device. The clocking of the SK pin
is not necessary after the device has entered the self clocking
mode. The ready/busy status of the CAT93C76 can be
. The falling
CSMIN
while V
voltage.
is lower than the recommended operating
CC
The device will power up into a read-only state and will
power-down into a reset state when V crosses the POR
level of ~1.3 V.
CC
SK
CS
STANDBY
STATUS VERIFY
t
CS
A
N
A
N−1
A
0
DI
1
1
1
t
SV
t
HZ
HIGH−Z
BUSY
DO
READY
HIGH−Z
t
EW
Figure 5. ERASE Instruction Timing
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CAT93C76
SK
STANDBY
CS
DI
1
0
0
*
* ENABLE = 11
DISABLE = 00
Figure 6. EWEN/EWDS Instruction Timing
SK
CS
DI
STATUS VERIFY
STANDBY
t
CS
1
0
0
1
0
t
SV
t
HZ
HIGH−Z
BUSY
DO
READY
HIGH−Z
t
EW
Figure 7. ERAL Instruction Timing
SK
CS
DI
STATUS VERIFY STANDBY
t
CSMIN
1
0
0
0
1
D
D
0
N
t
SV
t
HZ
BUSY
DO
READY
HIGH−Z
t
EW
Figure 8. WRAL Instruction Timing
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CAT93C76
PACKAGE DIMENSIONS
PDIP−8, 300 mils
CASE 646AA−01
ISSUE A
SYMBOL
MIN
NOM
MAX
A
5.33
A1
A2
b
0.38
2.92
0.36
3.30
0.46
1.52
0.25
9.27
4.95
0.56
1.78
0.36
10.16
b2
c
1.14
0.20
9.02
E1
D
E
E1
e
7.62
6.10
7.87
6.35
8.25
7.11
2.54 BSC
7.87
2.92
10.92
3.80
eB
L
PIN # 1
IDENTIFICATION
3.30
D
TOP VIEW
E
A2
A1
A
c
b2
L
eB
e
b
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.
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CAT93C76
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
SYMBOL
MIN
NOM
MAX
1.35
A
A1
b
1.75
0.25
0.51
0.25
0.10
0.33
0.19
c
E1
E
D
E
E1
e
4.80
5.80
3.80
5.00
6.20
4.00
1.27 BSC
h
0.25
0.40
0º
0.50
1.27
8º
L
PIN # 1
IDENTIFICATION
θ
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
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CAT93C76
PACKAGE DIMENSIONS
TSSOP8, 4.4x3
CASE 948AL−01
ISSUE O
b
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
1.20
0.15
1.05
0.30
0.20
3.10
6.50
4.50
0.05
0.80
0.19
0.09
2.90
6.30
4.30
0.90
E
c
E1
D
3.00
6.40
E
E1
e
4.40
0.65 BSC
1.00 REF
0.60
L
L1
0.50
0.75
0º
8º
θ
e
TOP VIEW
D
c
A2
A
q1
A1
L1
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
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CAT93C76
PACKAGE DIMENSIONS
TDFN8, 3x3
CASE 511AL−01
ISSUE A
D
A
e
b
L
E
E2
PIN#1 ID
PIN#1 INDEX AREA
A1
D2
TOP VIEW
SIDE VIEW
BOTTOM VIEW
SYMBOL
MIN
0.70
0.00
NOM
MAX
0.80
0.05
A
A1
A3
b
0.75
0.02
0.20 REF
0.30
0.23
2.90
2.20
2.90
1.40
0.37
3.10
2.50
3.10
1.80
A
A3
D
3.00
D2
E
−−−
A1
3.00
FRONT VIEW
E2
e
−−−
0.65 TYP
0.30
L
0.20
0.40
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MO-229.
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CAT93C76
Example of Ordering Information
Prefix
Device #
Suffix
CAT
93C76
V
I
− G
T3
Temperature Range
Lead Finish
Tape & Reel (Note 14)
Company ID
G: NiPdAu
Blank: Matte−Tin
T: Tape & Reel
2: 2,000 Units / Reel (Note 15)
3: 3,000 Units / Reel
I = Industrial (−40°C to +85°C)
E = Extended (−40°C to +125°C)
Product Number
93C76
Package
L: PDIP
V: SOIC, JEDEC
Y: TSSOP
ZD4: TDFN (3 x 3 mm)
10.All packages are RoHS−compliant (Lead−free, Halogen−free).
11. The standard lead finish is NiPdAu.
12.The device used in the above example is a CAT93C76VI−GT3 (SOIC, Industrial Temperature, NiPdAu, Tape & Reel, 3,000 / Reel).
13.Product die revision letter is marked on top of the package as a suffix to the production date code (e.g., AYWWA). For additional information,
please contact your ON Semiconductor sales office.
14.For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
15.For TDFN 3 x 3 mm package Tape and Reel = 2,000 / Reel, all others = 3,000 / Reel.
16.For additional package and temperature options, please contact your nearest ON Semiconductor sales office.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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CAT93C76/D
相关型号：
CAT93C76PE-1.8REVA
IC 512 X 16 MICROWIRE BUS SERIAL EEPROM, PDIP8, PLASTIC, DIP-8, Programmable ROM
ONSEMI
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