CAT9532HV6I-T2
更新时间：2024-09-18 14:10:56
品牌：ONSEMI
描述：16 I/O, PIA-GENERAL PURPOSE, QCC24, 4 X 4 MM, ROHS COMPLIANT, MO-220, TQFN-24
概述
规格参数
数据手册CAT9532HV6I-T2 概述
16 I/O, PIA-GENERAL PURPOSE, QCC24, 4 X 4 MM, ROHS COMPLIANT, MO-220, TQFN-24 并行 IO 端口
CAT9532HV6I-T2 规格参数
| 是否无铅： | 不含铅 | 是否Rohs认证： | 符合 |
| 生命周期： | Obsolete | 零件包装代码： | QFN |
| 包装说明： | HVQCCN, | 针数： | 24 |
| Reach Compliance Code： | compliant | ECCN代码： | EAR99 |
| HTS代码： | 8542.39.00.01 | 风险等级： | 5.6 |
| Is Samacsys： | N | JESD-30 代码： | S-XQCC-N24 |
| JESD-609代码： | e3 | 长度： | 4 mm |
| 湿度敏感等级： | 1 | I/O 线路数量： | 16 |
| 端口数量： | 1 | 端子数量： | 24 |
| 最高工作温度： | 85 °C | 最低工作温度： | -40 °C |
| 封装主体材料： | UNSPECIFIED | 封装代码： | HVQCCN |
| 封装形状： | SQUARE | 封装形式： | CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE |
| 峰值回流温度（摄氏度）： | 260 | 认证状态： | Not Qualified |
| 座面最大高度： | 0.8 mm | 最大供电电压： | 5.5 V |
| 最小供电电压： | 2.3 V | 表面贴装： | YES |
| 技术： | CMOS | 温度等级： | INDUSTRIAL |
| 端子面层： | Tin (Sn) | 端子形式： | NO LEAD |
| 端子节距： | 0.5 mm | 端子位置： | QUAD |
| 处于峰值回流温度下的最长时间： | 40 | 宽度： | 4 mm |
| uPs/uCs/外围集成电路类型： | PARALLEL IO PORT, GENERAL PURPOSE | Base Number Matches： | 1 |
CAT9532HV6I-T2 数据手册
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PDF下载CAT9532
16-bit Programmable LED
Dimmer with I2C Interface
Description
The CAT9532 is a CMOS device that provides 16−bit parallel
input/output port expander optimized for LED dimming control. The
CAT9532 outputs can drive directly 16 LEDs in parallel. Each
individual LED may be turned ON, OFF, or blinking at one of two
programmable rates. The device provides a simple solution for
dimming LEDs in 256 brightness steps for backlight and color mixing
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2
applications. The CAT9532 is suitable in I C and SMBus compatible
applications where it is necessary to limit the bus traffic or free−up the
bus master’s timer.
SOIC−24
W SUFFIX
CASE 751BK
The CAT9532 contains an internal oscillator and two PWM signals
that drive the LED outputs. The user can program the period and duty
cycle for each individual PWM signal. After the initial set−up
command to program the Blink Rate 1 and Blink Rate 2 (frequency
and duty cycle), only one command from the bus master is required to
turn each individual open drain output ON, OFF, or cycle at Blink
Rate 1 or Blink Rate 2. Each open drain LED output can provide a
maximum output current of 25 mA. The total current sunk by all I/Os
must not exceed 200 mA.
TSSOP−24
Y SUFFIX
CASE 948AR
Features
• 16 LED Drivers with Dimming Control
• 256 Brightness Steps
• 16 Open Drain Outputs Drive 25 mA Each
• 2 Selectable Programmable Blink Rates:
– Frequency: 0.593 Hz to 152 Hz
– Duty Cycle: 0% to 99.6%
TQFN−24
HV6 SUFFIX
CASE 510AG
• I/Os can be Used as GPIOs
2
• 400 kHz I C Bus Compatible
• 2.3 V to 5.5 V Operation
TQFN−24
HT6 SUFFIX
CASE 510AN
• 5 V Tolerant I/Os
• Active Low Reset Input
• 24−Lead SOIC, TSSOP and 24−pad TQFN (4 x 4 mm) Packages
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 16 of this data sheet.
Compliant
Applications
• Backlighting
• RGB Color Mixing
• Sensors Control
• Power Switches, Push−buttons
• Alarm Systems
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
June, 2011 − Rev. 0
CAT9532/D
CAT9532
MARKING DIAGRAMS
A3B
CAT9532WI
3YMXXX
HHHH
AXXX
YMCC
AB
CAT9532YI
3YMXXX
TQFN (HV6, HT6)
SOIC (W)
TSSOP (Y)
HHHH = Device Code
A
3
B
= Assembly Location
= Matte−Tin Lead Finish
= Product Revision (Fixed as “B”)
= LAAC = HV6
= MAAC = HT6
A
B
= Assembly Location
= Product Revision (Fixed as “B”)
A
XXX
= Assembly Location
= Last Three Digits of
= Assembly Lot Number
= Production Year (Last Digit)
CAT9532W = Device Code
CAT9532Y = Device Code
I
3
Y
M
XXX
I
= Industrial Temperature Range
= Temperature Range
Y
M
= Production Year (Last Digit)
= Production Month (1−9, O, N, D)
= Matte-Tin Lead Finish
= Production Year (Last Digit)
= Production Month (1−9, O, N, D)
= Last Three Digits of
Y
M
CC
= Production Month (1−9, O, N, D) XXXX = Last Four Digits of
= Country Code
= TH = Thailand
= MY = Malaysia
= Assembly Lot Number
= Assembly Lot Number
A0
1
V
CC
A1
A2
SDA
1
LED0
LED1
LED2
LED3
LED4
LED5
RESET
SCL
LED15
LED14
LED13
LED12
LED11
LED0
LED1
LED2
LED3
LED4
LED5
LED6
LED7
RESET
LED15
LED14
LED13
LED12
LED11
LED10
LED9
V
SS
LED8
SOIC (W), TSSOP (Y)
(Top View)
TQFN (HV6, HT6)
(Top View)
Figure 1. Pin Configurations
5 V
5 V
RS0
RS1
RS11
3 x 10 kW
V
CC
LED0
LED1
SDA
SCL
SDA
SCL
RESET
RESET
2
CAT9532
I C/SMBus
Master
LED11
A2
A1
A0
LED12
LED15
GPIOs
V
SS
Figure 2. Typical Application Circuit
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CAT9532
Table 1. PIN DESCRIPTION
DIP / SOIC / TSSOP
TQFN
22
Pin Name
Function
1
2
A0
Address Input 0
Address Input 1
Address Input 2
23
A1
A2
3
24
4−11
12
1−8
9
LED0 − LED7
LED Driver Output 0 to 7, I/O Port 0 to 7
V
SS
Ground
13−20
21
10−17
18
LED8 − LED15
RESET
SCL
LED Driver Output 8 to 15, I/O Port 8 to 15
Reset Input
Serial Clock
Serial Data
Power Supply
22
19
23
20
SDA
24
21
V
CC
A2 A1 A0
V
CC
POWER ON
RESET
INPUT
REGISTER
RESET
2
LED SELECT (LSx)
REGISTER
INPUT
FILTERS
SCL
SDA
I C BUS
CONTROL
LEDx
BLINK 0
PRESCALER 0
REGISTER
PWM 0
REGISTER
CONTROL
LOGIC
OSCILLATOR
BLINK 1
PRESCALER 1
REGISTER
PWM 1
REGISTER
V
SS
CAT9532
Note: Only one I/O is shown for clarity
Figure 3. Block Diagram
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
−2.0 to +7.0
−0.5 to +5.5
25
Units
V
with Respect to Ground
V
V
CC
Voltage on Any Pin with Respect to Ground
DC Current on I/Os
mA
mA
W
Supply Current
200
Package Power Dissipation Capability (T = 25°C)
1.0
A
Junction Temperature
+150
°C
°C
°C
°C
Storage Temperature
−65 to +150
300
Lead Soldering Temperature (10 seconds)
Operating Ambient Temperature
−40 to +85
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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CAT9532
Table 3. D.C. OPERATING CHARACTERISTICS (V = 2.3 to 5.5 V, V = 0 V; T = −40°C to +85°C, unless otherwise specified)
CC
SS
A
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
SUPPLIES
V
Supply Voltage
2.3
−
5.5
V
CC
CC
I
Supply Current
Operating mode; V = 5.5 V; no load;
SCL
−
250
550
mA
CC
f
= 100 kHz
I
Standby Current
Standby mode; V = 5.5 V; no load;
−
−
−
2.1
−
5.0
2
mA
mA
V
stb
CC
V = V or V , f = 0 kHz
I
SS
CC SCL
ΔI
Additional Standby Current
Power−on Reset Voltage
Standby mode; V = 5.5 V; every
CC
stb
LED I/O = V = 4.3 V, f
= 0 kHz
IN
SCL
V
(Note 1)
V
I
= 3.3 V, No load;
1.5
2.2
POR
CC
V = V or V
CC
SS
SCL, SDA, RESET
V
(Note 2)
(Note 2)
Low Level Input Voltage
High Level Input Voltage
Low Level Output Current
Leakage Current
−0.5
−
−
−
−
−
−
0.3 V
V
V
IL
CC
V
IH
0.7 V
5.5
−
CC
I
OL
V
= 0.4 V
3
−1
−
mA
mA
pF
pF
OL
I
IL
V = V = V
I
+1
6
CC
SS
SS
C (Note 3)
Input Capacitance
V = V
I
I
C
(Note 3)
Output Capacitance
V
O
= V
SS
−
8
O
A0, A1, A2
V
(Note 2)
(Note 2)
Low Level Input Voltage
High Level Input Voltage
Input Leakage Current
−0.5
2.0
−1
−
−
−
0.8
5.5
1
V
V
IL
V
IH
I
IL
mA
I/Os
V
(Note 2)
(Note 2)
(Note 4)
Low Level Input Voltage
High Level Input Voltage
Low Level Output Current
−0.5
2.0
9
−
−
−
−
−
−
−
−
−
−
0.8
5.5
−
V
V
IL
IH
V
I
OL
V
OL
V
OL
V
OL
V
OL
V
OL
V
OL
V
CC
= 0.4 V; V = 2.3 V
mA
CC
= 0.4 V; V = 3.0 V
12
15
15
20
25
−1
−
−
CC
= 0.4 V; V = 5.0 V
−
CC
= 0.7 V; V = 2.3 V
−
CC
= 0.7 V; V = 3.0 V
−
CC
= 0.7 V; V = 5.0 V
−
CC
I
IL
Input Leakage Current
= 3.6 V; V = V or V
CC
1
mA
I
SS
C
(Note 3)
Input/Output Capacitance
8
pF
I/O
1. V must be lowered to 0.2 V in order to reset the device.
DD
2. V min and V max are reference values only and are not tested.
IL
IH
3. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
4. The output current must be limited to a maximum 25 mA per each I/O; the total current sunk by all I/O must be limited to 200 mA (or 100 mA
for eight I/Os)
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CAT9532
Table 4. A.C. CHARACTERISTICS (V = 2.3 V to 5.5 V, T = −40°C to +85°C, unless otherwise specified) (Note 5)
CC
A
2
2
Standard I C
Min Max
Fast I C
Max
Min
Symbol
Parameter
Units
kHz
ms
F
SCL
Clock Frequency
100
400
t
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
START Condition Setup Time
Data In Hold Time
4
4.7
4
0.6
1.3
0.6
0.6
0
HD:STA
t
ms
LOW
t
ms
HIGH
t
4.7
0
ms
SU:STA
HD:DAT
t
ms
t
Data In Setup Time
250
100
ns
SU:DAT
t
(Note 6)
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Condition Setup Time
1000
300
300
300
ns
R
t (Note 6)
ns
F
t
4
0.6
1.3
ms
SU:STO
t
(Note 6)
Bus Free Time Between STOP and START
SCL Low to Data Out Valid
4.7
ms
BUF
t
3.5
0.9
100
200
ms
AA
DH
t
Data Out Hold Time
100
50
ns
T (Note 6)
Noise Pulse Filtered at SCL and SDA Inputs
100
ns
i
PORT TIMING
t
t
Output Data Valid
ns
ns
ms
PV
PS
PH
Input Data Setup Time
Input Data Hold Time
100
1
t
RESET
t
(Note 6)
Reset Pulse Width
Reset Recovery Time
Time to Reset
10
0
ns
ns
ns
W
t
REC
t
(Note 7)
400
RESET
5. Test conditions according to “AC Test Conditions” table.
6. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
7. The full delay to reset the part will be the sum of t
and the RC time constant of the SDA line.
RESET
Table 5. AC TEST CONDITIONS
Input Pulse Voltage
0.2 V to 0.8 V
CC
CC
Input Rise and Fall Times
Input Reference Voltage
Output Reference Voltage
Output Load
≤5 ns
0.3 V , 0.7 V
CC
CC
0.5 V
CC
Current source: I = 3 mA; 400 pF for f
= 400 kHz
OL
SCL(max)
t
t
F
t
R
HIGH
t
t
LOW
LOW
SCL
t
t
HD:DAT
SU:STA
t
t
t
SU:STO
SU:DAT
HD:STA
SDA IN
t
BUF
t
t
AA
DH
SDA OUT
Figure 4. 2−Wire Serial Interface Timing
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CAT9532
Pin Description
receiver, but the Master device controls which mode is
activated.
SCL: Serial Clock
I2C Bus Protocol
The features of the I C bus protocol are defined as
follows:
The serial clock input clocks all data transferred into or out
of the device. The SCL line requires a pull−up resistor if it
is driven by an open drain output.
2
1. Data transfer may be initiated only when the bus is
not busy.
SDA: Serial Data/Address
The bidirectional serial data/address pin is used to transfer
all data into and out of the device. The SDA pin is an open
drain output and can be wire−ORed with other open drain or
open collector outputs. A pull−up resistor must be connected
2. During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock line is high
will be interpreted as a START or STOP condition
(Figure 5).
from SDA line to V
.
CC
LED0 to LED15: LED Driver Outputs / General Purpose
I/Os
START and STOP Conditions
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of SDA
when SCL is HIGH. The CAT9532 monitors the SDA and
SCL lines and will not respond until this condition is met.
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
The pins are open drain outputs used to drive directly
LEDs. Any of these pins can be programmed to drive the
LED ON, OFF, Blink Rate1 or Blink Rate2. When not used
for controlling the LEDs, these pins may be used as general
purpose parallel input/output.
RESET: External Reset Input
Active low Reset input is used to initialize the CAT9532
internal registers and the I C state machine. The internal
Device Addressing
2
After the bus Master sends a START condition, a slave
address byte is required to enable the CAT9532 for a read or
write operation. The four most significant bits of the slave
address are fixed as binary 1100 (Figure 6). The CAT9532
uses the next three bits as address bits.
registers are held in their default state while Reset input is
active. An external pull−up resistor of maximum 25 kW is
required when this pin is not actively driven.
Functional Description
The address bits A2, A1 and A0 are used to select which
device is accessed from maximum eight devices on the same
bus. These bits must compare to their hardwired input pins.
The 8th bit following the 7−bit slave address is the R/W bit
that specifies whether a read or write operation is to be
performed. When this bit is set to “1”, a read operation is
initiated, and when set to “0”, a write operation is selected.
Following the START condition and the slave address byte,
the CAT9532 monitors the bus and responds with an
acknowledge (on the SDA line) when its address matches the
transmitted slave address. The CAT9532 then performs a read
or a write operation depending on the state of the R/W bit.
The CAT9532 is a 16−bit I/O bus expander that provides
a programmable LED dimmer, controlled through an I C
2
compatible serial interface.
The CAT9532 supports the I C Bus data transmission
2
protocol. This Inter−Integrated Circuit Bus protocol defines
any device that sends data to the bus to be a transmitter and
any device receiving data to be a receiver. The transfer is
controlled by the Master device which generates the serial
clock and all START and STOP conditions for bus access.
The CAT9532 operates as a Slave device. Both the Master
device and Slave device can operate as either transmitter or
SDA
SCL
START CONDITION
STOP CONDITION
Figure 5. Start/Stop Timing
SLAVE ADDRESS
1
1
0
0
A2 A1 A0
R/W
FIXED
PROGRAMMABLE
HARDWARE SELECTABLE
Figure 6. CAT9532 Slave Address
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CAT9532
Acknowledge
a stop condition to return the CAT9532 to the standby power
mode and place the device in a known state.
After a successful data transfer, each receiving device is
required to generate an acknowledge. The acknowledging
device pulls down the SDA line during the ninth clock cycle,
signaling that it received the 8 bits of data. The SDA line
remains stable LOW during the HIGH period of the
acknowledge related clock pulse (Figure 7).
The CAT9532 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation, it
responds with an acknowledge after receiving each 8− bit
byte.
Registers and Bus Transactions
After the successful acknowledgement of the slave
address, the bus master will send a command byte to the
CAT9532 which will be stored in the Control Register. The
format of the Control Register is shown in Figure 8.
The Control Register acts as a pointer to determine which
register will be written or read. The four least significant
bits, B0, B1, B2, B3, are used to select which internal
register is accessed, according to the Table 6.
If the auto increment flag (AI) is set, the four least
significant bits of the Control Register are automatically
incremented after a read or write operation. This allows the
user to access the CAT9532 internal registers sequentially.
The content of these bits will rollover to “0000” after the last
register is accessed.
When the CAT9532 begins a READ mode it transmits 8
bits of data, releases the SDA line, and monitors the line for
an acknowledge. Once it receives this acknowledge, the
CAT9532 will continue to transmit data. If no acknowledge
is sent by the Master, the device terminates data transmission
and waits for a STOP condition. The master must then issue
Table 6. INTERNAL REGISTERS SELECTION
B3
0
B2
0
B1
0
B0
0
Register Name
INPUT0
INPUT1
PSC0
Type
Register Function
Input Register 0
READ
0
0
0
1
READ
Input Register 1
0
0
1
0
READ/WRITE
READ/WRITE
READ/WRITE
READ/WRITE
READ/WRITE
READ/WRITE
READ/WRITE
READ/WRITE
Frequency Prescaler 0
PWM Register 0
0
0
1
1
PWM0
PSC1
0
1
0
0
Frequency Prescaler 1
PWM Register 1
0
1
0
1
PWM1
LS0
0
1
1
0
LED 0−3 Selector
LED 4−7 Selector
LED 8−11 Selector
LED 12−15 Selector
0
1
1
1
LS1
1
0
0
0
LS2
1
0
0
1
LS3
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 7. Acknowledge Timing
0
0
0
AI
B3
B2
B1
B0
REGISTER ADDRESS
RESET STATE: 00h
AUTO−INCREMENT FLAG
Figure 8. Control Register
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CAT9532
The Input Register 0 and Input Register 1 reflect the incoming logic levels of the I/O pins, regardless of whether the pin is
defined as an input or an output. These registers are read only ports. Writes to the input registers will be acknowledged but will
have no effect.
Table 7. INPUT REGISTER 0 AND INPUT REGISTER 1
INPUT0
LED 7
LED 6
LED 5
LED 4
LED 3
LED 2
LED 1
LED 0
bit
default
INPUT1
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
LED 15
LED 14
LED 13
LED 12
LED 11
LED 10
LED 9
LED 8
bit
7
6
5
4
3
2
1
0
default
X
X
X
X
X
X
X
X
The Frequency Prescaler 0 and Frequency Prescaler 1
registers (PSC0, PSC1) are used to program the period of the
pulse width modulated signals BLINK0 and BLINK1
respectively:
Every LED driver output can be programmed to one of
four states, LED OFF, LED ON, LED blinks at BLINK0 rate
and LED blinks at BLINK1 rate using the LED Selector
Registers (Table 10).
T_BLINK0 = (PSC0 + 1) / 152;
T_BLINK1 = (PSC1 + 1) / 152
Table 10. LED SELECTOR REGISTERS
LS0
Table 8. FREQUENCY PRESCALER 0 AND
FREQUENCY PRESCALER 1 REGISTERS
LED 3
LED 2
LED 1
LED 0
bit
default
LS1
7
6
0
5
4
0
3
2
0
1
0
0
PSC0
0
0
0
0
bit
default
PSC1
bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
LED 7
LED 6
LED 5
LED 4
bit
default
LS2
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
default
The PWM Register 0 and PWM Register 1 (PWM0,
PWM1) are used to program the duty cycle of BLINK0 and
BLINK1 respectively:
LED 11
LED 10
LED 9
LED 8
bit
default
LS3
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Duty Cycle_BLINK0 = PWM0 / 256;
Duty Cycle_BLINK1 = PWM1 / 256
After writing to the PWM0/1 register an 8−bit internal
counter starts to count from 0 to 255. The outputs are low (LED
on) when the counter value is less than the value programmed
into PWM register. The LED is off when the counter value is
higher than the value written into PWM register.
LED 15
LED 14
LED 13
LED 12
bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
default
The LED output (LED0 to LED15) is set by the 2 bits
value from the corresponding LSx Register (x = 0 to 3):
Table 9. PWM REGISTER 0 AND PWM REGISTER 1
PWM0
00 = LED Output set Hi−Z (LED Off – Default)
01 = LED Output set LOW (LED On)
10 = LED Output blinks at BLINK0 Rate
11 = LED Output blinks at BLINK1 Rate
bit
default
PWM1
bit
7
1
6
0
5
0
4
0
3
0
2
0
1
0
0
0
7
1
6
0
5
0
4
0
3
0
2
0
1
0
0
0
default
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8
CAT9532
Write Operations
LED Pins Used as General Purpose I/O
Data is transmitted to the CAT9532 registers using the
write sequence shown in Figure 9.
Any LED pins not used to drive LEDs can be used as
general purpose input/output, GPIO.
If the AI bit from the command byte is set to “1”, the
CAT9532 internal registers can be written sequentially.
After sending data to one register, the next data byte will be
sent to the next register sequentially addressed.
When used as input, the user should program the
corresponding LED pin to Hi−Z (“00” for the LSx register
bits). The pin state can be read via the Input Register
according to the sequence shown in Figure 11.
For use as output, an external pull−up resistor should be
connected to the pin. The value of the pull−up resistor is
calculated according to the DC operating characteristics. To
set the LED output high, the user has to program the output
Hi−Z writing “00” into the corresponding LED Selector
(LSx) register bits. The output pin is set low when the LED
output is programmed low through the LSx register bits
(“01” in LSx register bits).
Read Operations
The CAT9532 registers are read according to the timing
diagrams shown in Figure 10 and Figure 11. Data from the
register, defined by the command byte, will be sent serially
on the SDA line.
After the first byte is read, additional data bytes may be
read when the auto−increment flag, AI, is set. The additional
data byte will reflect the data read from the next register
sequentially addressed by the (B3 B2 B1 B0) bits of the
command byte.
When reading Input Port Registers (Figure 11), data is
clocked into the register on the failing edge of the
acknowledge clock pulse. The transfer is stopped when the
master will not acknowledge the data byte received and issue
the STOP condition.
SCL
1
2
3
4
5
6
7
8
9
Command Byte
Data To Register 1
DATA 1
Data To Register 2
Slave Address
SDA
A
S
1
1
0
0 A2 A1 A0 0
R/W
0
0
0 AI B3 B2 B1 B0 A
A
A
1.0
Acknowledge
From Slave
Acknowledge
From Slave
Acknowledge
From Slave
Start Condition
WRITE TO REGISTER
DATA OUT FROM PORT
t
pv
Figure 9. Write to Register Timing Diagram
Acknowledge From Master
Data From Register
Acknowledge
From Slave
Acknowledge
From Slave
Acknowledge
From Slave
Slave Address
Slave Address
MSB
S
1
1
0
0 A2 A1 A0 0
R/W
A
A
S
1
1
0
0 A2 A1 A0 1
A
LSB A
COMMAND BYTE
DATA
First Byte
R/W
At This Moment Master−Transmitter
Becomes Master−receiver and
Slave−Receiver Becomes
Slave−Transmitter
Auto−increment
Register Address
If AI = 1
No Acknowledge
From Master
Data From Register
NA P
LSB
DATA
MSB
Note: Transfer can be stopped at any time by a STOP condition.
Last Byte
Figure 10. Read from Register Timing Diagram
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9
CAT9532
External Reset Operation
The CAT9532 registers and the I C state machine are
initialized to their default state when the RESET input is
Power−On Reset Operation
The CAT9532 incorporates Power−On Reset (POR)
circuitry which protects the internal logic against powering
2
held low for a minimum of t . The external Reset timing is
up in the wrong state. The device is in a reset state for V
W
CC
shown in Figure 12.
less than the internal POR threshold level (V ). When
POR
V
CC
exceeds the V
level, the reset state is released and
POR
the CAT9532 internal state machine and registers are
initialized to their default state.
Slave Address
A2 A1 A0
Data From Port
DATA 1
Data From Port
DATA 4
SDA
A
NA P
S
1
1
0
0
A
Acknowledge
From Slave
Acknowledge
From Master
No Acknowledge
From Master
Start Condition
R/W
Stop
Condition
READ FROM
PORT
DATA INTO
PORT
DATA 1
DATA 2
DATA 3
DATA 4
t
ph
t
ps
Figure 11. Read Input Port Register Timing Diagram
START
30%
ACK OR READ CYCLE
SCL
SDA
RESET
LEDx
t
RESET
50%
50%
50%
t
W
t
REC
t
RESET
50%
LED OFF
Figure 12. RESET Timing Diagram
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10
CAT9532
Application Information
Programming Example
2
Command Description
I C Data
1
START
The following programming sequence is an example how
to set:
2
3
4
Send Slave address, A0−A2 = low
C0h
12h
00h
Command Byte: AI=”1”; PSC0 Addr
• LED0 to LED3: ON
Set Blink 1 at 152Hz, T_Blink1 = 1/152
Write PSC0 = 0
• LED4 to LED7: Dimming at 30% brightness; Blink 1:
152 Hz, duty cycle 30%
5
6
7
Set PWM0 duty cycle to 30%
PWM0 / 256 = 0.3; Write PWM0=77
4Dh
4Bh
80h
• LED8 to LED11: Blink at 2 Hz with 50% duty cycle
(Blink 2)
• LED12 to LED15: OFF
Set Blink 2 at 2Hz, T_Blink1 = 1/2
Write PSC1 = 75
Set PWM1 duty cycle to 50%
PWM1 / 256 = 0.5; Write PWM1=128
8
Write LS0: LED0 to LED3 = ON
Write LS1: LED4 to LED7 at Blink1
Write LS2: LED8 to LED11 at Blink2
Write LS3: LED12 to LED15 = OFF
STOP
55h
AAh
FFh
00h
9
10
11
12
5 V
5 V
V
CC
10 kW (x 3)
LED0
LED1
LED2
LED3
LED4
LED5
LED6
LED7
LED8
LED9
LED10
LED11
LED12
LED13
LED14
LED15
V
CC
SDA
SDA
SCL
SCL
RESET
GND
RESET
CAT9532
2
I C/SMBus MASTER
A2
A1
A0
V
SS
GPIOs
Note: LED0 to LED11 are used as LED drivers and LED12 to LED15 are used as regular GPIOs.
Figure 13. Typical Application
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11
CAT9532
PACKAGE DIMENSIONS
SOIC−24, 300 mils
CASE 751BK−01
ISSUE O
SYMBOL
MIN
NOM
MAX
2.65
0.30
2.55
0.51
0.33
15.40
10.51
7.60
2.35
A
A1
A2
b
0.10
2.05
0.31
0.20
15.20
10.11
7.34
E1
E
c
D
E
E1
e
1.27 BSC
h
0.25
0.40
0º
0.75
1.27
8º
L
b
e
θ
PIN#1 IDENTIFICATION
5º
15º
θ1
TOP VIEW
h
D
h
q1
A2
q
A
q1
L
c
A1
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-013.
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12
CAT9532
PACKAGE DIMENSIONS
TSSOP24, 4.4x7.8
CASE 948AR−01
ISSUE A
b
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
1.20
0.15
1.05
0.30
0.20
7.90
6.55
4.50
0.05
0.80
0.19
0.09
7.70
6.25
4.30
c
E1
E
D
7.80
6.40
E
E1
e
4.40
0.65 BSC
0.60
L
0.50
0.70
L1
1.00 REF
0º
8º
θ
e
TOP VIEW
D
c
A2
A
θ1
L
A1
L1
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
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13
CAT9532
PACKAGE DIMENSIONS
TQFN24, 4x4
CASE 510AG−01
ISSUE B
A
D
DETAIL A
E
E2
PIN#1 ID
D2
PIN#1 INDEX AREA
A1
TOP VIEW
SIDE VIEW
BOTTOM VIEW
SYMBOL
MIN
0.70
0.00
NOM
MAX
0.80
0.05
b
e
A
A1
A3
b
0.75
L
0.20 REF
0.25
0.20
2.70
2.70
0.30
0.30
2.90
2.90
0.50
D
4.00 BSC
2.80
DETAIL A
D2
E
4.00 BSC
2.80
E2
e
0.50 BSC
L
A
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MO-220.
(3) Minimum space between leads and flag cannot be smaller than 0.15 mm.
A3
FRONT VIEW
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14
CAT9532
PACKAGE DIMENSIONS
TQFN24, 4x4 TA
CASE 510AN−01
ISSUE O
A
D
DETAIL A
E
E2
PIN#1 ID
D2
PIN#1 INDEX AREA
A1
TOP VIEW
SIDE VIEW
BOTTOM VIEW
SYMBOL
MIN
0.70
0.00
NOM
MAX
0.80
0.05
b
e
A
A1
A3
b
0.75
−
0.20 REF
0.25
L
0.20
2.00
2.00
0.30
0.30
2.20
2.20
0.50
D
4.00 BSC
−
DETAIL A
D2
E
4.00 BSC
−
E2
e
0.50 BSC
−
L
A
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MO-220.
(3) Minimum space between leads and flag cannot be smaller than 0.15 mm.
A3
FRONT VIEW
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15
CAT9532
Example of Ordering Information (Notes 8 to 12)
Prefix
Device #
Suffix
CAT
9532
W
I
T1
Business
Group ID
Product Number
Temperature Range
I = Industrial (−40°C to +85°C)
Tape & Reel
T: Tape & Reel
9532
1: 1,000 / Reel (SOIC Only)
2: 2,000 / Reel
Package
W: SOIC, JEDEC
Y: TSSOP
HV6: TQFN
HT6: TQFN
Lead Finish
G: NiPdAu
Blank: Matte−Tin
8. All packages are RoHS−compliant (Lead−free, Halogen−free).
9. The standard plated finish is Matte−Tin for SOIC and TSSOP packages. The standard plated finish is NiPdAu for TQFN package.
10.The device used in the above example is a CAT9532WI−T1 (SOIC, Industrial Temperature, Matte−Tin, Tape & Reel, 1,000/Reel).
11. For additional temperature options, please contact your nearest ON Semiconductor Sales office.
12.For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Table 11. ORDERING PART NUMBER
Part Number
CAT9532WI
Package
SOIC
Lead Finish
Matte−Tin
Matte−Tin
Matte−Tin
Matte−Tin
NiPdAu
CAT9532WI−T1
CAT9532YI
SOIC
TSSOP
TSSOP
TQFN
TQFN
TQFN
TQFN
CAT9532YI−T2
CAT9532HV6I−G
CAT9532HV6I−GT2
CAT9532HT6I−G
CAT9532HT6I−GT2
NiPdAu
NiPdAu
NiPdAu
2
ON Semiconductor is licensed by Philips Corporation to carry the I C Protocol.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
CAT9532/D
CAT9532HV6I-T2 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| CAT9532WI | ONSEMI | 16-bit Programmable LED Dimmer with I2C Interface | 获取价格 |
|
| CAT9532WI-T1 | ONSEMI | 16-bit Programmable LED Dimmer with I2C Interface | 获取价格 |
|
| CAT9532YI | ONSEMI | 16-bit Programmable LED Dimmer with I2C Interface | 获取价格 |
|
| CAT9532YI-T2 | ONSEMI | 16-bit Programmable LED Dimmer with I2C Interface | 获取价格 |
|
| CAT9534 | CATALYST | Catalyst Semiconductor | 获取价格 |
|
| CAT9534 | ONSEMI | 8-bit I²C and SMBus I/O Port with Interrupt | 获取价格 |
|
| CAT9534HV4I-G | ONSEMI | 8-bit I²C and SMBus I/O Port with Interrupt | 获取价格 |
|
| CAT9534HV4I-GT2 | ONSEMI | 8-bit I²C and SMBus I/O Port with Interrupt | 获取价格 |
|
| CAT9534WI-G | ONSEMI | 8-bit I²C and SMBus I/O Port with Interrupt | 获取价格 |
|
| CAT9534WI-GT2 | ONSEMI | 8-bit I²C and SMBus I/O Port with Interrupt | 获取价格 |
|
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