CAV25320VE-GT3 [ONSEMI]
EEPROM 串行 32-Kb SPI - 汽车级;
| 型号： | CAV25320VE-GT3 |
| 厂家： | 
ONSEMI |
| 描述： | EEPROM 串行 32-Kb SPI - 汽车级 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总13页 (文件大小：310K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAV25320
EEPROM Serial 32-Kb SPI
Automotive Grade 1
Description
The CAV25320 is a EEPROM Serial 32−Kb SPI Automotive
Grade 1 device internally organized as 4096x8 bits. This features a
32−byte page write buffer and supports the Serial Peripheral Interface
(SPI) protocol. The device is enabled through a Chip Select (CS)
input. In addition, the required bus signals are clock input (SCK), data
input (SI) and data output (SO) lines. The HOLD input may be used to
pause any serial communication with the CAV25320 device. The
device features software and hardware write protection, including
partial as well as full array protection.
www.onsemi.com
SOIC−8
V SUFFIX
CASE 751BD
Features
• Automotive AEC−Q100 Grade 1 (−40°C to +125°C) Qualified
• 10 MHz SPI Compatible
TSSOP−8
Y SUFFIX
CASE 948AL
• 2.5 V to 5.5 V Supply Voltage Range
• SPI Modes (0,0) & (1,1)
• 32−byte Page Write Buffer
• Self−timed Write Cycle
PIN CONFIGURATION
• Hardware and Software Protection
• CAV Prefix for Automotive and Other Applications Requiring Site
1
V
CS
CC
and Change Control
SO
HOLD
WP
SCK
• Block Write Protection
V
SS
SI
− Protect 1/4, 1/2 or Entire EEPROM Array
• Low Power CMOS Technology
SOIC (V), TSSOP (Y)
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
PIN FUNCTION
Pin Name
CS
Function
Chip Select
• SOIC and TSSOP 8−lead Packages
• This Device is Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
SO
Serial Data Output
Write Protect
Ground
WP
V
CC
V
SS
SI
Serial Data Input
Serial Clock
SI
SCK
CS
CAV25320
SO
HOLD
Hold Transmission Input
Power Supply
WP
HOLD
SCK
V
CC
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
V
SS
Figure 1. Functional Symbol
© Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
April, 2019 − Rev. 3
CAV25320/D
CAV25320
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
°C
Operating Temperature
−45 to +130
−65 to +150
−0.5 to +6.5
Storage Temperature
°C
Voltage on any Pin with Respect to Ground (Note 1)
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than V + 0.5 V. During transitions, the voltage on any pin may
CC
undershoot to no less than −1.5 V or overshoot to no more than V + 1.5 V, for periods of less than 20 ns.
CC
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol
(Note 3)
Parameter
Min
1,000,000
100
Units
Program / Erase Cycles
Years
N
Endurance
END
T
DR
Data Retention
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, V = 5 V, 25°C.
CC
Table 3. D.C. OPERATING CHARACTERISTICS (V = 2.5 V to 5.5 V, T = −40°C to +125°C, unless otherwise specified.)
CC
A
Symbol
Parameter
Supply Current (Read Mode)
Supply Current (Write Mode)
Standby Current
Test Conditions
Min
Max
Units
mA
I
Read, V = 5.5 V, 10 MHz, SO open
2
3
4
CCR
CC
I
Write, V = 5.5 V, CS = V
mA
CCW
CC
CC
CC
I
V
= GND or V , CS = V
,
,
mA
SB1
IN
CC
WP = V , V = 5.5 V
CC
CC
I
Standby Current
V
IN
= GND or V , CS = V
6
mA
SB2
CC
CC
WP = GND, V = 5.5 V
CC
I
Input Leakage Current
Output Leakage Current
V
= GND or V
CC
−2
−1
2
2
mA
mA
L
IN
I
CS = V
,
LO
CC
V
OUT
= GND or V
CC
V
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
−0.5
0.3 V
V
V
V
V
IL
CC
V
IH
0.7 V
V
CC
+ 0.5
CC
V
I
I
= 3.0 mA
0.4
OL1
OH1
OL
V
= −1.6 mA
V
− 0.8 V
OH
CC
Table 4. PIN CAPACITANCE (Note 2) (T = 25°C, f = 1.0 MHz, V = +5.0 V)
A
CC
Symbol
Test
Conditions
Min
Typ
Max
8
Units
pF
C
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI, WP, HOLD)
V
OUT
= 0 V
OUT
C
V
IN
= 0 V
8
pF
IN
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2
CAV25320
Table 5. A.C. CHARACTERISTICS (T = −40°C to +125°C) (Note 4)
A
V
CC
= 2.5 V − 5.5 V
Min
DC
10
Max
Symbol
Parameter
Units
MHz
ns
f
Clock Frequency
Data Setup Time
Data Hold Time
SCK High Time
SCK Low Time
10
SCK
t
SU
t
H
10
ns
t
40
ns
WH
t
40
ns
WL
t
HOLD to Output Low Z
Input Rise Time
25
2
ns
LZ
t
RI
(Note 5)
(Note 5)
ms
t
FI
Input Fall Time
2
ms
t
HOLD Setup Time
HOLD Hold Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD to Output High Z
CS High Time
0
ns
HD
CD
t
10
ns
t
V
35
ns
t
0
ns
HO
t
20
25
ns
DIS
t
ns
HZ
CS
t
40
30
30
20
20
10
10
ns
t
CS Setup Time
ns
CSS
CSH
CNS
CNH
WPS
WPH
t
t
CS Hold Time
ns
CS Inactive Setup Time
CS Inactive Hold Time
WP Setup Time
ns
t
ns
t
ns
t
WP Hold Time
ns
t
(Note 6)
Write Cycle Time
5
ms
WC
4. AC Test Conditions:
Input Pulse Voltages: 0.3 V to 0.7 V
CC
CC
Input rise and fall times: ≤ 10 ns
Input and output reference voltages: 0.5 V
CC
Output load: current source I
/I
; C = 30 pF
OL max OH max L
5. This parameter is tested initially and after a design or process change that affects the parameter.
6. t is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
WC
Table 6. POWER−UP TIMING (Note 7)
Symbol
Parameter
Max
1
Units
ms
t
Power−up to Read Operation
Power−up to Write Operation
PUR
t
1
ms
PUW
7. t
and t
are the delays required from the time V is stable until the specified operation can be initiated.
PUR
PUW
CC
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3
CAV25320
Pin Description
pausing, the HOLD input should be tied to V , either
CC
directly or through a resistor.
SI: The serial data input pin accepts op−codes, addresses
and data. In SPI modes (0,0) and (1,1) input data is latched
on the rising edge of the SCK clock input.
Functional Description
The CAV25320 device supports the Serial Peripheral
Interface (SPI) bus protocol, modes (0,0) and (1,1). The
device contains an 8−bit instruction register. The instruction
set and associated op−codes are listed in Table 7.
SO: The serial data output pin is used to transfer data out of
the device. In SPI modes (0,0) and (1,1) data is shifted out
on the falling edge of the SCK clock.
SCK: The serial clock input pin accepts the clock provided
by the host and used for synchronizing communication
between host and CAV25320.
Reading data stored in the CAV25320 is accomplished by
simply providing the READ command and an address.
Writing to the CAV25320, in addition to a WRITE
command, address and data, also requires enabling the
device for writing by first setting certain bits in a Status
Register, as will be explained later.
After a high to low transition on the CS input pin, the
CAV25320 will accept any one of the six instruction
op−codes listed in Table 7 and will ignore all other possible
8−bit combinations. The communication protocol follows
the timing from Figure 2.
CS: The chip select input pin is used to enable/disable the
CAV25320. When CS is high, the SO output is tri−stated
(high impedance) and the device is in Standby Mode (unless
an internal write operation is in progress). Every
communication session between host and CAV25320 must be
preceded by a high to low transition and concluded with a low
to high transition of the CS input.
WP: The write protect input pin will allow all write
operations to the device when held high. When WP pin is
tied low and the WPEN bit in the Status Register (refer to
Status Register description, later in this Data Sheet) is set to
“1”, writing to the Status Register is disabled.
Table 7. INSTRUCTION SET
Instruction
WREN
WRDI
Opcode
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Operation
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
HOLD: The HOLD input pin is used to pause transmission
between host and CAV25320, without having to retransmit
the entire sequence at a later time. To pause, HOLD must be
taken low and to resume it must be taken back high, with the
SCK input low during both transitions. When not used for
RDSR
WRSR
READ
WRITE
t
CS
CS
t
t
t
WL
CSS
WH
t
t
t
CNS
CNH
CSH
SCK
SI
t
H
t
RI
t
FI
t
SU
VALID
IN
t
V
t
V
t
DIS
t
HO
HI−Z
HI−Z
VALID
OUT
SO
Figure 2. Synchronous Data Timing
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4
CAV25320
Status Register
The Status Register, as shown in Table 8, contains a
number of status and control bits.
allowed to protect a quarter, one half or the entire memory,
by setting these bits according to Table 9. The protected
blocks then become read−only.
The RDY (Ready) bit indicates whether the device is busy
with a write operation. This bit is automatically set to 1 during
an internal write cycle, and reset to 0 when the device is ready
to accept commands. For the host, this bit is read only.
The WEL (Write Enable Latch) bit is set/reset by the
WREN/WRDI commands. When set to 1, the device is in a
Write Enable state and when set to 0, the device is in a Write
Disable state.
The WPEN (Write Protect Enable) bit acts as an enable for
the WP pin. Hardware write protection is enabled when the
WP pin is low and the WPEN bit is 1. This condition
prevents writing to the status register and to the block
protected sections of memory. While hardware write
protection is active, only the non−block protected memory
can be written. Hardware write protection is disabled when
the WP pin is high or the WPEN bit is 0. The WPEN bit, WP
pin and WEL bit combine to either permit or inhibit Write
operations, as detailed in Table 10.
The BP0 and BP1 (Block Protect) bits determine which
blocks are currently write protected. They are set by the user
with the WRSR command and are non−volatile. The user is
Table 8. STATUS REGISTER
7
6
0
5
0
4
0
3
2
1
0
WPEN
BP1
BP0
WEL
RDY
Table 9. BLOCK PROTECTION BITS
Status Register Bits
BP1
BP0
Array Address Protected
None
Protection
0
0
1
1
0
1
0
1
No Protection
0C00−0FFF
Quarter Array Protection
Half Array Protection
Full Array Protection
0800−0FFF
0000−0FFF
Table 10. WRITE PROTECT CONDITIONS
WPEN
WP
X
WEL
Protected Blocks
Protected
Unprotected Blocks
Protected
Status Register
Protected
Writable
0
0
1
1
X
X
0
1
0
1
0
1
X
Protected
Writable
Low
Low
High
High
Protected
Protected
Protected
Protected
Protected
Writable
Protected
Writable
Protected
Protected
Protected
Writable
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5
CAV25320
WRITE OPERATIONS
Write Enable and Write Disable
The CAV25320 device powers up into a write disable
state. The device contains a Write Enable Latch (WEL)
which must be set before attempting to write to the memory
array or to the status register. In addition, the address of the
memory location(s) to be written must be outside the
protected area, as defined by BP0 and BP1 bits from the
status register.
The internal Write Enable Latch and the corresponding
Status Register WEL bit are set by sending the WREN
instruction to the CAV25320. Care must be taken to take the
CS input high after the WREN instruction, as otherwise the
Write Enable Latch will not be properly set. WREN timing
is illustrated in Figure 3. The WREN instruction must be
sent prior to any WRITE or WRSR instruction.
The internal write enable latch is reset by sending the
WRDI instruction as shown in Figure 4. Disabling write
operations by resetting the WEL bit, will protect the device
against inadvertent writes.
CS
SCK
1
1
0
SI
0
0
0
0
0
HIGH IMPEDANCE
SO
Dashed Line = mode (1, 1)
Figure 3. WREN Timing
CS
SCK
1
0
0
SI
0
0
0
0
0
HIGH IMPEDANCE
SO
Dashed Line = mode (1, 1)
Figure 4. WRDI Timing
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6
CAV25320
Byte Write
Page Write
Once the WEL bit is set, the user may execute a write
sequence, by sending a WRITE instruction, a 16−bit address
and data as shown in Figure 5. Only 12 significant address
bits are used by the CAV25320. The rest are don’t care bits,
as shown in Table 11. Internal programming will start after
the low to high CS transition. During an internal write cycle,
all commands, except for RDSR (Read Status Register) will
be ignored. The RDY bit will indicate if the internal write
cycle is in progress (RDY high), or the device is ready to
accept commands (RDY low).
After sending the first data byte to the CAV25320, the host
may continue sending data, up to a total of 32 bytes,
according to timing shown in Figure 6. After each data byte,
the lower order address bits are automatically incremented,
while the higher order address bits (page address) remain
unchanged. If during this process the end of page is
exceeded, then loading will “roll over” to the first byte in the
page, thus possibly overwriting previously loaded data.
Following completion of the write cycle, the CAV25320 is
automatically returned to the write disable state.
Table 11. BYTE ADDRESS
Device
Address Significant Bits
Address Don’t Care Bits
# Address Clock Pulses
CAV25320
A11 − A0
A15 − A12
16
CS
0
1
2
3
4
5
6
7
8
21 22 23 24 25 26 27 28 29 30 31
SCK
OPCODE
DATA IN
BYTE ADDRESS*
D7 D6 D5 D4 D3 D2 D1 D0
SI
0
0
0
0
0
0
1
0
A
N
A
0
HIGH IMPEDANCE
Dashed Line = mode (1, 1)
SO
* Please check the Byte Address Table (Table 11)
Figure 5. Byte WRITE Timing
CS
24+(N−1)x8−1 .. 24+(N−1)x8
21 22 23 24−31 32−39
0
1
2
3
4
5
6
7
8
24+Nx8−1
SCK
SI
Data Byte N
7..1
BYTE ADDRESS*
OPCODE
DATA IN
A
N
A
0
0
0
0
0
0
0
1
0
0
Data Data Data
Byte 1 Byte 2 Byte 3
HIGH IMPEDANCE
SO
Dashed Line = mode (1, 1)
* Please check the Byte Address Table (Table 11)
Figure 6. Page WRITE Timing
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7
CAV25320
Write Status Register
Write Protection
The Status Register is written by sending a WRSR
instruction according to timing shown in Figure 7. Only bits
2, 3 and 7 can be written using the WRSR command.
The Write Protect (WP) pin can be used to protect the
Block Protect bits BP0 and BP1 against being inadvertently
altered. When WP is low and the WPEN bit is set to “1”,
write operations to the Status Register are inhibited. WP
going low while CS is still low will interrupt a write to the
status register. If the internal write cycle has already been
initiated, WP going low will have no effect on any write
operation to the Status Register. The WP pin function is
blocked when the WPEN bit is set to “0”. The WP input
timing is shown in Figure 8.
CS
0
1
2
3
4
5
6
7
1
8
9
6
10
5
11
4
12
13
2
14
1
15
0
SCK
SI
OPCODE
0
DATA IN
3
0
0
0
0
0
0
7
MSB
HIGH IMPEDANCE
Dashed Line = mode (1, 1)
SO
Figure 7. WRSR Timing
t
t
WPH
WPS
CS
SCK
WP
WP
Dashed Line = mode (1, 1)
Figure 8. WP Timing
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8
CAV25320
READ OPERATIONS
Read from Memory Array
Read Status Register
To read from memory, the host sends a READ instruction
followed by a 16−bit address (see Table 11 for the number
of significant address bits).
To read the status register, the host simply sends a RDSR
command. After receiving the last bit of the command, the
CAT25320 will shift out the contents of the status register on
the SO pin (Figure 10). The status register may be read at any
time, including during an internal write cycle. While the
internal write cycle is in progress, the RDSR command will
output the full content of the status register. For easy
detection of the internal write cycle completion, both during
writing to the memory array and to the status register, we
recommend sampling the RDY bit only through the polling
routine. After detecting the RDY bit “0”, the next RDSR
instruction will always output the expected content of the
status register.
After receiving the last address bit, the CAV25320 will
respond by shifting out data on the SO pin (as shown in
Figure 9). Sequentially stored data can be read out by simply
continuing to run the clock. The internal address pointer is
automatically incremented to the next higher address as data
is shifted out. After reaching the highest memory address,
the address counter “rolls over” to the lowest memory
address, and the read cycle can be continued indefinitely.
The read operation is terminated by taking CS high.
CS
20 21 22 23 24 25 26 27 28 29 30
0
1
2
3
4
5
6
7
8
9
10
SCK
SI
OPCODE
BYTE ADDRESS*
A
0
A
N
0
0
0
0
0
0
1
1
DATA OUT
HIGH IMPEDANCE
SO
7
6
5
4
3
2
1
0
Dashed Line = mode (1, 1)
* Please check the Byte Address Table (Table 11)
MSB
Figure 9. READ Timing
CS
0
1
2
3
4
5
1
6
0
7
1
8
9
10
11
12
13
14
SCK
OPCODE
0
0
0
0
0
SI
DATA OUT
3
HIGH IMPEDANCE
Dashed Line = mode (1, 1)
5
7
6
4
2
1
0
SO
MSB
Figure 10. RDSR Timing
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9
CAV25320
Hold Operation
below the POR trigger level. This bi−directional POR
behavior protects the device against ‘brown−out’ failure
following a temporary loss of power.
The CAV25320 device powers up in a write disable state
and in a low power standby mode. A WREN instruction
must be issued prior to any writes to the device.
After power up, the CS pin must be brought low to enter
a ready state and receive an instruction. After a successful
byte/page write or status register write, the device goes into
a write disable mode. The CS input must be set high after the
proper number of clock cycles to start the internal write
cycle. Access to the memory array during an internal write
cycle is ignored and programming is continued. Any invalid
op−code will be ignored and the serial output pin (SO) will
remain in the high impedance state.
The HOLD input can be used to pause communication
between host and CAV25320. To pause, HOLD must be
taken low while SCK is low (Figure 11). During the hold
condition the device must remain selected (CS low). During
the pause, the data output pin (SO) is tri−stated (high
impedance) and SI transitions are ignored. To resume
communication, HOLD must be taken high while SCK is low.
Design Considerations
The CAV25320 device incorporates Power−On Reset
(POR) circuitry which protects the internal logic against
powering up in the wrong state. The device will power up
into Standby mode after VCC exceeds the POR trigger level
and will power down into Reset mode when VCC drops
CS
t
t
CD
CD
SCK
t
HD
t
HD
HOLD
SO
t
HZ
HIGH IMPEDANCE
t
LZ
Dashed Line = mode (1, 1)
Figure 11. HOLD Timing
ORDERING INFORMATION (Notes 8 − 10)
†
Device Order Number
CAV25320VE−GT3
Specific Device Marking
Package Type
Shipping
25320F
SOIC−8
(Pb−Free)
3,000 / Tape & Reel
3,000 / Tape & Reel
CAV25320YE−GT3
S32F
TSSOP−8
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
8. All packages are RoHS−compliant (Lead−free, Halogen−free).
9. The standard lead finish is NiPdAu.
10.For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.
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10
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8, 150 mils
CASE 751BD
ISSUE O
DATE 19 DEC 2008
SYMBOL
MIN
NOM
MAX
1.35
A
1.75
A1
b
0.10
0.33
0.19
4.80
5.80
3.80
0.25
0.51
0.25
5.00
6.20
4.00
c
E1
E
D
E
E1
e
h
L
θ
1.27 BSC
0.25
0.40
0º
0.50
1.27
8º
PIN # 1
IDENTIFICATION
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON34272E
SOIC 8, 150 MILS
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP8, 4.4x3.0, 0.65P
CASE 948AL
ISSUE A
DATE 20 MAY 2022
q
q
GENERIC
MARKING DIAGRAM*
XXX
YWW
AG
XXX = Specific Device Code
Y
= Year
WW = Work Week
A
G
= Assembly Location
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON34428E
TSSOP8, 4.4X3.0, 0.65P
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
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