CM1293-04SO [ONSEMI]
8-Channel Low Capacitance ESD Protection Array;
| 型号： | CM1293-04SO |
| 厂家： | 
ONSEMI |
| 描述： | 8-Channel Low Capacitance ESD Protection Array 局域网 光电二极管 |
| 文件： | 总8页 (文件大小：405K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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CM1293
8-Channel Low
Capacitance ESD
Protection Arrays
Product Description
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The CM1293 family of diode arrays has been designed to provide
ESD protection for electronic components or sub−systems requiring
minimal capacitive loading. These devices are ideal for protecting
systems with high data and clock rates or for circuits requiring low
capacitive loading. Each ESD channel consists of a pair of diodes in
series which steer the positive or negative ESD current pulse to either
MSOP−10
MR SUFFIX
CASE 846AE
the positive (V ) or negative (V ) supply rail. A Zener diode is
P
N
embedded between V and V , offering two advantages. First, it
P
N
protects the V rail against ESD strikes, and second, it eliminates the
BLOCK DIAGRAM
CC
need for a bypass capacitor that would otherwise be needed for
absorbing positive ESD strikes to ground. The CM1293 will protect
against ESD pulses up to (8 kV contact discharge) per the
IEC 61000−4−2Level 4 standard.
CH8
CH7
V
P
CH6 CH5
This device is particularly well−suited for protecting systems using
®
high−speed ports such as USB2.0, IEEE1394 (FireWire , i.LINKt),
Serial ATA, DVI, HDMI and corresponding ports in removable
storage, digital camcorders, DVD−RW drives and other applications
where extremely low loading capacitance with ESD protection are
required in a small package footprint.
CH1 CH2
V
CH3
CH4
N
CM1293−08MR
MARKING DIAGRAM
Features
• Eight Channels of ESD Protection
Note: For 2 and 4 Channel Devices, See the CM1293A Datasheet
• Provides ESD Protection to IEC61000−4−2
D039
•
8 kV Contact Discharge
• Low Loading Capacitance of 2.0 pF Max
• Low Clamping Voltage
• Channel I/O to I/O Capacitance 1.5 pF Typical
• Zener Diode Protects Supply Rail and Eliminates the Need for
External By−Pass Capacitors
• Each I/O Pin Can Withstand over 1000 ESD Strikes*
• These Devices are Pb−Free and are RoHS Compliant
D039
= CM1293−08MR
ORDERING INFORMATION
†
Device
CM1293−08MR
Package
Shipping
MSOP−10 4000/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Applications
• DVI Ports, HDMI Ports in Notebooks, Set Top Boxes, Digital TVs,
LCD Displays
• Serial ATA Ports in Desktop PCs and Hard Disk Drives
• PCI Express Ports
• General Purpose High−Speed Data Line ESD Protection
*Standard test condition is IEC61000−4−2 level 4 test circuit with each pin subjected to 8 kV contact discharge for 1000 pulses. Discharges
are timed at 1 second intervals and all 1000 strikes are completed in one continuous test run. The part is then subjected to standard production
test to verify that all of the tested parameters are within spec after the 1000 strikes.
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
March, 2011 − Rev. 4
CM1293/D
CM1293
PACKAGE / PINOUT DIAGRAM
Table 1. PIN DESCRIPTIONS
8−Channel, 10−Lead MSOP−10 Package
Top View
Pin
1
Name
CH1
CH2
CH3
CH4
Type
I/O
Description
ESD Channel
1
2
3
4
5
10
9
8
7
6
CH8
CH7
CH1
CH2
CH3
CH4
V
P
2
I/O
ESD Channel
CH6
CH5
3
I/O
ESD Channel
V
N
4
I/O
ESD Channel
10−Lead MSOP−10
5
V
GND
I/O
Negative Voltage Supply Rail
ESD Channel
N
6
CH5
CH6
7
I/O
ESD Channel
8
V
PWR
I/O
Positive Voltage Supply Rail
ESD Channel
P
9
CH7
CH8
10
I/O
ESD Channel
SPECIFICATIONS
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
6.0
Units
V
Operating Supply Voltage (V − V )
P
N
Operating Temperature Range
−40 to +85
−65 to +150
°C
°C
V
Storage Temperature Range
DC Voltage at any Channel Input
(V − 0.5) to (V + 0.5)
N P
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. STANDARD OPERATING CONDITIONS
Parameter
Rating
Units
°C
Operating Temperature Range
Package Power Rating
−40 to +85
mW
MSOP−10 Package (CM1293−08MR)
400
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2
CM1293
Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note 1)
Symbol
Parameter
Operating Supply Voltage (V −V )
Conditions
Min
Typ
Max
5.5
Units
V
V
P
3.3
P
N
I
Operating Supply Current
(V −V ) = 3.3 V
8.0
mA
V
P
P
N
V
Diode Forward Voltage
Top Diode
Bottom Diode
I = 8 mA, T = 25°C
F A
F
0.60
0.60
0.80
0.80
0.95
0.95
I
Channel Leakage Current
Channel Input Capacitance
T = 25°C, V = 5 V, V = 0 V
0.1
1.0
1.0
1.5
mA
pF
pF
pF
LEAK
A
P
N
C
At 1 MHz, V = 3.3 V, V = 0 V, V = 1.65 V
P N IN
IN
DC
IN
MUTUAL
Channel Input Capacitance Matching
At 1 MHz, V = 3.3 V, V = 0 V, V = 1.65 V
0.02
0.11
P
N
IN
C
Mutual Capacitance between Signal
Pin and Adjacent Signal Pin
At 1 MHz, V = 3.3 V, V = 0 V, V = 1.65 V
P N IN
V
ESD
ESD Protection
kV
Peak Discharge Voltage at any
Channel Input, in System
Contact Discharge per
IEC 61000−4−2 Standard
T = 25°C (Notes 3 and 4)
A
8
V
CL
Channel Clamp Voltage
Positive Transients
Negative Transients
T = 25°C, I = 1 A, t = 8/20 mS
V
A
PP
P
(Note 4)
+8.8
−1.4
R
Dynamic Resistance
Positive Transients
Negative Transients
I
= 1 A, t = 8/20 mS
W
DYN
PP
P
Any I/O Pin to Ground (Note 4)
0.7
0.4
1. All parameters specified at T = −40°C to +85°C unless otherwise noted.
A
2. Human Body Model per MIL−STD−883, Method 3015, C
= 100 pF, R
= 1.5 KW, V = 3.3 V, V grounded.
Discharge
Discharge P N
4. These measurements performed with no external capacitor on V (V floating).
Discharge P N
3. Standard IEC 61000−4−2 with C
= 150 pF, R
= 330 W, V = 3.3 V, V grounded.
Discharge
P
P
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3
CM1293
PERFORMANCE INFORMATION
Input Channel Capacitance Performance Curves
Figure 1. Typical Variation of CIN vs. VIN
(f = 1 MHz, VP = 3.3 V, VN = 0 V, 0.1 mF Chip Capacitor between VP and VN, 255C)
Figure 2. Typical Variation of CIN vs. Temp
(f = 1 MHz, VIN = 30 mV, VP = 3.3 V, VN = 0 V, 0.1 mF Chip Capacitor between VP and VN)
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4
CM1293
PERFORMANCE INFORMATION (Cont’d)
Typical Filter Performance (Nominal Conditions unless Specified Otherwise, 50 W Environment)
Figure 3. Insertion Loss (S21) vs. Frequency (0 VDC Bias, VP = 3.3 V)
Figure 4. Insertion Loss (S21) vs. Frequency (2.5 VDC Bias, VP = 3.3 V)
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5
CM1293
APPLICATION INFORMATION
Design Considerations
In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic
series inductances on the Supply/Ground rails as well as the signal trace segment between the signal input (typically
a connector) and the ESD protection device. Refer to Application of Positive ESD Pulse between Input Channel and Ground,
which illustrates an example of a positive ESD pulse striking an input channel. The parasitic series inductance back to power
supply is represented by L and L . The voltage V on the line being protected is:
1
2
CL
V
CL
= Fwd Voltage Drop of D + V
+ L x d(I
) / dt + L x d(I
) / dt
1
SUPPLY
1
ESD
2
ESD
where I
is the ESD current pulse, and V
is the positive supply voltage.
ESD
SUPPLY
An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge
per the IEC61000−4−2 standard results in a current pulse that rises from zero to 30 Amps in 1 ns. Here d(I
)/dt can be
ESD
−9
approximated by DI
/Dt, or 30/(1x10 ). So just 10 nH of series inductance (L and L combined) will lead to a 300 V
ESD
1
2
increment in V
!
CL
Similarly for negative ESD pulses, parasitic series inductance from the V pin to the ground rail will lead to drastically
N
increased negative voltage on the line being protected.
The CM1293 has an integrated Zener diode between V and V . This greatly reduces the effect of supply rail inductance
P
N
L on V by clamping V at the breakdown voltage of the Zener diode. However, for the lowest possible V , especially when
2
CL
P
CL
V is biased at a voltage significantly below the Zener breakdown voltage, it is recommended that a 0.22 mF ceramic chip
P
capacitor be connected between V and the ground plane.
P
As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected
electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the V pin of the Protection
P
Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the
ESD device to minimize stray series inductance.
L
2
V
CC
POSITIVE SUPPLY RAIL
V
P
PATH OF ESD CURRENT PULSE I
ESO
LINE BEING
PROTECTED
SYSTEM OR
CIRCUITRY
BEING
L
1
D
D
1
0.22 mF
CHANNEL
INPUT
ONE
CHANNEL
PROTECTED
2
V
CL
25 A
0 A
GROUND RAIL
V
N
CHASSIS GROUND
Figure 5. Application of Positive ESD Pulse between Input Channel and Ground
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6
CM1293
PACKAGE DIMENSIONS
MSOP 10, 3x3
CASE 846AE−01
ISSUE O
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
1.10
0.15
0.95
0.27
0.23
3.10
5.05
3.10
0.00
0.75
0.17
0.13
2.90
4.75
2.90
0.05
0.85
c
D
3.00
4.90
E
E1
E
E1
e
3.00
0.50 BSC
0.60
L
0.40
0.80
L1
L2
θ
0.95 REF
0.25 BSC
0º
8º
DETAIL A
TOP VIEW
D
A2
A
END VIEW
c
A1
e
b
q
SIDE VIEW
L2
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-187.
L
L1
DETAIL A
FireWire is a registered trademark of Apple Computer, Inc.; i.LINK is a trademark of Sony Corporation.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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CM1293/D
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