CM2009-02QR [ONSEMI]
VGA 端口伴随电路;
| 型号： | CM2009-02QR |
| 厂家： | 
ONSEMI |
| 描述： | VGA 端口伴随电路 光电二极管 商用集成电路 |
| 文件： | 总7页 (文件大小：209K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CM2009
VGA Port Companion
Circuit
Product Description
The CM2009 connects between a video graphics controller
embedded in a PC, graphics adapter card or set top box and the VGA
or DVI−I port connector. The CM2009 incorporates ESD protection
for all signals, level shifting for the DDC signals and buffering for the
SYNC signals. ESD protection for the video, DDC and SYNC lines is
implemented with low−capacitance current steering diodes.
All ESD diodes are designed to safely handle the high current spikes
specified by IEC−61000−4−2 Level 4 ( 8 kV contact discharge if
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QSOP16
QR SUFFIX
CASE 492
C
BYP
is present, 4 kV if not). The ESD protection for the DDC signal
pins are designed to prevent “back current” when the device is
powered down while connected to a monitor that is powered up.
Separate positive supply rails are provided for the VIDEO, DDC
and SYNC channels to facilitate interfacing with low voltage video
controller ICs to provide design flexibility in multi−supply−voltage
environments.
Two non−inverting drivers provide buffering for the HSYNC and
VSYNC signals from the video controller IC (SYNC1, SYNC2).
These buffers accept TTL input levels and convert them to CMOS
MARKING DIAGRAM
CMD YYWW
CM2009
0xQR
output levels that swing between Ground and V
typically 5 V. Additionally, each driver has a series termination resistor
(R ) connected to the SYNC_OUT pin, eliminating the external
T
, which is
CM2009 0xQR = Specific Device Code
CC_SYNC
YY
= Year
WW
= Work Week
termination resistors typically required for the HSYNC and VSYNC
lines of the video cable. There are three versions with different values
ORDERING INFORMATION
of R to allow termination at typically 65 W (CM2009−00) or 15 W
T
†
Device
Package
Shipping
(CM2009−02).
The 15 W (CM2009−02) version will typically require two external
resistors which can be chosen to exactly match the characteristic
impedance of the SYNC lines of the video cable.
Two N−channel MOSFETs provide the level shifting function
required when the DDC controller is operated at a lower supply
voltage than the monitor. The gate terminals for these MOSFETS
CM2009−00QR
QSOP−16 2500/Tape & Reel
(Pb−Free)
CM2009−02QR
QSOP−16 2500/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
(V ) should be connected to the supply rail (typically 3.3 V)
CC_DDC
that supplies power to the transceivers of the DDC controller.
Features
• Includes ESD Protection, Level−Shifting, Buffering and
Sync Impedance Matching
• 7 Channels of ESD Protection for all VGA Port
Connector Pins Meeting IEC−61000−4−2 Level 4 ESD
Requirements ( 8 kV Contact Discharge)
• 5 V Drivers for HSYNC and VSYNC Lines
• Integrated Impedance Matching Resistors on Sync Lines
• Bi−directional Level Shifting N−Channel FETs
Provided for DDC_CLK & DDC_DATA Channels
• Backdrive Protection on DDC Lines
• Compact 16−Lead QSOP Package
• These Devices are Pb−Free and are RoHS Compliant
• Very Low Loading Capacitance from ESD Protection
Diodes on VIDEO Lines (4 pF Maximum)
Applications
• VGA and DVI−I Ports in:
♦ Desktop and Notebook PCs
♦ Graphics Cards
♦ Set Top Boxes
© Semiconductor Components Industries, LLC, 2012
1
Publication Order Number:
May, 2012 − Rev. 5
CM2009/D
CM2009
SIMPLIFIED ELECTRICAL SCHEMATIC
9
DDC_OUT1
DDC_OUT2
VCC_VIDEO
12
2
VCC_SYNC
VCC_DDC
BYP
8
7
1
3
4
5
VIDEO_1
VIDEO_2
VIDEO_3
RT
RT
6
16
14
GND
SYNC_OUT2
SYNC_OUT1
GND
10
11
DDC_IN1
DDC_IN2
13
15
SYNC_IN1
SYNC_IN2
PACKAGE / PINOUT DIAGRAM
Top View
V
SYNC_OUT2
SYNC_IN2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CC_SYNC
V
CC_VIDEO
VIDEO_1
VIDEO_2
VIDEO_3
GND
SYNC_OUT1
SYNC_IN1
DDC_OUT2
DDC_IN2
DDC_IN1
DDC_OUT1
V
CC_DDC
BYP
16 Pin QSOP
Table 1. PIN DESCRIPTIONS
Lead(s)
Name
Description
1
V
This is an isolated supply input for the SYNC_1 and SYNC_2 level shifters and their associated ESD
protection circuits.
CC_SYNC
2
3
V
This is a supply pin specifically for the VIDEO_1, VIDEO_2 and VIDEO_3 ESD protection circuits.
CC_VIDEO
VIDEO_1
VIDEO_2
VIDEO_3
GND
Video signal ESD protection channel. This pin is typically tied one of the video lines between the VGA
controller device and the video connector.
4
5
Video signal ESD protection channel. This pin is typically tied one of the video lines between the VGA
controller device and the video connector.
Video signal ESD protection channel. This pin is typically tied one of the video lines between the VGA
controller device and the video connector.
6
7
8
Ground reference supply pin.
V
This is an isolated supply input for the DDC_1 and DDC_2 level−shifting N−FET gates.
CC_DDC
BYP
This input is used to connect an external 0.2 mF bypass capacitor to the DDC circuits, resulting in an
increased ESD withstand voltage rating for these circuits ( 8 kV with vs. 4 kV without).
9
DDC_OUT1
DDC_IN1
DDC signal output. Connects to the video connector side of one of the sync lines.
DDC signal input. Connects to the VGA controller side of one of the sync lines.
10
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2
CM2009
Table 1. PIN DESCRIPTIONS
Lead(s)
11
Name
Description
DDC_IN2
DDC signal input. Connects to the VGA controller side of one of the sync lines.
DDC signal output. Connects to the video connector side of one of the sync lines.
Sync signal buffer input. Connects to the VGA controller side of one of the sync lines.
Sync signal buffer output. Connects to the video connector side of one of the sync lines.
Sync signal buffer input. Connects to the VGA controller side of one of the sync lines.
Sync signal buffer output. Connects to the video connector side of one of the sync lines.
12
DDC_OUT2
SYNC_IN1
SYNC_OUT1
SYNC_IN2
SYNC_OUT2
13
14
15
16
SPECIFICATIONS
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
[GND − 0.5] to +6.0
10
Units
V
V
V
and V
Supply Voltage Inputs
CC_VIDEO, CC_DDC
CC_SYNC
ESD Diode Forward Current (one diode conducting at a time)
mA
V
DC Voltage at Inputs
VIDEO_1, VIDEO_2, VIDEO_3
DDC_IN1, DDC_IN2
DDC_OUT1, DDC_OUT2
SYNC_IN1, SYNC_IN2
[GND − 0.5] to [V
+ 0.5]
+ 0.5]
CC_VIDEO
[GND − 0.5] to 6.0
[GND − 0.5] to 6.0
[GND − 0.5] to [V
CC_SYNC
Operating Temperature Range
Storage Temperature Range
−40 to +85
°C
°C
−40 to +150
Package Power Rating (T = 25°C)
500
mW
A
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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3
CM2009
Table 3. ELECTRICAL OPERATING CHARACTERISTICS (Note 1)
Symbol
Parameter
Conditions
Min
Typ Max Units
I
V
Supply Current
V
= 5.0 V; VIDEO inputs at V
CC_VIDEO
10
mA
CC_VIDEO
CC_VIDEO
CC_VIDEO
or GND
I
V
V
Supply Current
Supply Current
V
= 5.0 V
10
50
mA
mA
CC_DDC
CC_DDC
CC_DDC
I
V
V
= 5 V; SYNC inputs at GND or
; SYNC outputs unloaded
CC_SYNC
CC_SYNC
CC_SYNC
CC_SYNC
V
= 5 V; SYNC inputs at 3.0 V;
2.0
1.0
mA
CC_SYNC
SYNC outputs unloaded
V
ESD Diode Forward Voltage
Logic High Input Voltage
Logic Low Input Voltage
Logic High Output Voltage
Logic Low Output Voltage
I = 10 mA
F
V
V
V
V
V
W
F
V
IH
V
V
= 5.0 V; (Note 2)
= 5.0 V; (Note 2)
2.0
CC_SYNC
CC_SYNC
V
IL
0.6
V
OH
I
I
= 0 mA, V
= 5.0 V; (Note 2)
4.85
OH
CC_SYNC
CC_SYNC
V
OL
= 0 mA, V
OL
= 5.0 V; (Note 2)
0.15
R
SYNC Driver Output Resistance
(CM2009−00 only)
V
= 5.0 V; SYNC Inputs at GND or 3.0 V
65
15
OUT
CC_SYNC
R
SYNC Driver Output Resistance
(CM2009−02 only)
V
= 5.0 V; SYNC Inputs at GND or 3.0 V;
W
V
V
OUT
CC_SYNC
(Note ?)
= 24 mA; V
V
OH−02
Logic High Output Voltage
(CM2009−02 only)
I
= 5.0 V;
= 5.0 V;
2.0
OH
CC_SYNC
(Note 2)
V
OL−02
Logic Low Output Voltage
(CM2009−02 only)
I
OL
= 24 mA; V
0.8
CC_SYNC
(Note 2)
I
IN
Input Current
VIDEO Inputs
V
V
= 5.0 V; V = V or GND
CC_VIDEO
1
1
mA
mA
mA
CC_VIDEO
IN
SYNC_IN1, SYNC_IN2 Inputs
= 5.0 V; V = V
or GND
CC_SYNC
IN
CC_SYNC
I
Level Shifting N−MOSFET ”OFF” State
Leakage Current
(V
− V ) ≤ 0.4 V;
DDC_IN
= V
10
OFF
CC_DDC
V
DDC_OUT CC_DDC
(V
DDC_IN
− V
CC_DDC
) ≤ 0.4 V;
10
0.18
4
mA
V
CC_DDC
DDC_OUT
V
= V
V
ON
Voltage Drop Across Level−shifting
N−MOSFET when “ON”
V = 2.5 V; V = GND; I = 3 mA;
CC_DDC S DS
C
VIDEO Input Capacitance
V
= 5.0 V; V = 2.5 V; f = 1 MHz;
pF
pF
IN_VID
CC_VIDEO
IN
(Note 4)
V
= 2.5 V; V = 1.25 V; f = 1 MHz;
4.5
CC_VIDEO
IN
(Note 4)
t
t
SYNC Driver L => H Propagation Delay
SYNC Driver H => L Propagation Delay
SYNC Driver Output Rise & Fall Times
ESD Withstand Voltage
C = 50 pF; V = 5.0 V; Input t and t ≤ 5 ns
12
12
ns
ns
ns
kV
PLH
L
CC
R
F
C = 50 pF; V = 5.0 V; Input t and t ≤ 5 ns
PHL
L
CC
R
F
t
t
C = 50 pF; V = 5.0 V; Input t and t ≤ 5 ns
4
R, F
L
CC
R
F
V
V
= V = 5 V; (Notes 3, 4 & ?)
CC_SYNC
8
ESD
CC_VIDEO
1. All parameters specified over standard operating conditions unless otherwise noted.
2. These parameters apply only to the SYNC drivers. Note that R = R + R
.
BUFFER
OUT
T
3. Per the IEC−61000−4−2 International ESD Standard, Level 4 contact discharge method. BYP, V
and V
must be bypassed
CC_VIDEO
CC_SYNC
to GND via a low impedance ground plane with a 0.2 mF, low inductance, chip ceramic capacitor at each supply pin. ESD pulse is applied
between the applicable pins and GND. ESD pulses can be positive or negative with respect to GND. Applicable pins are: VIDEO_1, VIDEO_2,
VIDEO_3, SYNC_OUT1, SYNC_OUT2, DDC_OUT1 and DDC_OUT2. All other pins are ESD protected to the industry standard 2 kV
Human Body Model (MIL−STD−883, Method 3015). The bypass capacitor at the BYP pin may optionally be omitted, in which case the max.
ESD withstand voltage for the DDC_OUT1 and DDC_OUT2 pins is reduced to 4 kV.
4. The SYNC_OUT pins on the CM2009−02 are guaranteed for 2 kV HBM ESD protection.
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4
CM2009
APPLICATION INFORMATION
Figure 1. Typical Application Connection Diagram
NOTES:
1. The CM2009 should be placed as close to the VGA or DVI−I connector as possible.
2. The ESD protection channels VIDEO_1, VIDEO_2, VIDEO_3 may be used interchangeably between the R, G, B
signals.
3. If differential video signal routing is used, the RED, BLUE, and GREEN signal lines should be terminated with
external 37.5 W resistors.
4. “VF” are external video filters for the RGB signals.
5. Supply bypass capacitors C1 and C2 must be placed immediately adjacent to the corresponding Vcc pins.
Connections to the Vcc pins and ground plane must be made with minimal length copper traces (preferably less than
5 mm) for best ESD protection.
6. The bypass capacitor for the BYP pin has been omitted in this diagram. This results in a reduction in the maximum
ESD withstand voltage at the DDC_OUT pins from 8 kV to 4 kV. If 8 kV ESD protection is required, a 0.2 mF
ceramic bypass capacitor should be connected between BYP and ground.
7. The SYNC buffers may be used interchangeably between HSYNC and VSYNC.
8. The EMI filters at the SYNC_OUT and DDC_OUT pins (C5 to C12, and Ferrite Beads FB1 to FB4) are for reference
only. The component values and filter configuration may be changed to suit the application.
9. The DDC level shifters DDC_IN, DDC_OUT, may be used interchangeably between DDCA_CLK and
DDCA_DATA.
10. R1, R2 are optional. They may be used, if required, to pull the DDC_CLK and DDC_DATA lines to VCC_5V when
no monitor is connected to the VGA connector. If used, it should be noted that “back current” may flow between the
DDC pins and VCC_5V via these resistors when VCC_5V is powered down.
11. For optimal ESD performance with the CM2009−02, an additional clamp device (such as the CMD PACDN042)
should be placed on HSYNC/VSYNC lines between the external matching resistor and the VGA connector.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
QSOP16
CASE 492−01
ISSUE A
DATE 23 MAR 2011
2X
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION.
4. DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH,
PROTRUSIONS, OR GATE BURRS SHALL NOT EX
CEED 0.005 PER SIDE. DIMENSION E1 DOES NOT
INCLUDE INTERLEAD FLASH OR PROTRUSION. IN
TERLEAD FLASH OR PROTRUSION SHALL NOT EX
CEED 0.005 PER SIDE. D AND E1 ARE DETERMINED
AT DATUM H.
0.20 C
D
D
L2
D
A
16
9
GAUGE
PLANE
SEATING
PLANE
E
C
E1
C
L
2X
DETAIL A
5. DATUMS A AND B ARE DETERMINED AT DATUM H.
2X 10 TIPS
0.20 C
D
INCHES
MIN
0.053
MILLIMETERS
DIM
MAX
0.069
0.010
----
0.012
0.010
MIN
1.35
0.10
1.24
0.20
0.19
MAX
1.75
0.25
----
0.30
0.25
1
8
0.25
C D
A
16X b
e
A1 0.004
A2 0.049
M
0.25
C A-B D
B
b
c
0.008
0.007
h x 45
_
D
E
0.193 BSC
4.89 BSC
A2
0.237 BSC
0.154 BSC
0.025 BSC
6.00 BSC
3.90 BSC
0.635 BSC
H
0.10
0.10
C
C
A
E1
e
h
0.009
0.020
0.050
0.22
0.40
0.50
L
0.016
1.27
L2
M
0.010 BSC
0.25 BSC
A1
0
8
0
8
_
_
_
_
SEATING
PLANE
16X
M
C
DETAIL A
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT
16X
0.42
16X
1.12
16
9
XXXXXXX
XXXXXXX
YYWWG
XXXXX = Specific Device Code
6.40
YY
WW
G
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer
to device data sheet for actual part
marking. Pb−Free indicator, “G”, may
or not be present.
1
8
0.635
PITCH
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON04472D
QSOP16
PAGE 1 OF 1
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