CM3202-00DE [ONSEMI]
DDR VDDQ 和端接稳压器;
| 型号： | CM3202-00DE |
| 厂家： | 
ONSEMI |
| 描述： | DDR VDDQ 和端接稳压器 双倍数据速率 接口集成电路 稳压器 |
| 文件： | 总12页 (文件大小：262K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CM3202-00
DDR VDDQ and VTT
Termination Voltage
Regulator
Product Description
The CM3202−00 is a dual−output low noise linear regulator
designed to meet SSTL−2 and SSTL−3 specifications for
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DDR−SDRAM V
supply and termination voltage V supply.
DDQ
TT
With integrated power MOSFET’s, the CM3202−00 can source up to
2 A of VDDQ continuous current, and source or sink up to 2 A VTT
continuous current. The typical dropout voltage for VDDQ is 500 mV
at 2 A load current.
The CM3202−00 provides fast response to transient load changes.
Load regulation is excellent, from no load to full load. It also has
built−in over−current limits and thermal shutdown at 170°C.
The CM3202−00 supports Suspend−To−RAM (STR) and ACPI
1
WDFN8
DE SUFFIX
CASE 511BH
MARKING DIAGRAM
compliance with shutdown mode which tri−states V to minimize
quiescent system current.
The CM3202−00 is packaged in an easy−to−use WDFN8. Low
thermal resistance allows it to withstand high power dissipation at
85°C ambient. It operates over the industrial ambient temperature
range of –40°C to 85°C.
TT
CM320
200DE
CM320 200DE = CM3202−00DE
Features
ORDERING INFORMATION
• Two Linear Regulators
†
♦ Maximum 2 A Current from VDDQ
♦ Source and Sink Up to 2 A VTT Current
Device
CM3202−00DE
Package
Shipping
WDFN8
3000/Tape & Reel
(Pb−Free)
• 1.7 V to 2.8 V Adjustable V
Output Voltage
• 500 mV Typical VDDQ Dropout Voltage at 2 A
DDQ
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
• V Tracking at 50% of VDDQ
TT
• Excellent Load and Line Regulation, Low Noise
• Fast Transient Response
• Meet JEDEC DDR−I and DDR−II Memory Power Spec.
• Linear Regulator Design Requires No Inductors and Has Low
External Component Count
• Integrated Power MOSFETs
• Dual Purpose ADJ/Shutdown Pin
• Built−In Over−Current Limit and Thermal Shutdown for VDDQ
and VTT
• Fast Transient Response
• Low Quiescent Current
• These Devices are Pb−Free and are RoHS Compliant
Applications
• DDR Memory and Active Termination Buses
• Desktop Computers, Servers
• Residential and Enterprise Gateways
• DSL Modems
• Routers and Switchers
• DVD Recorders
• 3D AGP Cards
• LCD TV and STB
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
April, 2011 − Rev. 3
CM3202−00/D
CM3202−00
TYPICAL APPLICATION
V
IN
= 3.3 V to 3.6 V
V
DDQ
= 2.5 V/2 A
C
IN
4.7 mF/10 V
C
4.7 mF/10 V, cer
DDQ
220 mF/
10 V
cer
VDDQ
VDDQ
Chip
Set
220 mF/
10 V
DL0
1
2
8
7
VIN
VDDQ
R1
10 kW
RT0
ADJSD
NC
DLn
CM3202
V
= 1.25 V/2 A
TT
3
4
6
5
GND
VTT
NC
C
TT
RTn
R2
10 kW
DDR
REF MEMORY
GND
4.7 mF/
220 mF/
S/D
10 V
cer
10 V
1.25 V, 2.5 A
1 kW
V
TT
V
REF
0.1 mF/10 V
cer
FUNCTIONAL BLOCK DIAGRAM
VIN
ADJSD
VDDQ
+
1.22 V
UVLO &
Bandgap
-
+
-
Current
Limit
OTP &
Shutdown
Current
Limit
+
-
0.49*
VDDQ
V
TT
0.51*
VDDQ
+
-
GND
Current
Limit
CM3202
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2
CM3202−00
PACKAGE / PINOUT DIAGRAMS
Top View
Bottom View
(Pins Down View)
(Pins Up View)
Thermal Pad
VDDQ
Pin 1
Marking
VIN
1
8
8
1
NC
VTT
NC
2
3
4
7
6
5
ADJSD
GND
7
6
5
2
3
4
GND
PAD
GND
8−Lead WDFN Package
CM3202−00DE
Table 1. PIN DESCRIPTIONS
Lead(s)
Name
VIN
Description
Input supply voltage pin. Bypass with a 220 mF capacitor to GND.
Not internally connected. For better heat flow, connect to GND (exposed pad).
regulator output pin, which is preset to 50% of V
1
2
3
4
5
6
NC
VTT
NC
V
TT
.
DDQ
Not internally connected. For better heat flow, connect to GND (exposed pad).
GND
GND
Ground pin (analog).
Ground pin (power).
This pin is for V
output voltage adjustment. It is available as long as V
is enabled.
DDQ
DDQ
During Manual/Thermal shutdown, it is tightened to GND. The V
using an external resistor divider connected to ADJSD:
output voltage is set
DDQ
V
DDQ
= 1.25 V × ((R1 + R2) / R2)
7
ADJSD
Where R1 is the upper resistor and R2 is the ground−side resistor. In addition, the ADJSD pin functions as
a Shutdown pin. When ADJSD voltage is higher than 2.7 V (SHDN_H), the circuit is in Shutdown mode.
When ADJSD voltage is below 1.5 V (SHDN_L), both VDDQ and VTT are enabled. A low−leakage Schottky
diode in series with ADJSD pin is recommended to avoid interference with the voltage adjustment setting.
8
VDDQ
GND
V
regulator output voltage pin.
DDQ
EPad
The backside exposed pad which serves as the package heatsink. Must be connected to GND.
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3
CM3202−00
SPECIFICATIONS
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter
VIN to GND
Rating
Units
[GND − 0.3] to +6.0
V
V
Pin Voltages
V
, V to GND
[GND − 0.3] to +6.0
[GND − 0.3] to +6.0
DDQ TT
ADJSD to GND
Output Current
A
VDDQ / VTT, Continuous (Note 1)
VDDQ / VTT, Peak
2.0 / 2.0
2.8 / 2.8
3
VDDQ Source + VTT Source
Temperature
°C
Operating Ambient
Operating Junction
Storage
–40 to +85
–40 to +170
–40 to +150
Thermal Resistance, R (Note 2)
55
°C / W
JA
WDFN8, 3 mm x 3 mm
Continuous Power Dissipation (Note 2)
W
WDFN8, T = 25°C / 85°C
2.6 / 1.5
2000
A
ESD Protection (HBM)
V
Lead Temperature (Soldering, 10 sec)
300
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Despite the fact that the device is designed to handle large continuous/peak output currents, it is not capable of handling these under all
conditions. Limited by the package thermal resistance, the maximum output current of the device cannot exceed the limit imposed by the
maximum power dissipation value.
2
2. Measured with the package using a 4 in / 2 layers PCB with thermal vias.
Table 3. STANDARD OPERATING CONDITIONS
Parameter
Rating
Units
Ambient Operating Temperature Range
–40 to +85
°C
VDDQ Regulator
DDR−1 Supply Voltage, VIN
Load Current, Continuous
Load Current, Peak (1 s)
3.1 to 3.6
0 to 2
2.5
V
A
A
C
220
mF
DDQ
VTT Regulator
DDR−1 Supply Voltage, VIN
Load Current, Continuous
Load Current, Peak (1 s)
3.1 to 3.6
0 to 2.0
2.50
V
A
A
C
220
mF
TT
V
Supply Voltage Range
3.10 to 3.60
V
A
IN
VDDQ Source + VTT Source
Load Current, Continuous
Load Current, Peak (1 s)
2.5
3.5
Junction Operating Temperature Range
–40 to +150
°C
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CM3202−00
SPECIFICATIONS (Cont’d)
Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note 1)
Symbol
General
Parameter
Conditions
Min
Typ
Max
Units
I
Quiescent Current
Shutdown Current
ADJSD Logic High
ADJSD Logic Low
I
= 0, I = 0
8
15
mA
mA
V
Q
DDQ
TT
I
V
= 3.3 V (Shutdown)
0.1
0.5
SHDN
ADJSD
SHDN_H
SHDN_L
UVLO
(Note 2)
2.7
1.50
2.90
V
Under−Voltage Lockout
Thermal SHDN Threshold
Thermal SHDN Hysteresis
Hysteresis = 100 mV
2.40
150
2.70
170
50
V
T
°C
OVER
T
°C
HYS
TEMPCO
V , V TEMPCO
DDQ TT
150
ppm/°C
VDDQ Regulator
V
VDDQ Output Voltage
VDDQ Load Regulation
VDDQ Line Regulation
VDDQ Dropout Voltage
ADJSD Bias Current
VDDQ Current Limit
I
= 100 mA
2.450 2.500 2.550
V
DDQ DEF
DDQ
V
10 mA ≤ I
≤ 2 A (Note 3)
10
5
25
25
mV
mV
mV
mA
A
DDQ LOAD
DDQ
V
3.1 V ≤ V ≤ 3.6 V, I
= 0.1 A
DDQ LINE
IN
DDQ
V
I = 2 A (Note 4)
DDQ
500
0.8
2.5
DROP
I
3.0
ADJ
DDQ LIM
I
2.0
VTT Regulator
V
VTT Output Voltage
VTT Load Regulation
I
= 100 mA
TT
1.225 1.250 1.275
V
TT DEF
V
Source, 0 ≤ I ≤ 2 A (Note 3)
Sink, −2 A ≤ I ≤ 0 (Note 3)
10
30
mV
TT LOAD
TT
TT
–30
2.0
–10
V
VTT Line Regulation
3.1 V ≤ V ≤ 3.6 V, I = 0.1 A
5
15
mV
A
TT LINE
IN
TT
I
ITT Current Limit
Source / Sink (Note 3)
2.5
TT LIM
I
VTT Shutdown Leakage Current
Thermal Shutdown Enabled
10
mA
VTT OFF
1. V = 3.3 V, V
= 2.50 V, V = 1.25 V (default values), C
= C = 47 mF, T = 25°C unless otherwise specified.
IN
DDQ
TT
DDQ TT A
2. he SHDN Logic High value is normally satisfied for full input voltage range by using a low leakage current (bellow 1 mA). Schottky diode at
ADJSD control pin.
3. Load and line regulation are measured at constant junction temperature by using pulse testing with a low duty cycle. Changes in output
voltage due to heating effects must be taken into account separately. Load and line regulation values are guaranteed up to the maximum
power dissipation.
4. Dropout voltage is input to output voltage differential at which output voltage has dropped 100 mV from the nominal value obtained at 3.3 V
input. It depends on load current and junction temperature.
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CM3202−00
TYPICAL OPERATING CHARACTERISTICS
VTT vs. VDDQ
VDDQ vs. Temperature
1.65
1.55
1.45
1.35
1.25
1.15
1.05
0.95
0.85
0.75
2.510
2.505
2.
500
2.495
2.490
1.5ꢀꢁꢂ1.75ꢀꢁꢃꢄꢂ2ꢀꢁꢃꢄ2.25 2.5
2.75
3
3.25
−40 −20
0
20 40 60 80 100 120 140
VDDQ (V)
TEMPERATURE (5C)
VDDQ vs. Load Current
VDDQ Dropout vs. IDDQ
3.0
2.5
2.0
1.5
1.0
600
500
400
300
200
TA = 25°C
VIN = 3.3 V
TA = 25°C
0.5
0
100
0
0
1.0
2.0
3.0
4.0
0
0.5
1.0
1.5
2.0
2.5
IDDQ (A)
IDDQ (A)
VTT vs. Load Current
Startup into Full Load
2.5
2.0
Vin
2 V/div
UVLO
1.5
1.0
VDDQ
1 V/div
0.5
0
VTT
1 V/div
0
1.0
2.0
3.0
4.0
ITT (A)
TIME (1 ms/div)
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CM3202−00
TYPICAL OPERATING CHARACTERISTICS (Cont’d)
VDDQ Transient Response
VTT Transient Response
V
= 3.3V
IN
V
IN
IDDQ
0.5A/div
ITT
0.5A/div
-0.75A
VDDQ
0.1V/div
VTT
0.1V/div
TIME (0.2 ms/div)
TIME (0.2 ms/div)
APPLICATION INFORMATION
Powering DDR Memory
Double−Data−Rate (DDR) memory has provided a huge step in performance for personal computers, servers and graphic
systems. As is apparent in its name, DDR operates at double the data rate of earlier RAM, with two memory accesses per cycle
versus one. DDR SDRAM’s transmit data at both the rising and falling edges of the memory bus clock.
DDR’s use of Stub Series Terminated Logic (SSTL) topology improves noise immunity and power−supply rejection, while
reducing power dissipation. To achieve this performance improvement, DDR requires more complex power management
architecture than previous RAM technology.
Unlike the conventional DRAM technology, DDR SDRAM uses differential inputs and a reference voltage for all interface
signals. This increases the data bus bandwidth, and lowers the system power consumption. Power consumption is reduced by
lower operating voltage, a lower signal voltage swing associated with Stub Series Terminated Logic (SSTL_2), and by the use
of a termination voltage, V . SSTL_2 is an industry standard defined in JEDEC document JESD8−9. SSTL_2 maintains
TT
high−speed data bus signal integrity by reducing transmission reflections. JEDEC further defines the DDR SDRAM
specification in JESD79C.
DDR memory requires three tightly regulated voltages: V
, V , and V
(see Typical DDR terminations, Class II). In
DDQ TT
REF
a typical SSTL_2 receiver, the higher current V
supply voltage is normally 2.5 V with a tolerance of 200 mV. The active
DDQ
bus termination voltage, V , is half of V
. V
is a reference voltage that tracks half of V
1%, and is compared
TT
DDQ
REF
DDQ,
with the V terminated signal at the receiver. V must be within 40 mV of V
TT
TT
REF
VDDQ
VTT (=VDDQ/2) VDDQ
Rt = 25
Rs = 25
Transmitter
Line
+
−
Receiver
VREF (=VDDQ/2)
Figure 1. Typical DDR Terminations, Class II
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CM3202−00
APPLICATION INFORMATION (Cont’d)
The VTT power requirement is proportional to the number of data lines and the resistance of the termination resistor, but
does not vary with memory size. In a typical DDR data bus system each data line termination may momentarily consume
16.2 mA to achieve the 405 mV minimum over V needed at the receiver:
TT
405ꢀmV
Iterminaton
+
+ 16.2ꢀmA
Rt(25ꢀW)
A typical 64 Mbyte SSTL−2 memory system, with 128 terminated lines, has a worst−case maximum V supply current up
TT
to 2.07 A. However, a DDR memory system is dynamic, and the theoretical peak currents only occur for short durations, if
they ever occur at all. These high current peaks can be handled by the V external capacitor. In a real memory system, the
TT
continuous average V current level in normal operation is less than 200 mA.
TT
The VDDQ power supply, in addition to supplying current to the memory banks, could also supply current to controllers
and other circuitry. The current level typically stays within a range of 0.5 A to 1 A, with peaks up to 2 A or more, depending
on memory size and the computing operations being performed.
The tight tracking requirements and the need for V to sink, as well as source, current provide unique challenges for
TT
powering DDR SDRAM.
CM3202−00 Regulator
The CM3202−00 dual output linear regulator provides all of the power requirements of DDR memory by combining two
linear regulators into a single TDFN−8 package. VDDQ regulator can supply up to 2 A current, and the two−quadrant V
TT
termination regulator has current sink and source capability to 2 A. The VDDQ linear regulator uses a PMOS pass element
for a very low dropout voltage, typically 500 mV at a 2 A output. The output voltage of V can be set by an external voltage
DDQ
divider. The use of regulators for both the upper and lower side of the VDDQ output allows a fast transient response to any
change of the load, from high current to low current or inversely. The second output, V , is regulated at V /2 by an internal
TT
DDQ
resistor divider. Same as VDDQ, VTT has the same fast transient response to load change in both directions. The V regulator
TT
can source, as well as sink, up to 2 A current. The CM3202−00 is designed for optimal operation from a nominal 3.3 VDC bus,
but can work with VIN as high as 5 V. When operating at higher VIN voltages, attention must be given to the increased package
power dissipation and proportionally increased heat generation.
V
REF
is typically routed to inputs with high impedance, such as a comparator, with little current draw. An adequate V
REF
can be created with a simple voltage divider of precision, matched resistors from V
capacitor can also be added for improved noise performance.
to ground. A small ceramic bypass
DDQ
Input and Output Capacitors
The CM3202−00 requires that at least a 220 mF electrolytic capacitor be located near the V pin for stability and to maintain
IN
the input bus voltage during load transients. An additional 4.7 mF ceramic capacitor between the V and the GND, located
IN
as close as possible to those pins, is recommended to ensure stability.
At a minimum of a 220 mF electrolytic capacitor is recommended for the V
output. An additional 4.7 mF ceramic
DDQ
capacitor between the V
and GND, located very close to those pins, is recommended.
DDQ
At a minimum of a 220 mF electrolytic capacitor is recommended for the V output. This capacitor should have low ESR
TT
to achieve best output transient response. SP or OSCON capacitors provide low ESR at high frequency, and thus are a good
choice. In addition, place a 4.7 mF ceramic capacitor between the V pin and GND, located very close to those pins. The total
TT
ESR must be low enough to keep the transient within the V window of 40 mV during the transition for source to sink.
TT
An average current step of 0.5 A requires:
40ꢀmV
ESR t
+ 40ꢀmW
1ꢀA
Both outputs will remain stable and in regulation even during light or no load conditions.
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8
CM3202−00
APPLICATION INFORMATION (Cont’d)
Adjusting VDDQ Output Voltage
The CM3202−00 internal bandgap reference is set at 1.25 V. The V
voltage is adjustable by using a resistor divider, R1
DDQ
and R2:
VDDQ + VADJ
where V
R1 ) R2
R2
= 1.25 V. For best regulator stability, we recommend that R and R not exceed 10 kW each.
ADJ
1
2
Shutdown
ADJSD also serves as a shutdown pin. When this is pulled high (SHDN_H), both the VDDQ and the VTT outputs tri−state
and could sink/source less than 10 mA. During shutdown, the quiescent current is reduced to less than 0.5 mA, independent
of output load.
It is recommended that a low leakage Schottky diode be placed between the ADJSD Pin and an external shutdown signal
to prevent interference with the ADJ pin’s normal operation. When the diode anode is pulled low, or left open, the CM3202−00
is again enabled.
Current Limit, Foldback and Over−temperature Protection
The CM3202−00 features internal current limiting with thermal protection. During normal operation, V
limits the output
DDQ
current to approximately 2 A and V limits the output current to approximately 2 A. When V is current limiting into a hard
TT
TT
short circuit, the output current folds back to a lower level, about 1 A, until the over−current condition ends. While current
limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the
package. If the junction temperature of the device exceeds 170°C (typical), the thermal protection circuitry triggers and
tri−states both VDDQ and VTT outputs. Once the junction temperature has cooled to below about 120°C the CM3202−00
returns to normal operation.
Thermal Considerations
Typical Thermal Characteristics
The overall junction to ambient thermal resistance (q ) for device power dissipation (P ) primarily consists of two paths
JA
D
in the series. The first path is the junction to the case (q ) which is defined by the package style and the second path is case
JC
to ambient (q ) thermal resistance which is dependent on board layout. The final operating junction temperature for any
CA
condition can be estimated by the following thermal equation:
TJUNC + TAMB ) PD (qJC) ) PD (qCA)
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ+ TAMB ) PD (qCA)
When a CM3202−00 using WDFN8 package is mounted on a double−sided printed circuit board with four square inches
of copper allocated for “heat spreading,” the q is approximately 55°C/W. Based on the over temperature limit of 170°C with
JA
an ambient temperature of 85°C, the available power of the package will be:
170° C * 85° C
PD +
+ 1.5ꢀW
55° CńW
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CM3202−00
APPLICATION INFORMATION (Cont’d)
PCB Layout Considerations
TheCM3202−00 has a heat spreader attached to the bottom of the WDFN8 package in order for the heat to be transferred
more easily from the package to the PCB. The heat spreader is a copper pad of dimensions just smaller than the package itself.
By positioning the matching pad on the PCB top layer to connect to the spreader during the manufacturing, the heat will be
transferred between the two pads. See the Thermal Layout, the CM3202−00 shows the recommended PCB layout. Please be
noted that there are four vias on either side to allow the heat to dissipate into the ground and power planes on the inner layers
of the PCB. Vias can be placed underneath the chip, but this can be resulted in blocking of the solder. The ground and power
planes need to be at least 2 square inches of copper by the vias. It also helps dissipation if the chip is positioned away from
the edge of the PCB, and not near other heat−dissipating devices. A good thermal link from the PCB pad to the rest of the PCB
will assure the best heat transfer from the CM3202−00 to ambient, qJA, of approximately 55°C/W.
Top View
Bottom Layer
Ground Plane
Top Layer Copper
Connects to Heat Spreader
Pin Solder Mask
Thermal PAD
Solder Mask
Vias (0.3 mm Diameter)
Figure 2. Thermal Layout for WDFN8 Package
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10
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFN8 3x3, 0.65P
CASE 511BH−01
ISSUE O
1
DATE 21 JUL 2010
SCALE 2:1
NOTES:
A
B
E
L
L
D
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L1
DETAIL A
PIN ONE
REFERENCE
ALTERNATE
CONSTRUCTIONS
MILLIMETERS
DIM MIN
MAX
0.80
0.05
2X
0.10
C
A
A1
A3
b
0.70
0.00
0.20 REF
A3
EXPOSED Cu
MOLD CMPD
2X
0.10
C
0.25
0.35
TOP VIEW
D
D2
E
3.00 BSC
2.20
2.40
DETAIL B
A
3.00 BSC
A1
0.10
0.08
C
E2
e
K
L
L1
1.40
0.65 BSC
0.45 REF
0.20
−−−
1.60
A3
C
DETAIL B
ALTERNATE
CONSTRUCTIONS
0.40
0.15
C
A1
NOTE 4
SEATING
PLANE
SIDE VIEW
D2
DETAIL A
8X L
1
4
E2
5
8
8X
b
e
0.10
0.05
C
C
A
B
NOTE 3
BOTTOM VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
8X
0.53
2.46
PACKAGE
OUTLINE
3.30
1.66
1
8X
0.65
PITCH
0.40
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON49350E
WDFN8, 3X3, 0.65P
PAGE 1 OF 1
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