CS51024EN16
更新时间：2024-09-18 14:21:29
品牌：ONSEMI
描述：1A SWITCHING CONTROLLER, 1000kHz SWITCHING FREQ-MAX, PDIP16, 0.300 INCH, PLASTIC, DIP-16
概述
规格参数
数据手册CS51024EN16 概述
1A SWITCHING CONTROLLER, 1000kHz SWITCHING FREQ-MAX, PDIP16, 0.300 INCH, PLASTIC, DIP-16 开关式稳压器或控制器
CS51024EN16 规格参数
| 是否Rohs认证： | 不符合 | 生命周期： | Obsolete |
| 零件包装代码： | DIP | 包装说明： | DIP, DIP16,.3 |
| 针数： | 16 | Reach Compliance Code： | not_compliant |
| ECCN代码： | EAR99 | HTS代码： | 8542.39.00.01 |
| 风险等级： | 5.82 | 模拟集成电路 - 其他类型： | SWITCHING CONTROLLER |
| 控制模式： | CURRENT-MODE | 控制技术： | PULSE WIDTH MODULATION |
| 最大输入电压： | 20 V | 最小输入电压： | 8.2 V |
| 标称输入电压： | 14 V | JESD-30 代码： | R-PDIP-T16 |
| JESD-609代码： | e0 | 长度： | 19.18 mm |
| 功能数量： | 1 | 端子数量： | 16 |
| 最高工作温度： | 85 °C | 最低工作温度： | -40 °C |
| 最大输出电流： | 1 A | 封装主体材料： | PLASTIC/EPOXY |
| 封装代码： | DIP | 封装等效代码： | DIP16,.3 |
| 封装形状： | RECTANGULAR | 封装形式： | IN-LINE |
| 峰值回流温度（摄氏度）： | NOT SPECIFIED | 认证状态： | Not Qualified |
| 座面最大高度： | 4.07 mm | 子类别： | Switching Regulator or Controllers |
| 表面贴装： | NO | 切换器配置： | SINGLE |
| 最大切换频率： | 1000 kHz | 技术： | BIPOLAR |
| 温度等级： | INDUSTRIAL | 端子面层： | Tin/Lead (Sn/Pb) |
| 端子形式： | THROUGH-HOLE | 端子节距： | 2.54 mm |
| 端子位置： | DUAL | 处于峰值回流温度下的最长时间： | NOT SPECIFIED |
| 宽度： | 7.62 mm | Base Number Matches： | 1 |
CS51024EN16 数据手册
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PDF下载CS51021/CS51023
CS51022/CS51024
Enhanced Current Mode
PWM Controller
Description
Features
The CS51021/ 22/ 23/ 24 Fixed
Frequency PWM Current Mode
Controller family provides all neces- ing, current slope compensation,
sary features required for AC-DC or accurate duty cycle control and an
threshold overcurrent protection,
current sense leading edge blank-
ꢀ 75µA Max. Startup Current
ꢀ Fixed Frequency Current
Mode Control
DC-DC primary side control.
Several features are included elimi-
nating the additional components
externally available 5V reference.
The CS51021 and CS51023 feature
bidirectional synchronization capa-
ꢀ 1MHz Switching Frequency
ꢀ Undervoltage Protection
Monitor
needed to implement them external- bility, while the CS51022 and
ꢀ Overvoltage Protection
Monitor with
ly. In addition to low start-up cur-
rent (75µA) and high frequency
operation capability, the CS51021/
22/ 23/ 24 family includes overvolt-
age and undervoltage monitoring,
externally programmable dual
CS51024 offer a sleep mode with
100µA maximum IC current con-
sumption. The CS51021/ 22/ 23/ 24
family is available in a 16 lead nar-
row body SO package.
Programmable Hysteresis
ꢀ Programmable Dual
Threshold Overcurrent
Protection with Delayed
Restart
ꢀ Programmable Soft Start
Device
Sleep/Synch
VCC Start/Stop
8.25V/ 7.7V
8.25V/ 7.7V
13V/ 7.7V
ꢀ Accurate Maximum Duty
Cycle Limit
CS51021
CS51022
CS51023
CS51024
Synch
Sleep
Synch
Sleep
ꢀ Programmable Slope
Compensation
ꢀ Leading Edge Current
13V/ 7.7V
Sense Blanking
ꢀ 1A Sink/Source Gate Drive
ꢀ Bidirectional Synchronization
(CS51021/23)
Typical Application Diagram
100
V
IN
(36V to 72V)
ꢀ 50ns PWM Propagation
PGND
BAS21
1µF
51k
Delay
18V
SYNC/SLEEP
22µF
ꢀ 100µA Max Sleep Current
11V
100:1
10K
0.1µF
FZT688
2:5
MBRB2060CT
200K,1%
4:1
(CS51022/24)
10
24.3K
1%
V
OUT
(5V/5A)
10
VC
VREF
VCC
UV
0.01µF
4700pF
51K
2.49K,1%
BA521
22K
10K
100µF
100µF
680pF
COMP
Package Options
OV
SGND
100pF
VFB
ISET
RTCT
16 Lead SO Narrow & PDIP
SLOPE
GATE
ISENSE
IRF6345
10
SYNC/
SLEEP
CSS
6.98k,
1%
1
6.98k,
1%
100
100p
330pF
PGnd
V
C
GATE
SENSE
LGnd U1
10
62
0.01µF
470pF
I
PGnd
SLEEP
or SYNC
SLOPE
V
V
CC
0.1µF
5.1K
REF
TL431
1K
2K, 1%
1000pF
LGnd
SS
UV
OV
180
2K,1%
10K
R C
COMP
T
T
MOC81025
I
SET
V
1K
FB
Consult factory for other package options.
36-72V to 5V, 5A DC-DC Convertor
ON Semiconductor
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885–3600 Fax: (401)885–5786
N. American Technical Support: 800-282-9855
Web Site: www.onsemi.com
September, 2000 - Rev. 13
1
Absolute Maximum Ratings
Power Supply Voltage, VCC ............................................................................................................................................-0.3V, 20V
Driver Supply Voltage, VC ..............................................................................................................................................-0.3V, 20V
SYNC, SLEEP, RTCT, SOFT START, VFB, SLOPE, ISENSE, UV, OV, ISET (Logic Pins).......................................-0.25V to VREF
Peak GATE Output Current.........................................................................................................................................................1A
Steady State Output Current..................................................................................................................................................± 0.2A
Operating Junction Temperature, TJ..................................................................................................................................... 150°C
Storage Temperature Range, TS...................................................................................................................................-65 to 150°C
ESD (Human Body Model).........................................................................................................................................................2kV
Lead Temperature Soldering: Reflow (SMD styles only).............................................60 sec. max above 183°C, 230°C peak
Electrical Characteristics: Unless otherwise stated, specifications apply for -40°C < TA < 85°C, -40°C < TJ < 150°C,
3V < VC < 20V, 8.2V < VCC < 20V, RT = 12kΩ, CT = 390pF.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ꢀ Under Voltage Lockout
START Threshold (CS51021/ 22)
START Threshold (CS51023/ 24)
STOP Threshold
7.95
12.4
7.4
8.25
13
8.8
13.4
8.2
1.00
6
V
V
7.7
0.75
5
V
Hysteresis (CS51021/ 22)
Hysteresis (CS51023/ 24)
0.50
4
V
V
I
I
I
I
CC @ Startup (CS51021/ 22)
CC @ Startup (CS51023/ 24)
CC Operating (CS51021/ 23)
CC Operating (CS51022/ 24)
VCC < UVSTART Threshold
VCC < UVSTART Threshold
40
75
µA
45
7
75
9
µA
mA
mA
mA
6
8
IC Operating
Includes 1nF Load
7
12
ꢀ Voltage Reference
Initial Accuracy
Total Accuracy
T
A = 25C, IREF = 2mA, VCC = 14V (Note1) 4.95
5
5
6
6
5.05
5.15
20
V
V
1mA<IREF<10mA
8.2V < VCC < 18V, IREF = 2mA
1mA < IREF < 10mA
4.9
Line Regulation
Load Regulation
mV
mV
15
NOISE Voltage
OP Life Shift
(Note 1)
50
4
uV
mV
V
T=1000 Hours (Note 1)
Force VREF
20
FAULT Voltage
.92 × VREF .95 × VREF .97 × VREF
OK Voltage
Force VREF
.94 × VREF .96 × VREF .98 × VREF
V
OK Hysteresis
Current Limit
Force VREF
Force VREF
50
105
160
mV
mA
-20
ꢀ Error Amplifier
Initial Accuracy
TA=25°C, IREF = 2mA, VCC = 14V,
2.465
2.440
2.515
2.565
V
V
FB = COMP (Note 1)
FB = COMP
Reference Voltage
V
2.515
-0.2
2.590
-2
V
VFB Leakage Current
VFB = 0V
µA
Open Loop Gain
1.4V < COMP < 4V (Note 1)
(Note 1)
60
1.5
2
90
2.5
6
dB
MHz
mA
Unity Gain Bandwidth
COMP Sink Current
COMP = 1.5V, VFB = 2.7V
COMP Source Current
COMP = 1.5V, VFB = 2.3V
2
-0.2
-0.5
mA
Electrical Characteristics: -40°C < TA < 85°C, -40°C < TJ < 150°C, 3V < VC < 20V, 8.2V < VCC < 20V,
RT = 12kΩ, CT = 390pF, unless otherwise stated
PARAMETER
ꢀ Error Amplifier continued
COMP High Voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
FB = 2.3V
FB = 2.7V
4.35
0.4
4.8
0.8
5
V
V
COMP Low Voltage
V
1.2
PS Ripple Rejection
SS Clamp, VCOMP
FREQ = 120Hz (Note 1)
60
85
dB
V
VSS=2.5V, VFB = 0V, ISET = 2V
2.4
2.5
2.6
I
LIM(SET) Clamp
(Note 1)
0.95
230
1
1.15
V
ꢀ Oscillator
Accuracy
RT = 12k, CT = 390pF
255
2
280
3
kHz
%
Voltage Stability
Temperature Stability
Delta Frequency 8.2V < VCC < 20V
T
MIN < TA < TMAX (Note1)
8
%
Min Charge & Discharge Time
Duty Cycle Accuracy
(Note1)
0.333
70
µs
%
RT = 12k, CT = 390pF
77
83
Peak Voltage
(Note 1)
3
V
V
V
Valley Voltage
(Note 1)
1.5
1.4
Valley Clamp Voltage
10k Resistor to ground on RTCT
1.2
1.6
Discharge Current
Discharge Current
0.8
1
1
1.2
mA
mA
TA=25°C (Note 1)
0.925
1.075
ꢀ Synchronization (CS51021/23)
Input Threshold
1.0
160
3.5
1.5
260
4.3
2.7
360
4.8
V
ns
V
Output Pulsewidth
Output High Voltage
I
SYNC = 100µA
Input Resistance
Drive Delay
(Note 1)
35
80
70
120
2
140
150
3.5
kΩ
ns
SYNC to GATE RESET
1k Load
Output Drive Current
1.25
mA
ꢀ SLEEP (CS51022/24)
SLEEP Input Threshold
SLEEP Input Current
Active High
1.0
11
1.5
25
2.7
46
V
V
SLEEP = 4V
µA
I
CC @ SLEEP
VCC ≤ 15V
50
100
µA
ꢀ GATE Driver
HIGH Voltage
Measure VC-GATE, VC = 10V, 150mA Load
1.5
2.2
V
LOW Voltage
Measure GATE-PGnd, 150mA SINK
VC = 20V, 1nF
1.2
1.5
16
V
V
HIGH Voltage Clamp
11
13.5
LOW Voltage Clamp
Peak Current
Measured at 10mA Output Current
VC = 20V, 1nF (Note 1)
0.6
1
0.8
V
A
UVL Leakage
RISE Time
VC = 20V, measured at 0V
-1
-50
µA
ns
Load = 1nF, 1V < GATE < 9V,
VC = 20V, TA = 25°C
60
100
FALL Time
Load = 1nF, 9V > GATE > 1V, VC = 20V
15
40
ns
3
Electrical Characteristics: Unless otherwise stated, specifications apply for -40°C < TA < 85°C, -40°C < TJ < 150°C,
3V < VC < 20V, 8.2V < VCC < 20V, RT = 12kΩ, CT = 390pF.
PARAMETER
ꢀ SLOPE Compensation
Charge Current
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SLOPE = 2V
-63
-53
-43
µA
COMP Gain
Fraction of slope voltage added
to ISENSE (Note 1)
0.095
0.100
0.105
V/ V
Discharge Voltage
SYNC = 0V
0.1
0.2
V
ꢀ Current Sense
OFFSET Voltage
(Note 1)
0.09
0.10
55
0.11
160
2.2
V
ns
Blanking Time
Blanking Disable Voltage
Second Current Threshold Gain
Adjust VFB
1.8
2
V
1.21
1.33
5
1.45
V/ V
kΩ
ns
I
SENSE Input Resistance
Minimum On Time
Gain
GATE High to Low
(Note 1)
30
70
110
0.78
0.80
0.82
V/ V
ꢀ OV & UV Voltage Monitors
OV Monitor Threshold
OV Hysteresis Current
UV Monitor Threshold
UV Monitor Hysteresis
2.4
-10
1.38
25
2.5
-12.5
1.45
75
2.6
-15
V
µA
V
1.52
100
mV
ꢀ SOFT START (SS)
Charge Current
SS = 2V
SS = 2V
-70
250
4.4
-55
1000
4.7
-40
µA
µA
V
Discharge Current
Charge Voltage, VSS
Discharge Voltage, VSS
5
0.25
0.27
0.30
V
Note 1: Guaranteed by Design, not 100% tested in production.
Package Pin Description
PACKAGE PIN #
PIN SYMBOL
FUNCTION
16L PDIP & SO Narrow
1
2
GATE
ISENSE
External power switch driver with 1.0A peak capability.
Current sense amplifier input.
3
SYNC
Bi-directional synchronization. Locks to the highest frequency.
(CS51021/ 23)
3
SLEEP
Active high chip disable. In sleep mode, VREF and GATE are
turned off.
(CS51022/ 24)
4
SLOPE
Additional slope to the current sense signal. Internal current
source charges the external capacitor.
5
6
UV
OV
Undervoltage protection monitor.
Overvoltage protection monitor.
4
Package Pin Description: continued
PIN SYMBOL
PACKAGE PIN #
FUNCTION
16L PDIP & SO Narrow
7
RTCT
Timing resistor RT and capacitor CT determine oscillator frequen-
cy and maximum duty cycle, DMAX
.
8
ISET
Voltage at this pin sets pulse-by-pulse overcurrent threshold, and
second threshold (1.33 times higher) with Soft Start retrigger (hic-
cup mode).
9
VFB
Feedback voltage input. Connected to the error amplifier invert-
ing input.
10
11
COMP
SS
Error amplifier output. Frequency compensation network is usu-
ally connected between COMP and VFB pins.
Charging external capacitor restricts error amplifier output volt-
age during the start or fault conditions (hiccup).
12
13
LGnd
VREF
Logic ground.
5.0V reference voltage output.
14
VCC
Logic supply voltage.
15
16
PGnd
VC
Output power stage ground connection.
Output power stage supply voltage.
Block Diagram
VCC
VREF
Vcc_OK
START
STOP
V
= 5V
REF
-
+
LGnd
VREF_OK
VC
+
SLEEP
4.75V
200ns
4.3V
SYNC
RTCT
OSC
G
2
GATE
Q
S
R
D
F
4
ZD
1
1
SS
Clamp
G
13.5V
1
D
2
ISET
Clamp
COMP
VFB
PGnd
D
3
+
20k
2.5V
E/A
-
VREF
PWM
Comp
D
1
10k
VREF
55µA
VFB
Monitor
SS
53µA
+
–
SS
Monitor
G
4
2V
DISABLE
+
×
×
0.1V
SLOPE
4.7V
–
55ns
Blank
0.1
+
–
∑
I
SENSE
VISense
0.8
Q
2
2nd
Threshold
G
3
1.33
Discharge
Latch
FAULT
×
ISET
OV
VREF
12.5µA
UV
UV
Monitor
OV
Monitor
+
–
+
–
1.45V
2.5V
Figure 1: CS51021/22/23/24 Block Diagram
5
Circuit Description
Blanking is disabled when VFB is less than 2V so that the
200ns
4.3V
minimum on-time of the controller does not have an addi-
tional 55ns of delay time during fault conditions. For the
remaining portion of the switching period, the current
sense signal, combined with a fraction of the slope com-
pensation voltage, is applied to the positive input of the
PWM comparator where it is compared with the divided
by three error amplifier output voltage. The pulse-by-
pulse overcurrent protection threshold is set by the volt-
age at the ISET pin. This voltage is passed through the ISET
Clamp and appears at the non-inverting input of the PWM
comparator, limiting its dynamic range according to the
following formula:
SYNC
R C
T
T
T
T
CH
DIS
0V
V
SLOPE
SLOPE
IS
0V
0V
Overcurrent Threshold= 0.8 × VI(SENSE) +0.1V + 0.1 VSLOPE
where
IS + 0.1 SLOPE
IS
V
COMP
VI(SENSE) is voltage at the ISENSE pin
and
PWM COMP
55ns Blanking
0V
0V
V
SLOPE is voltage at the SLOPE pin.
GATE
During extreme overcurrent or short circuit conditions,
the slope of the current sense signal will become much
steeper than during normal operation. Due to loop propa-
gation delay, the sensed signal will overshoot the pulse-
by-pulse threshold eventually reaching the second over-
current protection threshold which is 1.33 times higher
than the first threshold and is described by the following
equation:
V
DS
V
IN
0V
Figure 2: Typical Waveforms
2nd Threshold = 1.33 × VI(SET)
Exceeding the second threshold will reset the Soft Start
capacitor CSS and reinitiate the Soft Start sequence, repeat-
ing for as long as the fault condition persists.
Theory of Operation
Powering the IC
The IC has two supply and two ground pins. VC and
Soft Start
PGnd pins provide high speed power drive for the exter-
nal power switch. VCC and LGnd pins power the control
portion of the IC. The internal logic monitors the supply
voltage, VCC. During abnormal operating conditions, the
output is held low. The CS51021/ 22/ 23/ 24 requires only
75µA of startup current.
During power up, when the output filter capacitor is dis-
charged and the output voltage is low, the voltage across
the Soft Start capacitor (VSS) controls the duty cycle. An
internal current source of 55µA charges CSS. The maxi-
mum error amplifier output voltage is clamped by the SS
Clamp. When the Soft Start capacitor voltage exceeds the
error amplifier output voltage, the feedback loop takes
over the duty cycle control. The Soft Start time can be esti-
mated with the following formula:
Voltage Feedback
The output voltage is monitored via the VFB pin and is
compared with the internal 2.5V reference. The error
amplifier output minus one diode drop is divided by 3
and connected to the negative input of the PWM compara-
tor. The positive input of the PWM comparator is connect-
ed to the modified current sense signal. The oscillator
turns the external power switch on at the beginning of
each cycle. When current sense ramp voltage exceeds the
reference side of PWM comparator, the output stage latch-
es off. It is turned on again at the beginning of the next
oscillator cycle.
tSS = 9 × 104 × CSS
The Soft Start voltage, VSS, charges and discharges
between 0.25V and 4.7V.
Slope Compensation
DC-DC converters with current mode control require a
current sense signal with slope compensation to avoid
instability at duty cycles greater than 50%. Slope capacitor
CS is charged by an internal 53µA current source and is
Current Sense and Protection
discharged during the oscillator discharge time. The slope
compensation voltage is divided by 10 and is added to the
current sense voltage, VI(SENSE). The signal applied to the
The current is monitored at the ISENSE pin. The
CS51021/ 22/ 23/ 24 has leading edge blanking circuitry
that ignores the first 55ns of each switching period.
6
Circuit Description: continued
input of the PWM comparator is a combination of these
R1
R2
R3
VIN
dVSLOPE
dt
two voltages. The slope compensation,
lated using the following formula:
, is calcu-
VUV
Figure 4: UV/OV Monitor Divider
VOV
dVSLOPE
dt
53µA
CS
= 0.1 ×
To calculate the OV/ UV resistor divider:
It should be noted that internal capacitance of the IC will
cause an error when determining slope compensation
capacitance CS. This error is typically small for large val-
ues of CS, but increases as CS becomes small and compara-
ble to the internal capacitance. The effect is apparent as a
reduction in charging current due to the need to charge
the internal capacitance in parallel with CS. Figure 3 shows
a typical curve indicating this decrease in available charg-
ing current.
1. Solve for R3, based on OV hysteresis requirements.
V
OV(HYST) × 2.5V
R3 =
’
VMAX × 12.5µA
where VOV(HYST) is the desired amount of overvoltage hys-
teresis, and VMAX is the input voltage at which the supply
will shut down.
2. Find the total impedance of the divider.
60
55
50
45
40
35
30
25
20
VMAX × R3
RTOT = R1 + R2 + R3 =
2.5
3. Determine the value of R2 from the UV threshold condi-
tions.
1.45 × RTOT
R2 =
− R3,
VMIN
where VMIN is the UV voltage at which the supply will
shut down.
4. Calculate R1.
10
100
1000
Compensation Cap (pF)
R1 = RTOT − R2 − R3
5. The undervoltage hysteresis is given by:
Figure 3: The slope compensation pin charge current reduces when a
small capacitor is used.
VMIN × 0.075
VUV(HYST)
=
1.45
Undervoltage (UV) and Overvoltage (OV) Monitor
Synchronization
Two independent comparators monitor OV and UV con-
ditions. A string of three resistors is connected in series
between the monitored voltage (usually the input voltage)
and ground (see Figure 4). When voltage at the OV pin
exceeds 2.5V, an overvoltage condition is detected and
GATE shuts down. An internal 12.5µA current source
turns on and feeds current into the external resistor, R3,
creating a hysteresis determined by the value of this resis-
tor (the higher the value, the greater the hysteresis). The
hysteresis voltage of the OV monitor is determined by the
following formula:
A bi-directional synchronization is provided to synchro-
nize several controllers. When SYNC pins are connected
together, the converters will lock to the highest switching
frequency. The fastest controller becomes the master, pro-
ducing a 4.3V, 200ns pulse train. Only one, the highest fre-
quency SYNC signal, will appear on the SYNC line. For
reliable operation, the master frequency should be approx-
imately 20% higher than the free running slave frequency.
Sleep
The sleep input is an active high input. The CS51022/ 51024
is placed in sleep mode when SLEEP is driven high. In
sleep mode, the controller and MOSFET are turned off.
Connect to Gnd for normal operation. The sleep mode
operates at VCC ≤ 15V.
V
OV(HYST) = 12.5µA × R3
where R3 is a resistor connected from the OV pin to ground.
When the monitored voltage is low and the UV pin is less
than 1.45V, GATE shuts down. The UV pin has fixed 75mV
hysteresis.
Oscillator and Duty Cycle Limit
Both OV and UV conditions are latched until the Soft Start
capacitor is discharged. This way, every time a fault con-
dition is detected the controller goes through the power
up sequence.
The switching frequency is set by RT and CT connected to
the RTCT pin. CT charges and discharges between 3V and
1.5V.
7
Circuit Description: continued
100
The maximum duty cycle is set by the ratio of the on time,
ON, and the whole period, T = tON + tOFF. Because the
8
7
t
6
timing capacitor’s discharge current is trimmed, the maxi-
mum duty cycle is well defined. It is determined by the
ratio between the timing resistor RT and the timing capaci-
tor CT. Refer to figures 5 and 6 to select appropriate values
for RT and CT.
5
90
80
70
60
4
3
2
1. C = 47pF
2. C = 100pF
T
3. C = 150pF
T
T
1
fSW
=
; TSW = tCH + tDIS
TSW
4. C = 220pF
T
1
5. C = 390pF
T
6. C = 470pF
T
7. C = 560pF
T
8. C = 680pF
T
2500
2000
1500
1000
50
1
40
1. C = 47pF
T
5
10
15
20
25
30
35
(kΩ)
40
45
50
55
2. C = 100pF
T
R
T
3. C = 150pF
T
4. C = 220pF
T
5. C = 390pF
T
Figure 6: Duty Cycle vs. RT for Discrete Capacitor Values.
6. C = 470pF
T
7. C = 560pF
T
2
8. C = 680pF
T
3
4
500
5
6
7
8
0
5
10
15
20
25
30
35
40
45
50
R
T
(kΩ)
Figure 5: Frequency vs. RT for Discrete Capacitor Values.
8
Package Specification
PACKAGE THERMAL DATA
PACKAGE DIMENSIONS IN mm (INCHES)
D
Thermal Data
16L SO Narrow
PDIP
Lead Count
Metric
English
Max Min
.394 .386
RΘJC
typ
28
42
°C/ W
°C/ W
Max
Min
9.80
RΘJA
typ
115
80
16L SO Narrow
16L PDIP
10.00
19.69
18.67 .775 .735
Plastic DIP (N); 300 mil wide
Surface Mount Narrow Body (D); 150 mil wide
7.11 (.280)
6.10 (.240)
6.20 (.244)
5.80 (.228)
4.00 (.157)
3.80 (.150)
1.77 (.070)
1.14 (.045)
8.26 (.325)
7.62 (.300)
2.54 (.100) BSC
3.68 (.145)
2.92 (.115)
0.51 (.020)
1.27 (.050) BSC
1.75 (.069) MAX
0.33 (.013)
0.39 (.015)
MIN.
.356 (.014)
.203 (.008)
1.57 (.062)
1.37 (.054)
.558 (.022)
.356 (.014)
Some 8 and 16 lead
packages may have
1/2 lead at the end
of the package.
0.25 (.010)
0.19 (.008)
1.27 (.050)
0.40 (.016)
REF: JEDEC MS-001
D
0.25 (0.10)
0.10 (.004)
All specs are the same.
D
REF: JEDEC MS-012
Ordering Information
Part Number
CS51021ED16
CS51021EDR16
CS51022ED16
CS51022EDR16
CS51023ED16
CS51023EDR16
CS51024ED16
CS51024EDR16
CS51021EN16
CS51022EN16
CS51023EN16
CS51024EN16
Description
16L SO Narrow
16L SO Narrow (tape & reel)
16L SO Narrow
16L SO Narrow (tape & reel)
16L SO Narrow
16L SO Narrow (tape & reel)
16L SO Narrow
16L SO Narrow (tape & reel)
16L PDIP
ON Semiconductor and the ON Logo are trademarks of
Semiconductor Components Industries, LLC (SCILLC). ON
Semiconductor reserves the right to make changes without
further notice to any products herein. For additional infor-
mation and the latest available information, please contact
your local ON Semiconductor representative.
16L PDIP
16L PDIP
16L PDIP
© Semiconductor Components Industries, LLC, 2000
9
Notes
Notes
Notes
CS51024EN16 相关器件
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| CS5102A-BLZ | CIRRUS | 16-bit, 100 kSps / 20 kSps A/D Converters | 获取价格 |
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| CS5102A-BLZR | CIRRUS | ADC, Successive Approximation, 16-Bit, 1 Func, 2 Channel, Serial Access, CMOS, PQCC28, MS-047, LCC-28 | 获取价格 |
|
| CS5102A-BP | CIRRUS | 16-Bit, 100kHz/ 20kHz A/D Converters | 获取价格 |
|
| CS5102A-JL | CIRRUS | 16-Bit, 100kHz/ 20kHz A/D Converters | 获取价格 |
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