概述
规格参数
数据手册
替代型号CS51221EDR16G 概述
Enhanced Voltage Mode PWM Controller 增强型电压模式PWM控制器 稳压芯片 开关式稳压器或控制器
CS51221EDR16G 规格参数
| 是否无铅： | 不含铅 | 是否Rohs认证： | 符合 |
| 生命周期： | Active | 零件包装代码： | SOIC |
| 包装说明： | SOP, SOP16,.25 | 针数： | 16 |
| Reach Compliance Code： | compliant | ECCN代码： | EAR99 |
| HTS代码： | 8542.39.00.01 | Factory Lead Time： | 1 week |
| 风险等级： | 5.22 | 模拟集成电路 - 其他类型： | SWITCHING CONTROLLER |
| 控制模式： | VOLTAGE-MODE | 控制技术： | PULSE WIDTH MODULATION |
| 最大输入电压： | 15 V | 最小输入电压： | 4.7 V |
| JESD-30 代码： | R-PDSO-G16 | JESD-609代码： | e3 |
| 长度： | 9.9 mm | 湿度敏感等级： | 1 |
| 功能数量： | 1 | 端子数量： | 16 |
| 最高工作温度： | 85 °C | 最低工作温度： | -40 °C |
| 最大输出电流： | 1 A | 封装主体材料： | PLASTIC/EPOXY |
| 封装代码： | SOP | 封装等效代码： | SOP16,.25 |
| 封装形状： | RECTANGULAR | 封装形式： | SMALL OUTLINE |
| 峰值回流温度（摄氏度）： | 260 | 认证状态： | Not Qualified |
| 座面最大高度： | 1.75 mm | 子类别： | Switching Regulator or Controllers |
| 表面贴装： | YES | 切换器配置： | SINGLE |
| 最大切换频率： | 1000 kHz | 温度等级： | INDUSTRIAL |
| 端子面层： | Tin (Sn) | 端子形式： | GULL WING |
| 端子节距： | 1.27 mm | 端子位置： | DUAL |
| 处于峰值回流温度下的最长时间： | 40 | 宽度： | 3.9 mm |
CS51221EDR16G 数据手册
通过下载CS51221EDR16G数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载CS51221
Enhanced Voltage Mode
PWM Controller
The CS51221 fixed frequency feed forward voltage mode PWM
controller contains all of the features necessary for basic voltage mode
operation. This PWM controller has been optimized for high
frequency primary side control operation. In addition, this device
includes such features as: Soft−Start, accurate duty cycle limit control,
less than 50mA startup current, over and undervoltage protection, and
bidirectional synchronization. The CS51221 is available in a 16 lead
SOIC narrow surface mount package.
http://onsemi.com
SOIC−16
D SUFFIX
CASE 751B
16
1
TSSOP−16
DTB SUFFIX
CASE 948F
Features
16
• 1.0 MHz Frequency Capability
• Fixed Frequency Voltage Mode Operation, with Feed Forward
• Thermal Shutdown
• Undervoltage Lock−Out
• Accurate Programmable Max Duty Cycle Limit
• 1.0 A Sink/Source Gate Drive
1
PIN CONNECTIONS AND
MARKING DIAGRAM
1
16
GATE
V
C
I
PGND
SENSE
• Programmable Pulse−By−Pulse Overcurrent Protection
• Leading Edge Current Sense Blanking
• 75 ns Shutdown Propagation Delay
• Programmable Soft−Start
SYNC
V
V
CC
FF
UV
OV
REF
LGND
SS
COMP
R C
T
T
I
V
FB
SET
• Undervoltage Protection
• Overvoltage Protection with Programmable Hysteresis
• Bidirectional Synchronization
1
16
• 25 ns GATE Rise and Fall Time (1.0 nF Load)
• 3.3 V 3% Reference Voltage Output
• Pb−Free Packages are Available*
CS51221= Specific Device Code
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
A
G
= Pb−Free Package
ORDERING INFORMATION
†
Device
Package
Shipping
CS51221ED16
SOIC−16 48 Units / Rail
CS51221ED16G
SOIC−16 48 Units / Rail
(Pb−Free)
CS51221EDR16
SOIC−16 2500 Tape & Reel
CS51221EDR16G
SOIC−16 2500 Tape & Reel
(Pb−Free)
CS51221EDTB16G TSSOP−16 96 Units / Rail
(Pb−Free)
CS51221EDTB16R2G TSSOP−16 2500 Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
September, 2005 − Rev. 8
CS51221/D
CS51221
C S 5 1 2 2 1
Figure 1. Application Diagram, 36 V−72 V to 5.0 V/5.0 A Converter
http://onsemi.com
2
CS51221
MAXIMUM RATINGS
Rating
Value
Unit
Internally
Limited
Operating Junction Temperature, T
Lead Temperature Soldering:
−
J
Reflow: (SMD styles only) (Note 1)
230 peak
−65 to +150
2.0
°C
°C
kV
Storage Temperature Range, T
S
ESD (Human Body Model)
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. 60 second maximum above 183°C.
MAXIMUM RATINGS
Pin Name
Gate Drive Output
Current Sense Input
Timing Resistor/Capacitor
Feed Forward
Pin Symbol
V
V
I
I
SINK
MAX
MIN
SOURCE
GATE
15 V
6.0 V
6.0 V
6.0 V
6.0 V
6.0 V
6.0 V
6.0 V
6.0 V
6.0 V
6.0 V
15 V
15 V
6.0 V
N/A
−0.3 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
N/A
1.0 A Peak, 200 mA DC
1.0 mA
1.0 A Peak, 200 mA DC
I
1.0 mA
10 mA
SENSE
R C
T
1.0 mA
T
FF
1.0 mA
25 mA
Error Amp Output
Feedback Voltage
Sync Input
COMP
10 mA
20 mA
V
FB
1.0 mA
1.0 mA
SYNC
UV
10 mA
10 mA
Undervoltage
1.0 mA
1.0 mA
Overvoltage
OV
1.0 mA
1.0 mA
Current Set
I
1.0 mA
1.0 mA
SET
Soft−Start
SS
1.0 mA
10 mA
Logic Section Supply
Power Section Supply
Reference Voltage
Power Ground
V
CC
10 mA
50 mA
V
C
10 mA
1.0 A Peak, 200 mA DC
10 mA
V
REF
lnternally Limited
1.0 A Peak, 200 mA DC
N/A
PGND
LGND
N/A
Logic Ground
N/A
N/A
N/A
ELECTRICAL CHARACTERISTICS (−40°C < T < 85°C; −40°C < T < 125°C; 3.0 V < V < 15 V; 4.7 V < V < 15 V;
A
J
C
CC
R = 12 k; C = 390 pF; unless otherwise specified.)
T
T
Characteristic
Test Conditions
Min
Typ
Max
Unit
Start/Stop Voltages
Start Threshold
Stop Threshold
Hysteresis
−
−
4.4
3.2
400
−
4.6
3.8
850
38
4.7
4.1
V
V
Start−Stop
1400
75
mV
mA
I
@ Startup
V
CC
< UVL Start Threshold
CC
Supply Current
I
I
I
Operating
−
−
−
−
9.5
12
14
18
mA
mA
mA
CC
Operating
Operating
1.0 nF Load on GATE
No Switching
C
C
2.0
4.0
http://onsemi.com
3
CS51221
ELECTRICAL CHARACTERISTICS (−40°C < T < 85°C; −40°C < T < 125°C; 3.0 V < V < 15 V; 4.7 V < V < 15 V;
A
J
C
CC
R = 12 k; C = 390 pF; unless otherwise specified.)
T
T
Characteristic
Test Conditions
Min
Typ
Max
Unit
Reference Voltage
Total Accuracy
Line Regulation
Load Regulation
Noise Voltage
Op Life Shift
0 mA < I
0 mA < I
< 2.0 mA
−
3.2
−
3.3
6.0
6.0
50
3.4
20
V
REF
mV
mV
mV
mV
V
< 2.0 mA
−
15
REF
10 Hz < F < 10 kHz. Note 2
−
−
T = 1000 Hrs. Note 2
−
4.0
2.95
3.05
100
40
20
Fault Voltage
−
−
−
−
2.8
2.9
30
2.0
3.1
3.2
150
100
V
V
Voltage
V
REF(OK)
REF(OK)
Hysteresis
mV
mA
Current Limit
Error Amp
Reference Voltage
V
V
= COMP
= 1.2 V
1.234
−
1.263
1.3
−
1.285
2.0
−
V
mA
dB
MHz
mA
mA
V
FB
V
FB
Input Current
FB
Open Loop Gain
Unity Gain Bandwidth
COMP Sink Current
COMP Source Current
COMP High Voltage
COMP Low Voltage
PSRR
Note 2
Note 2
60
1.5
3.0
1.0
2.8
75
−
−
COMP = 1.4 V, V = 1.45 V
12
32
FB
COMP = 1.4 V, V = 1.15 V
1.6
3.1
125
85
2.0
3.4
300
−
FB
V
FB
V
FB
= 1.15 V
= 1.45 V
mV
dB
V
Freq = 120 Hz. Note 2
60
SS Clamp, V
SS = 1.4 V, V = 0 V, I = 2.0 V
SET
1.3
1.7
1.4
1.8
1.5
1.9
COMP
FB
COMP Max Clamp
Oscillator
Note 2
V
Frequency Accuracy
Voltage Stability
Temperature Stability
Max Frequency
−
260
−
273
1.0
8.0
−
320
2.0
−
kHz
%
−
−40°C < T < 125°C. (Note 2)
−
%
J
Note 2
1.0
80
−
MHz
%
Duty Cycle
−
85
90
Peak Voltage
Note 2
1.94
0.9
0.85
0.85
2.0
0.95
1.0
1.0
2.06
1.0
1.15
1.15
V
Valley Clamp Voltage
Valley Voltage
−
V
Note 2
V
Discharge Current
Synchronization
Input Threshold
−
mA
−
0.9
200
2.1
35
1.4
320
2.5
70
1.8
450
2.8
V
ns
V
Output Pulse Width
Output High Voltage
Input Resistance
SYNC to Drive Delay
Output Drive Current
−
100 mA Load
−
140
180
2.25
kW
ns
mA
Time from SYNC to GATE Shutdown
100
1.0
140
1.5
R
= 1.0 W
SYNC
2. Guaranteed by design, not 100% tested in production.
http://onsemi.com
4
CS51221
ELECTRICAL CHARACTERISTICS (−40°C < T < 85°C; −40°C < T < 125°C; 3.0 V < V < 15 V; 4.7 V < V < 15 V;
A
J
C
CC
R = 12 k; C = 390 pF; unless otherwise specified.)
T
T
Characteristic
Test Conditions
Min
Typ
Max
Unit
Gate Driver
High Saturation Voltage
Low Saturation Voltage
High Voltage Clamp
Output Current
V
− GATE, V = 10 V, I
= 200 mA
−
−
1.5
1.2
13.5
1.0
1.0
60
2.0
1.5
16
V
V
C
C
SOURCE
GATE − PGND, I
= 200 mA
SINK
−
11
−
V
1.0 nF Load. Note 3
GATE = 0 V
1.25
50
A
Output UVL Leakage
Rise Time
−
mA
ns
ns
V
1.0 nF Load, V = 20 V, 1.0 V < GATE < 9.0 V
−
100
50
C
Fall Time
1.0 nF Load, V = 20 V, 9.0 V < GATE < 1.0 V
−
25
C
Max Gate Voltage During UVL/Sleep
Feed Forward (FF)
Discharge Voltage
Discharge Current
FF to GATE Delay
I
= 500 mA
0.4
0.7
1.0
GATE
I
FF
= 2.0 mA
−
0.3
16
75
0.7
30
V
FF = 1.0 V
2.0
50
mA
ns
−
125
Overcurrent Protection
Overcurrent Threshold
I
= 0.5 V, Ramp I
0.475
50
0.5
90
0.525
125
V
SET
SENSE
I
to GATE Delay
−
ns
SENSE
External Voltage Monitors
Overvoltage Threshold
Overvoltage Hysteresis Current
Undervoltage Threshold
Undervoltage Hysteresis
Soft−Start (SS)
OV Increasing
OV = 2.15 V
1.9
10
2.0
12.5
1.0
75
2.1
15
V
mA
V
UV Increasing
0.95
25
1.05
125
−
mV
Charge Current
SS = 2.0 V
SS = 2.0 V
40
4.0
2.8
0.25
1.15
−
50
5.0
3.0
0.3
1.25
0.1
70
7.0
mA
mA
V
Discharge Current
Charge Voltage
−
−
3.4
Discharge Voltage
0.35
1.35
0.2
V
Soft−Start Clamp Offset
Soft−Start Fault Voltage
Blanking
FF = 1.25 V
V
OV = 2.15 V or LV = 0.85 V
V
Blanking Time
−
50
2.8
2.8
150
3.0
3.0
250
3.3
3.3
ns
V
SS Blanking Disable Threshold
COMP Blanking Disable Threshold
Thermal Shutdown
Thermal Shutdown
V
V
< 1.0
FB
< 1.0, SS > 3.0 V
V
FB
Note 3
Note 3
125
5.0
150
10
180
15
°C
°C
Thermal Hysteresis
3. Guaranteed by design, not 100% tested in production.
http://onsemi.com
5
CS51221
PACKAGE PIN DESCRIPTION
Package
Pin #
Pin
Symbol
Function
1
GATE
External power switch driver with 1.0 A peak capability. Rail to rail output occurs when the capacitive load is
between 470 pF and 10 nF.
2
3
I
Current sense comparator input.
Bidirectional synchronization. Locks to highest frequency.
PWM ramp.
SENSE
SYNC
FF
4
5
UV
Undervoltage protection monitor.
Overvoltage protection monitor.
6
OV
7
R C
T
Timing resistor R and capacitor C determine oscillator frequency and maximum duty cycle, D
.
MAX
T
T
T
8
I
Voltage at this pin sets pulse−by−pulse overcurrent threshold.
Feedback voltage input. Connected to the error amplifier inverting input.
Error amplifier output.
SET
9
V
FB
10
11
12
13
14
15
16
COMP
SS
Charging external capacitor restricts error amplifier output voltage during the power up or fault conditions.
LGND
Logic ground.
V
3.3 V reference voltage output. Decoupling capacitor can be selected from 0.01 mF to 10 mF.
Logic supply voltage.
REF
V
CC
PGND
Output power stage ground.
V
C
Output power stage supply voltage.
http://onsemi.com
6
CS51221
V
CC
2.0 mA (maximum load current)
V
V
REF
3.3 V
−
+
−
UVL
ENABLE
Thermal
Shutdown
V
REF
= 3.3 V
V
REF
OK
+
−
+
3.1 V
C
UV Lockout
Start/Stop
Low Sat
Gate Driver
S
R
Q
GATE
PGND
G1
SYNC
R C
OSC
13.5 V
G2
Q
T
T
2.0 V to 1.0 V Trip Points
V
BG
(1.263 V)
3.0 V
−
+
Max Duty Cycle
(Sat Sense)
V
REF
+
EAMP
50 mA
−
V
FB
SS to 1.8 V Max
+
LGND
PWM
Comp
−
+
−
COMP
FF
ON
Soft−Start Clamp
FF Discharge
V
O
Off
Latching
Discharge
G4
SS
OV
5.0 mA
G3
+
OV Monitor
+
−
Max SS
Det
3.0 V
2.0 V
−
+
I
SET
I
LIM
−
DISABLE
150 ns
Blank
(Sat Sense)
UV Monitor
−
UV
I
SENSE
+
1.0 V
Figure 2. Block Diagram
http://onsemi.com
7
CS51221
APPLICATION INFORMATION
V
OUT
THEORY OF OPERATION
Feed Forward Voltage Mode Control
In conventional voltage mode control, the ramp signal has
fixed rising and falling slope. The feedback signal is derived
solely from the output voltage. Consequently, voltage mode
control has inferior line regulation and audio susceptibility.
Feed forward voltage mode control derives the ramp
signal from the input line, as shown in Figure 3. Therefore,
the ramp of the slope varies with the input voltage. At the
start of each switch cycle, the capacitor connected to the FF
pin is charged through a resistor connected to the input
voltage. Meanwhile, the Gate output is turned on to drive an
external power switching device. When the FF pin voltage
V
COMP
FF
V
IN
R C
T
T
GATE
reaches the error amplifier output V
, the PWM
COMP
Figure 4. Pulse Width Modulated by Output
Current with Constant Input Voltage
comparator turns off the Gate, which in turn opens the
external switch. Simultaneously, the FF capacitor is quickly
discharged to 0.3 V.
Overall, the dynamics of the duty cycle are controlled by
both input and output voltages. As illustrated in Figure 4,
with a fixed input voltage the output voltage is regulated
solely by the error amplifier. For example, an elevated
V
IN
V
COMP
output voltage reduces V
which in turn causes duty
COMP
cycle to decrease. However, if the input voltage varies, the
slope of the ramp signal will react immediately which
provides a much improved line transient response. As an
example shown in Figure 5, when the input voltage goes up,
the rising edge of the ramp signal increases which reduces
duty cycle to counteract the change.
FF
I
OUT
R C
T
T
V
IN
V
OUT
Power Stage
GATE
GATE
R
Figure 5. Pulse Width Modulated by Input Voltage
with Constant Output Current
Latch & Driver
Feedback
Network
Powering the IC & UVL
PWM
The Undervoltage Lockout (UVL) comparator has two
voltage references; the start and stop thresholds. During
FF
FB
COMP
−
+
power−up, the UVL comparator disables V
(which
REF
in−turn disables the entire IC) until the controller reaches its
start threshold. During power−down, the UVL
Error Amplifier
V
CC
+
−
C
comparator allows the controller to operate until the V
CC
stop threshold is reached. The CS51221 requires only 50 mA
during startup. The output stage is held at a low impedance
state in lock out mode.
Figure 3. Feed Forward Voltage Mode Control
During power up and fault conditions, the Soft−Start
clamps the Comp pin voltage and limits the duty cycle. The
power up transition tends to generate temporary duty cycles
much greater than the steady state value due to the low
output voltage. Consequently, excessive current stresses
often take place in the system. Soft−Start technique
alleviates this problem by gradually releasing the clamp on
the duty cycle to eliminate the in−rush current. The duration
The feed forward feature can also be employed to provide
a volt−second clamp, which limits the maximum product of
input voltage and turn on time. This clamp is used in circuits,
such as Forward and Flyback converter, to prevent the
transformer from saturating. Calculations used in the design
of the volt−second clamp are presented in the Design
Guidelines section.
http://onsemi.com
8
CS51221
of the Soft−Start can be programmed through a capacitance
connected to the SS pin. The constant charging current to the
SS pin is 50 mA (typ).
The V
(ok) comparator monitors the 3.3 V V
REF
REF
output and latches a fault condition if V
falls below 3.1 V.
REF
The fault condition may also be triggered when the OV pin
voltage rises above 2.0 V or the UV pin voltage falls below
1.0 V. The undervoltage comparator has a built−in hysteresis
of 75 mV (typ). The hysteresis for the OV comparator is
programmable through a resistor connected to the OV pin.
When an OV condition is detected, the overvoltage
hysteresis current of 12.5 mA (typ) is sourced from the pin.
In Figure 6, the fault condition is triggered by pulling the
UV pin to the ground. Immediately, the SS capacitor is
discharged with 5.0 mA of current (typ) and the GATE output
is disabled until the SS voltage reaches the discharge voltage
of 0.3 V (typ). The IC starts the Soft−Start transition again
if the fault condition has recovered as shown in Figure 6.
However, if the fault condition persists, the SS voltage will
stay at 0.1 V until the removal of the fault condition.
Figure 7. The GATE Output Is Terminated When
the ISENSE Pin Voltage Reaches the Threshold Set
By the ISET Pin. CH2: ISENSE Pin, CH4: ISET Pin,
CH3: GATE Pin
The current sense signal is prone to leading edge spikes
caused by the switching transition. A RC low−pass filter is
usually applied to the current signals to avoid premature
triggering. However, the low pass filter will inevitably
change the shape of the current pulse and also add cost. The
CS51221 uses leading edge blanking circuitry that blocks
out the first 150 ns (typ) of each current pulse. This removes
the leading edge spikes without altering the current
waveform. The blanking is disabled during Soft−Start and
when the V
is saturated high so that the minimum
COMP
on−time of the controller does not have the additional
blanking period. The max SS detect comparator keeps the
blanking function disabled until SS charges fully. The output
of the max Duty Cycle detector goes high when the error
amplifier output gets saturated high, indicating that the
output voltage has fallen well below its regulation point and
the power supply may be underload stress.
Figure 6. The Fault Condition Is Triggered when
the UV Pin Voltage Falls Below 1.0 V. The
Soft−Start Capacitor Is Discharged and the GATE
Output Is Disabled. CH2: Envelop of GATE Output,
CH3: SS Pin with 0.01 mF Capacitor, CH4: UV Pin
Oscillator and Synchronization
The switching frequency is programmable through a RC
network connected to the R C Pin. As shown in Figure 8,
T
T
when the R C pin reaches 2.0 V, the capacitor is discharged
T
T
by a 1.0 mA current source and the Gate signal is disabled.
When the R C pin decreases to 1.0 V, the Gate output is
Current Sense and Overcurrent Protection
T
T
turned on and the discharge current is removed to let the
R C pin ramp up. This begins a new switching cycle. The
C charging time over the switch period sets the maximum
T
The current can be monitored by the I
pulse by pulse current limit. Various techniques, such as a
using current sense resistor or current transformer, can be
pin to achieve
SENSE
T
T
duty cycle clamp which is programmable through the R
adopted to derive current signals. The voltage of the I
pin
T
SET
value as shown in the Design Guidelines. At the beginning
of each switching cycle, the SYNC pin generates a 2.5 V,
320 nS (typ) pulse. This pulse can be utilized to synchronize
other power supplies.
sets the threshold for maximum current. As shown in
Figure 7, when the I pin voltage exceeds the I
voltage, the current limit comparator will reset the GATE
latch flip−flop to terminate the GATE pulse.
SENSE
SET
http://onsemi.com
9
CS51221
DESIGN GUIDELINES
Switch Frequency and Maximum Duty Cycle
Calculations
Oscillator timing capacitor, C , is charged by V
T
REF
through R and discharged by an internal current source.
T
During the discharge time, the internal clock signal sets the
Gate output to the low state, thus providing a user selectable
maximum duty cycle clamp. Charge and discharge times are
determined by following general formulas;
(V
(V
* V
)
VALLEY
REF
+ R C lnǒ
Ǔ
t
C
T T
* V
)
REF
PEAK
(V
* V
* I R )
* I R )
REF
PEAK
d T
+ R C lnǒ
Ǔ
t
d
T T
(V
* V
REF
VALLEY d T
where:
t = charging time;
C
Figure 8. The SYNC Pin Generates a Sync Pulse at
the Beginning of Each Switching Cycle.
t = discharging time;
d
V
V
= valley voltage of the oscillator;
= peak voltage of the oscillator.
VALLEY
CH2: GATE Pin, CH3: RTCT, CH4: SYNC Pin
PEAK
Substituting in typical values for the parameters in the
above formulas, V = 3.3 V, V = 1.0 V, V
=
PEAK
REF
VALLEY
2.0 V, I = 1.0 mA:
d
t
C
+ 0.57R C
T T
1.3 * 0.001R
2.3 * 0.001R
T
T
+ R C lnǒ
Ǔ
t
d
T T
0.57
0.57 ) Inǒ
D
+
max
1.3*0.001R
2.3*0.001R
T
T
Ǔ
It is noticed from the equation that for the oscillator to
function properly, R has to be greater than 2.3 k.
T
Select RC for Feed Forward Ramp
If the line voltage is much greater than the FF pin Peak
Voltage, the charge current can be treated as a constant and
is equal to V /R. Therefore, the volt−second value is
IN
determined by:
V
T
+ (V
* V
) R C
FF(d)
IN
ON
COMP
Figure 9. Operation with External Sync.
CH2: SYNC Pin, CH3: GATE Pin, CH4: RTCT Pin
where:
V
V
= COMP pin voltage;
COMP
= FF pin discharge voltage.
FF(d)
An external pulse signal can feed to the bidirectional
SYNC pin to synchronize the switch frequency. For reliable
operation, the sync frequency should be approximately 20%
higher than free running IC frequency. As show in Figure 9,
when the SYNC pin is triggered by an incoming signal, the
As shown in the equation, the volt−second clamp is set by
the V clamp voltage which is equal to 1.8 V. In
COMP
Forward or Flyback circuits, the volt−second clamp value is
designed to prevent transformers from saturation.
In a buck or forward converter, volt−second is equal to
IC immediately discharges C . The GATE signal is turned
T
V
T
S
OUT
+ ǒ
Ǔ
V
T
ON
on once the R C pin reaches the valley voltage. Because of
IN
T
T
n
the steep falling edge, this valley voltage falls below the
regular 1.0 V threshold. However, the R C pin voltage is
n = transformer turns ratio, which is a constant determined
by the regulated output voltage, switching period and
transformer turns ration (use 1.0 for buck converter). It is
interesting to notice from the aforementioned two equations
T
T
then quickly raised by a clamp. When the R C pin reaches
T
T
the 0.95 V (typ) Valley Clamp Voltage, the clamp is
disconnected after a brief delay and C is charged through
T
R .
T
http://onsemi.com
10
CS51221
800
700
600
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
R = 5.0 K
T
500
400
300
200
R = 10 K
T
100
0
0.55
0.50
1000
R = 50 K
T
0.0001
0.001
C (mF)
0.01
10000
100000
1000000
R (W)
T
T
Figure 10. Typical Performance Characteristics,
Oscillator Frequency vs. CT
Figure 11. Typical Performance Characteristics,
Oscillator Duty Cycle vs. RT
that during steady state, V
doesn’t change for input
12.5 mA (R1 ) R2) + V
(C)
COMP
HYST
voltage variations. This intuitively explains why FF voltage
mode control has superior line regulation and line transient
response. Knowing the nominal value of V and T , one
where:
V
, V
= input voltage OV and UV
IN(LOW)
IN(HIGH)
IN
ON
threshold;
can also select the value of RC to place V
of its dynamic range.
at the center
COMP
V
HYST
= OV hysteresis seen at V
IN
It is self−evident from equation A and B that to use this
design, V has to be two times greater than
Select Feedback Voltage Divider
IN(HIGH)
As shown in Figure 12, the voltage divider output feeds to
the FB pin, which connects to the inverting input of the error
amplifier. The non−inverting input of the error amplifier is
connected to a 1.27 V (typ) reference voltage. The FB pin
has an input current which has to be considered for accurate
DC outputs. The following equation can be used to calculate
the R1 and R2 value
V
. Otherwise, two voltage dividers have to be used
IN(LOW)
to program OV and UV separately.
V
OUT
Ier
R1
R2
R1 ) R2
ǒ
ǓV
+ 1.27 * ʼn
OUT
FB
−
+
Ri
where ∇ is the correction factor due to the existence of the
FB pin input current Ier.
COMP
ʼn + (Ri ) R1ńńR2)Ier
+
−
R2
1.27
Ri = DC resistance between the FB pin and the voltage
divider output.
Ier = V input current, 1.3 mA typical.
FB
Figure 12. The Design of Feedback Voltage Divider
Has to Consider the Error Amplifier Input Current
Design Voltage Dividers for OV and UV Detection
In Figure 13, the voltage divider uses three resistors in
series to set OV and UV threshold seen from the input
voltage. The values of the resistors can be calculated from
the following three equations, where the third equation is
derived from OV hysteresis requirement.
R1
R2
R3
V
IN
R2 ) R3
ǒ
Ǔ+ 1.0 V
V
(A)
IN(LOW)
R2 ) R3 ) R1
V
UV
V
OV
R3
ǒ
Ǔ+ 2.0 V
V
(B)
IN(HIGH)
Figure 13. OV/UV Monitor Divider
R2 ) R3 ) R1
http://onsemi.com
11
CS51221
PACKAGE DIMENSIONS
SOIC−16
D SUFFIX
CASE 751B−05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
G
DIM MIN
MAX
10.00
4.00
1.75
0.49
1.25
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
0.386
0.150
0.054
0.014
0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
C
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
−T−
SEATING
PLANE
K
M
P
R
J
_
_
_
_
M
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
D
16 PL
M
S
S
0.25 (0.010)
T B
A
PACKAGE THERMAL DATA
Parameter
SOIC−16
28
Unit
R
Typical
Typical
°C/W
°C/W
q
q
JC
JA
R
115
http://onsemi.com
12
CS51221
PACKAGE DIMENSIONS
TSSOP−16
CASE 948F−01
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
16X KREF
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
S
S
V
0.10 (0.004)
T U
S
0.15 (0.006) T U
16
9
2X L/2
K
K1
B
L
−U−
J1
PIN 1
IDENT.
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
SECTION N−N
8
1
A
B
C
D
F
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
J
N
1.20
−−− 0.047
0.25 (0.010)
S
0.15 (0.006) T U
0.15 0.002 0.006
0.75 0.020 0.030
A
M
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
−V−
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
N
F
6.40 BSC
0.252 BSC
M
0
8
0
8
_
_
_
_
DETAIL E
−W−
C
0.10 (0.004)
DETAIL E
H
SEATING
PLANE
−T−
D
G
http://onsemi.com
13
CS51221
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
Literature Distribution Center for ON Semiconductor
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA
Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
For additional information, please contact your
local Sales Representative.
CS51221D
CS51221EDR16G CAD模型
引脚图
封装焊盘图
CS51221EDR16G 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| CS51221ED16G | ONSEMI | Enhanced Voltage Mode PWM Controller | 类似代替 |
|
| CS51221EDR16 | ONSEMI | Enhanced Voltage Mode PWM Controller | 类似代替 |
|
CS51221EDR16G 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| CS51221EDTB16G | ONSEMI | Enhanced Voltage Mode PWM Controller | 获取价格 |
|
| CS51221EDTB16R2G | ONSEMI | Enhanced Voltage Mode PWM Controller | 获取价格 |
|
| CS51221EN16 | CHERRY | Enhanced Voltage Mode PWM Controller | 获取价格 |
|
| CS51221_09 | ONSEMI | Enhanced Voltage Mode PWM Controller | 获取价格 |
|
| CS51227/D | ETC | Enhanced Voltage Mode PWM Controller | 获取价格 |
|
| CS51227ED8 | CHERRY | Switching Controller, Voltage-mode, 1000kHz Switching Freq-Max, PDSO8, SO-8 | 获取价格 |
|
| CS51227EDR8 | ONSEMI | 1A SWITCHING CONTROLLER, 1000kHz SWITCHING FREQ-MAX, PDSO8, SOIC-8 | 获取价格 |
|
| CS51227EDR8 | CHERRY | Switching Controller, Voltage-mode, 1000kHz Switching Freq-Max, PDSO8, SO-8 | 获取价格 |
|
| CS5124 | CHERRY | High Performance, Integrated Current Mode PWM Controllers | 获取价格 |
|
| CS5124 | ONSEMI | High Performance, Integrated Current Mode PWM Controllers | 获取价格 |
|
CS51221EDR16G 相关文章
Bourns 密封通孔金属陶瓷微调电位计产品选型手册(英文版)
- 2024-09-20
- 6
Bourns 精密环境传感器产品选型手册(英文版)
- 2024-09-20
- 9
Bourns POWrTher 负温度系数(NTC)热敏电阻手册 (英文版)
- 2024-09-20
- 8
Bourns GMOV 混合过压保护组件产品选型手册(英文版)
- 2024-09-20
- 6
