CS5174ED8 [ONSEMI]
1.5 A 280 kHz/560 kHz Boost Regulators; 1.5 A 280千赫/ 560 kHz的升压稳压器
| 型号： | CS5174ED8 |
| 厂家： | 
ONSEMI |
| 描述： | 1.5 A 280 kHz/560 kHz Boost Regulators |
| 文件： | 总22页 (文件大小：187K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CS5171, CS5172, CS5173,
CS5174
1.5 A 280 kHz/560 kHz
Boost Regulators
The CS5171/2/3/4 products are 280 kHz/560 kHz switching
regulators with a high efficiency, 1.5 A integrated switch. These parts
operate over a wide input voltage range, from 2.7 V to 30 V. The
flexibility of the design allows the chips to operate in most power
supply configurations, including boost, flyback, forward, inverting,
and SEPIC. The ICs utilize current mode architecture, which allows
excellent load and line regulation, as well as a practical means for
limiting current. Combining high frequency operation with a highly
integrated regulator circuit results in an extremely compact power
supply solution. The circuit design includes provisions for features
such as frequency synchronization, shutdown, and feedback controls
for either positive or negative voltage regulation. These parts are
pin−to−pincompatible with LT1372/1373.
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SOIC−8
D SUFFIX
CASE 751
PIN CONNECTIONS AND
MARKING DIAGRAM
CS5171/3
1
8
V
C
V
SW
FB
Test
SS
PGND
AGND
Part Number
CS5171
Frequency
280 kHz
280 kHz
560 kHz
560 kHz
Feedback Voltage Polarity
positive
negative
positive
negative
V
CC
CS5172
CS5173
CS5172/4
1
8
CS5174
V
C
V
SW
Test
NFB
SS
PGND
AGND
Features
• Pb−Free Packages are Available
V
CC
• Integrated Power Switch: 1.5 A Guaranteed
• Wide Input Range: 2.7 V to 30 V
• High Frequency Allows for Small Components
• Minimum External Components
• Easy External Synchronization
• Built in Overcurrent Protection
x
x
A
L
Y
W
= 1, 2, 3, or 4
= E, G
= Assembly Location
= Wafer Lot
= Year
= Work Week
• Frequency Foldback Reduces Component Stress During an
Overcurrent Condition
ORDERING INFORMATION
See detailed ordering and shipping information in the
package dimensions section on page 17 of this data sheet.
• Thermal Shutdown with Hysteresis
• Regulates Either Positive or Negative Output Voltages
• Shut Down Current: 50 mA Maximum
• Pin−to−Pin Compatible with LT1372/1373
• Wide Temperature Range
♦ Industrial Grade: −40°C to 125°C
♦ Commercial Grade: 0°C to 125°C
Semiconductor Components Industries, LLC, 2004
1
Publication Order Number:
June, 2004 − Rev. 20
CS5171/D
CS5171, CS5172, CS5173, CS5174
R2
3.72 k
D1
V
OUT
8
7
6
5
1
V
5 V
V
SW
C
MBRS120T3
2
3
4
PGND
AGND
FB
C1
0.01 mF
Test
SS
L1
+
C3
22 mF
SS
V
CC
22 mH
3.3 V
R3
R1
5 k
+
C2
22 mF
1.28 k
Figure 1. Applications Diagram
MAXIMUM RATINGS
Rating
Value
Unit
°C
Junction Temperature Range, T
−40 to +150
−65 to +150
J
Storage Temperature Range, T
°C
STORAGE
Package Thermal Resistance: Junction−to−Case, R
45
165
°C/W
°C/W
q
JC
Junction−to−Ambient, R
q
JA
Lead Temperature Soldering: Reflow (Note 1)
ESD, Human Body Model
230 Peak
1.2
°C
kV
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. 60 second maximum above 183°C.
MAXIMUM RATINGS
Pin Name
IC Power Input
Pin Symbol
V
V
I
I
SINK
MAX
MIN
SOURCE
V
CC
30 V
30 V
6.0 V
10 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
N/A
200 mA
1.0 mA
10 mA
1.0 mA
Shutdown/Sync
SS
1.0 mA
10 mA
1.0 mA
Loop Compensation
Voltage Feedback Input
V
C
FB
(CS5171/3 only)
Negative Feedback Input
(transient, 10 ms)
NFB
−10 V
10 V
1.0 mA
1.0 mA
(CS5172/4 only)
Test Pin
Test
6.0 V
0.3 V
0 V
−0.3 V
−0.3 V
0 V
1.0 mA
4 A
1.0 mA
10 mA
10 mA
3.0 A
Power Ground
Analog Ground
Switch Input
PGND
AGND
N/A
V
SW
40 V
−0.3 V
10 mA
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CS5171, CS5172, CS5173, CS5174
ELECTRICAL CHARACTERISTICS (2.7 V< V < 30 V; Industrial Grade: −40°C < T < 125°C;
CC
J
Commercial Grade: 0°C < T < 125°C; For all CS5171/2/3/4 specifications unless otherwise stated.)
J
Characteristic
Test Conditions
Min
Typ
Max
Unit
Positive and Negative Error Amplifiers
FB Reference Voltage (CS5171/3 only)
NFB Reference Voltage (CS5172/4 only)
FB Input Current (CS5171/3 only)
V
V
tied to FB; measure at FB
= 1.25 V
1.246
−2.55
−1.0
−16
−
1.276
−2.45
0.1
1.300
−2.35
1.0
V
V
C
C
FB = V
mA
mA
%/V
REF
NFB Input Current (CS5172/4 only)
NFB = NV
−10
−5.0
0.03
REF
FB Reference Voltage Line Regulation
(CS5171/3 only)
V
C
= FB
0.01
NFB Reference Voltage Line Regulation
(CS5172/4 only)
V
C
= 1.25 V
−
0.01
0.05
%/V
Positive Error Amp Transconductance
Negative Error Amp Transconductance
Positive Error Amp Gain
I
I
= ± 25 mA
= ± 5 mA
300
115
200
100
25
550
160
500
180
50
800
225
−
mMho
mMho
V/V
V/V
mA
VC
VC
(Note 2)
(Note 2)
Negative Error Amp Gain
320
90
V
C
V
C
V
C
Source Current
Sink Current
FB = 1.0 V or NFB = −1.9 V, V = 1.25 V
C
FB = 1.5 V or NFB = −3.1 V, V = 1.25 V
200
1.5
625
1.7
1500
1.9
mA
C
High Clamp Voltage
FB = 1.0 V or NFB = −1.9 V;
V
V
C
sources 25 mA
V
V
Low Clamp Voltage
Threshold
FB = 1.5 V or NFB = −3.1 V, V sinks 25 mA
0.25
0.75
0.50
1.05
0.65
1.30
V
V
C
C
Reduce V from 1.5 V until switching stops
C
C
Oscillator
Base Operating Frequency
Reduced Operating Frequency
Maximum Duty Cycle
CS5171/2, FB = 1 V or NFB = −1.9 V
CS5171/2, FB = 0 V or NFB = 0 V
CS5171/2
230
30
280
52
310
120
−
kHz
kHz
%
90
94
Base Operating Frequency
Reduced Operating Frequency
Maximum Duty Cycle
CS5173/4, FB = 1 V or NFB = −1.9 V
CS5173/4, FB = 0 V or NFB = 0 V
CS5173/4
460
60
560
104
90
620
160
−
kHz
kHz
%
82
NFB Frequency Shift Threshold
FB Frequency Shift Threshold
Frequency drops to reduced operating frequency
Frequency drops to reduced operating frequency
−0.80
0.36
−0.65
0.40
−0.50
0.44
V
V
Sync/ Shutdown
Sync Range
CS5171/2
320
640
2.5
−
−
−
500
1000
−
kHz
kHz
V
Sync Range
CS5173/4
Sync Pulse Transition Threshold
SS Bias Current
Rise time = 20 ns
SS = 0 V
SS = 3.0 V
−15
−
−3.0
3.0
−
mA
mA
8.0
Shutdown Threshold
Shutdown Delay
−
0.50
0.85
1.20
V
2.7 V ≤ V ≤ 12 V
12
12
80
36
350
200
ms
ms
CC
12 V < V ≤ 30 V
CC
2. Guaranteed by design, not 100% tested in production.
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CS5171, CS5172, CS5173, CS5174
ELECTRICAL CHARACTERISTICS (continued) (2.7 V< V < 30 V; Industrial Grade: −40°C < T < 125°C;
CC
J
Commercial Grade: 0°C < T < 125°C; For all CS5171/2/3/4 specifications unless otherwise stated.)
J
Characteristic
Test Conditions
Min
Typ
Max
Unit
Power Switch
Switch Saturation Voltage
I
I
I
I
= 1.5 A, (Note 3)
−
−
−
−
0.8
1.4
−
V
V
V
V
SWITCH
SWITCH
SWITCH
SWITCH
= 1.0 A, 0°C ≤ T ≤ 85°C
0.55
0.75
0.09
J
= 1.0 A, −40°C ≤ T ≤ 0°C
= 10 mA
J
−
0.45
Switch Current Limit
Minimum Pulse Width
50% duty cycle, Note 3
80% duty cycle, Note 3
1.6
1.5
1.9
1.7
2.4
2.2
A
A
FB = 0 V or NFB = 0 V, I
= 4.0 A, (Note 3)
200
250
300
ns
SW
DI / DIV
2.7 V ≤ V ≤ 12 V, 10 mA ≤ I ≤ 1.0 A
SW
−
−
−
−
10
−
30
100
30
mA/A
mA/A
mA/A
mA/A
CC
SW
CC
12 V < V ≤ 30 V, 10 mA ≤ I
≤ 1.0 A
CC
SW
2.7 V ≤ V ≤ 12 V, 10 mA ≤ I
≤ 1.5 A, (Note 3)
≤ 1.5 A, (Note 3)
CC
SW
SW
17
−
12 V < V ≤ 30 V, 10 mA ≤ I
CC
100
Switch Leakage
V
SW
= 40 V, V = 0V
−
2.0
100
mA
CC
General
Operating Current
I
= 0
−
5.5
8.0
mA
SW
Shutdown Mode Current
V
C
V
C
< 0.8 V, SS = 0 V, 2.7 V ≤ V ≤ 12 V
−
−
12
−
60
mA
CC
< 0.8 V, SS = 0 V, 12 V ≤ V ≤ 30 V
100
CC
Minimum Operation Input Voltage
Thermal Shutdown
V
switching, maximum I
10 mA
SW =
−
150
−
2.45
180
25
2.70
210
−
V
SW
(Note 3)
(Note 3)
°C
°C
Thermal Hysteresis
3. Guaranteed by design, not 100% tested in production.
PACKAGE PIN DESCRIPTION
Package
Pin #
Pin
Symbol
Function
1
V
C
Loop compensation pin. The V pin is the output of the error amplifier and is used for loop compensation,
current limit and soft start. Loop compensation can be implemented by a simple RC network as shown in the
application diagram on page 2 as R1 and C1.
C
2
FB
Positive regulator feedback pin. This pin senses a positive output voltage and is referenced to 1.276 V. When
the voltage at this pin falls below 0.4 V, chip switching frequency reduces to 20% of the nominal frequency.
(CS5171/3
only)
2
Test
These pins are connected to internal test logic and should either be left floating or tied to ground. Connection
to a voltage between 2 V and 6 V shuts down the internal oscillator and leaves the power switch running.
(CS5172/4)
3
(CS5171/3)
3
NFB
SS
Negative feedback pin. This pin senses a negative output voltage and is referenced to −2.5 V. When the volt-
age at this pin goes above −0.65 V, chip switching frequency reduces to 20% of the nominal frequency.
(CS5172/4)
4
Synchronization and shutdown pin. This pin may be used to synchronize the part to nearly twice the base
frequency. A TTL low will shut the part down and put it into low current mode. If synchronization is not used,
this pin should be either tied high or left floating for normal operation.
5
6
V
Input power supply pin. This pin supplies power to the part and should have a bypass capacitor connected to
AGND.
CC
AGND
PGND
Analog ground. This pin provides a clean ground for the controller circuitry and should not be in the path of
large currents. The output voltage sensing resistors should be connected to this ground pin. This pin is con-
nected to the IC substrate.
7
8
Power ground. This pin is the ground connection for the emitter of the power switching transistor. Connection
to a good ground plane is essential.
V
SW
High current switch pin. This pin connects internally to the collector of the power switch. The open voltage
across the power switch can be as high as 40 V. To minimize radiation, use a trace as short as practical.
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CS5171, CS5172, CS5173, CS5174
V
CC
Thermal
Shutdown
Shutdown
2.0 V
Regulator
V
SW
PWM
Latch
R
Oscillator
S
Delay
Timer
Switch
Q
Driver
Sync
SS
Frequency
Shift 5:1
×5
200 k
2.0 V
Slope
Compensation
Negative
Error Amp
63 mW
250 k
NFB
+
−
PGND
Ramp
Summer
CS5172/4
only
PWM
Comparator
−0.65 V Detector
0.4 V Detector
+
−
FB
−
+
CS5171/3
only
Positive
Error Amp
1.276 V
AGND
V
C
Figure 2. Block Diagram
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CS5171, CS5172, CS5173, CS5174
TYPICAL PERFORMANCE CHARACTERISTICS
7.2
7.0
70
60
V
V
= 30 V
= 12 V
CC
V
= 30 V
CC
6.8
6.6
6.4
I
= 1.5 A
50
40
30
SW
V
CC
= 12 V
6.2
CC
20
10
6.0
5.8
V
CC
= 2.7 V
100
V
CC
= 2.7 V
5.6
0
0
50
100
0
50
Temperature (°C)
Temperature (°C)
Figure 3. ICC (No Switching) vs. Temperature
Figure 4. DICC/ DIVSW vs. Temperature
1.9
1200
1000
800
−40 °C
85 °C
1.8
1.7
600
25 °C
400
1.6
1.5
200
0
500
1000
0
50
100
I
(mA)
SW
Temperature (°C)
Figure 5. VCE(SAT) vs. ISW
Figure 6. Minimum Input Voltage vs. Temperature
570
565
560
555
285
280
275
270
265
550
545
540
535
530
525
520
260
255
0
50
100
0
50
100
Temperature (°C)
Temperature (°C)
Figure 8. Switching Frequency vs. Temperature
(CS5173/4 only)
Figure 7. Switching Frequency vs. Temperature
(CS5171/2 only)
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CS5171, CS5172, CS5173, CS5174
TYPICAL PERFORMANCE CHARACTERISTICS
V
CC
= (12 V)
V
CC
= (12 V)
100
75
100
75
−40°C
85°C
85°C
−40°C
50
50
25°C
25
0
25
0
25°C
350
380
400
(mV)
420
450
−550
−660
(mV)
NFB
−725
V
V
FB
Figure 10. Switching Frequency vs. VNFB
(CS5172/4 only)
Figure 9. Switching Frequency vs. VFB
(CS5171/3 only)
1.280
1.278
1.276
V
CC
= 12 V
−2.42
−2.43
−2.44
V
CC
= 30 V
1.274
1.272
1.270
−2.45
−2.46
−2.47
−2.48
V
= 2.7 V
CC
V
= 12 V
CC
V
CC
= 30 V
V
CC
= 2.7 V
1.268
0
50
Temperature (°C)
100
0
50
Temperature (°C)
100
Figure 12. Reference Voltage vs. Temperature
(CS5172/4 only)
Figure 11. Reference Voltage vs. Temperature
(CS5171/3 only)
0.20
0.18
0.16
0.14
0.12
−7
−8
−9
V
= 12 V
= 2.7 V
CC
−10
−11
−12
0.10
0.08
V
CC
−13
−14
0
50
100
0
50
100
Temperature (°C)
Temperature (°C)
Figure 13. IFB vs. Temperature (CS5171/3 only)
Figure 14. INFB vs. Temperature (CS5172/ 4 only)
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CS5171, CS5172, CS5173, CS5174
TYPICAL PERFORMANCE CHARACTERISTICS
99
98
2.60
2.50
2.40
2.30
2.20
V
= 30 V
CC
V
CC
= 12 V
97
96
V
CC
= 2.7 V
95
94
93
V
= 2.7 V
CC
V
= 12 V
CC
V
= 30 V
CC
0
50
Temperature (°C)
100
0
50
Temperature (°C)
100
Figure 16. Maximum Duty Cycle vs. Temperature
Figure 15. Current Limit vs. Temperature
1.1
1.7
1.0
0.9
0.8
0.7
V
C
High Clamp Voltage
1.5
1.3
1.1
0.9
0.7
0.6
0.5
0.4
V
C
Threshold
0
50
100
0
100
50
Temperature (°C)
Temperature (°C)
Figure 18. Shutdown Threshold vs. Temperature
Figure 17. VC Threshold and High Clamp
Voltage vs. Temperature
40
160
140
25°C
V
CC
= 2.7 V
30
20
85°C
120
100
80
−40°C
V
CC
= 12 V
10
V
CC
= 30 V
100
0
60
40
−10
1
3
5
(V)
7
9
0
50
Temperature (°C)
V
SS
Figure 20. ISS vs. VSS
Figure 19. Shutdown Delay vs. Temperature
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CS5171, CS5172, CS5173, CS5174
TYPICAL PERFORMANCE CHARACTERISTICS
600
−40°C
40
30
550
25°C
20
10
0
85°C
500
450
0
50
100
10
(V)
Temperature (°C)
V
IN
Figure 22. Error Amplifier Transconductance
vs. Temperature (CS5171/3 only)
Figure 21. ICC vs. VIN During Shutdown
100
60
190
180
170
160
150
20
140
130
120
110
100
−20
−60
−255 −175 −125
−75
−25
0
25
0
50
100
V
REF
− V (mV)
Temperature (°C)
FB
Figure 24. Error Amplifier IOUT vs. VFB
(CS5171/3 only)
Figure 23. Negative Error Amplifier
Transconductance vs. Temperature (CS5172/4 only)
2.6
2.5
2.4
100
80
60
40
20
2.3
2.2
0
−20
2.1
2.0
−40
−60
−200
−150
−100
−50
(mV)
0
50
0
50
100
Temperature (°C)
V
REF
− V
NFB
Figure 26. Switch Leakage vs. Temperature
Figure 25. Error Amplifier IOUT vs. VNFB
(CS5172/4 only)
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CS5171, CS5172, CS5173, CS5174
APPLICATIONS INFORMATION
THEORY OF OPERATION
Current Mode Control
The oscillator is trimmed to guarantee an 18% frequency
accuracy. The output of the oscillator turns on the power
switch at a frequency of 280 kHz (CS5171/2) or 560 kHz
(CS5173/4), as shown in Figure 27. The power switch is
turned off by the output of the PWM Comparator.
A TTL−compatible sync input at the SS pin is capable of
syncing up to 1.8 times the base oscillator frequency. As
shown in Figure 28, in order to sync to a higher frequency,
a positive transition turns on the power switch before the
output of the oscillator goes high, thereby resetting the
oscillator. The sync operation allows multiple power
supplies to operate at the same frequency.
V
CC
Oscillator
S
L
Q
−
V
C
R
+
Power Switch
D1
PWM
V
SW
Comparator
In Out
Driver
C
O
R
LOAD
X5
SUMMER
W
63 m
Slope Compensation
A sustained logic low at the SS pin will shut down the IC
and reduce the supply current.
Figure 27. Current Mode Control Scheme
An additional feature includes frequency shift to 20% of
the nominal frequency when either the NFB or FB pins
trigger the threshold. During power up, overload, or short
circuit conditions, the minimum switch on−time is limited
by the PWM comparator minimum pulse width. Extra
switch off−time reduces the minimum duty cycle to protect
external components and the IC itself.
The CS517x family incorporates a current mode control
scheme, in which the PWM ramp signal is derived from the
power switch current. This ramp signal is compared to the
output of the error amplifier to control the on−time of the
power switch. The oscillator is used as a fixed−frequency
clock to ensure a constant operational frequency. The
resulting control scheme features several advantages over
conventional voltage mode control. First, derived directly
from the inductor, the ramp signal responds immediately to
line voltage changes. This eliminates the delay caused by the
output filter and error amplifier, which is commonly found
in voltage mode controllers. The second benefit comes from
inherent pulse−by−pulse current limiting by merely
clamping the peak switching current. Finally, since current
mode commands an output current rather than voltage, the
filter offers only a single pole to the feedback loop. This
allows both a simpler compensation and a higher
gain−bandwidth over a comparable voltage mode circuit.
Without discrediting its apparent merits, current mode
control comes with its own peculiar problems, mainly,
subharmonic oscillation at duty cycles over 50%. The
CS517x family solves this problem by adopting a slope
compensation scheme in which a fixed ramp generated by
the oscillator is added to the current ramp. A proper slope
rate is provided to improve circuit stability without
sacrificing the advantages of current mode control.
As previously mentioned, this block also produces a ramp
for the slope compensation to improve regulator stability.
Error Amplifier
200 k
2.0 V
250 k
NFB
+
−
CS5172/4
negative error−amp
V
C
C1
120 pF
1MW
0.01 mF
Voltage
Clamp
+
1.276 V
R1
5 kW
−
FB
CS5171/3
positive error−amp
Figure 29. Error Amplifier Equivalent Circuit
For CS5172/4, the NFB pin is internally referenced to
−2.5 V with approximately a 250 kW input impedance. For
CS5171/3, the FB pin is directly connected to the inverting
input of the positive error amplifier, whose non−inverting
input is fed by the 1.276 V reference. Both amplifiers are
transconductance amplifiers with a high output impedance
Oscillator and Shutdown
of approximately 1 MW, as shown in Figure 29. The V pin
is connected to the output of the error amplifiers and is
internally clamped between 0.5 V and 1.7 V. A typical
C
Sync
Current
Ramp
connection at the V pin includes a capacitor in series with
C
V
SW
a resistor to ground, forming a pole/zero for loop
compensation.
Figure 28. Timing Diagram of Sync and Shutdown
An external shunt can be connected between the V pin
C
and ground to reduce its clamp voltage. Consequently, the
current limit of the internal power transistor current is
reduced from its nominal value.
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CS5171, CS5172, CS5173, CS5174
Switch Driver and Power Switch
approximately 1.5 V, the internal power switch briefly turns
on. This is a part of the CS517x’s normal operation. The
turn−on of the power switch accounts for the initial current
swing.
The switch driver receives a control signal from the logic
section to drive the output power switch. The switch is
grounded through emitter resistors (63 mW total) to the
PGND pin. PGND is not connected to the IC substrate so that
switching noise can be isolated from the analog ground. The
peak switching current is clamped by an internal circuit. The
clamp current is guaranteed to be greater than 1.5 A and
varies with duty cycle due to slope compensation. The
power switch can withstand a maximum voltage of 40 V on
When the V pin voltage rises above the threshold, the
C
internal power switch starts to switch and a voltage pulse can
be seen at the V pin. Detecting a low output voltage at the
SW
FB pin, the built−in frequency shift feature reduces the
switching frequency to a fraction of its nominal value,
reducing the minimum duty cycle, which is otherwise
limited by the minimum on−time of the switch. The peak
current during this phase is clamped by the internal current
limit.
When the FB pin voltage rises above 0.4 V, the frequency
increases to its nominal value, and the peak current begins
to decrease as the output approaches the regulation voltage.
The overshoot of the output voltage is prevented by the
active pull−on, by which the sink current of the error
amplifier is increased once an overvoltage condition is
detected. The overvoltage condition is defined as when the
FB pin voltage is 50 mV greater than the reference voltage.
the collector (V pin). The saturation voltage of the switch
SW
is typically less than 1 V to minimize power dissipation.
Short Circuit Condition
When a short circuit condition happens in a boost circuit,
the inductor current will increase during the whole
switching cycle, causing excessive current to be drawn from
the input power supply. Since control ICs don’t have the
means to limit load current, an external current limit circuit
(such as a fuse or relay) has to be implemented to protect the
load, power supply and ICs.
In other topologies, the frequency shift built into the IC
prevents damage to the chip and external components. This
feature reduces the minimum duty cycle and allows the
transformer secondary to absorb excess energy before the
switch turns back on.
COMPONENT SELECTION
Frequency Compensation
The goal of frequency compensation is to achieve
desirable transient response and DC regulation while
ensuring the stability of the system. A typical compensation
network, as shown in Figure 31, provides a frequency
response of two poles and one zero. This frequency response
is further illustrated in the Bode plot shown in Figure 32.
I
L
V
OUT
V
C
R1
V
CC
CS5171
C2
V
C
C1
GND
Figure 31. A Typical Compensation Network
Figure 30. Startup Waveforms of Circuit Shown in
the Application Diagram. Load = 400 mA.
The high DC gain in Figure 32 is desirable for achieving
DC accuracy over line and load variations. The DC gain of
a transconductance error amplifier can be calculated as
follows:
The CS517x can be activated by either connecting the
V
pin to a voltage source or by enabling the SS pin.
CC
Startup waveforms shown in Figure 30 are measured in the
boost converter demonstrated in the Application Diagram
on the page 2 of this document. Recorded after the input
voltage is turned on, this waveform shows the various
phases during the power up transition.
Gain
+ G R
M O
DC
where:
= error amplifier transconductance;
G
M
R = error amplifier output resistance ≈ 1 MW.
O
When the V voltage is below the minimum supply
The low frequency pole, f is determined by the error
CC
P1,
voltage, the V
pin is in high impedance. Therefore,
amplifier output resistance and C1 as:
SW
current conducts directly from the input power source to the
output through the inductor and diode. Once V reaches
1
f
+
P1
CC
2pC1R
O
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11
CS5171, CS5172, CS5173, CS5174
The first zero generated by C1 and R1 is:
−V
OUT
2 V
1
f
+
Z1
2pC1R1
R
P
200 kW
R1
The phase lead provided by this zero ensures that the loop
R
has at least a 45° phase margin at the crossover frequency.
Therefore, this zero should be placed close to the pole
generated in the power stage which can be identified at
frequency:
IN
NFB
+
250 kW
R2
−
Negative Error−Amp
1
f
+
P
2pC R
O LOAD
Figure 33. Negative Error Amplifier and NFB Pin
where:
C = equivalent output capacitance of the error amplifier
O
It is shown that if R1 is less than 10 k, the deviation from
the design target will be less than 0.1 V. If the tolerances of
the negative voltage reference and NFB pin input current are
≈120pF;
R
LOAD
= load resistance.
The high frequency pole, f , can be placed at the output
P2
considered, the possible offset of the output V
in the range of:
varies
OFFSET
filter’s ESR zero or at half the switching frequency. Placing
the pole at this frequency will cut down on switching noise.
The frequency of this pole is determined by the value of C2
and R1:
*0.0.5 (R1 ) R2)
ǒ
Ǔ* (15 mA R1) v V
OFFSET
R2
0.0.5 (R1 ) R2)
v ǒ
Ǔ* (5 mA R1)
1
f
+
R2
P2
2pC2R1
One simple method to ensure adequate phase margin is to
design the frequency response with a −20 dB per decade
slope, until unity−gain crossover. The crossover frequency
VSW Voltage Limit
In the boost topology, V pin maximum voltage is set by
the maximum output voltage plus the output diode forward
voltage. The diode forward voltage is typically 0.5 V for
Schottky diodes and 0.8 V for ultrafast recovery diodes
SW
should be selected at the midpoint between f and f where
Z1
P2
the phase margin is maximized.
V
+ V
)V
OUT(MAX)
SW(MAX)
F
f
P1
where:
V = output diode forward voltage.
f
Z1
F
In the flyback topology, peak V voltage is governed by:
SW
f
P2
V
+ V
)(V
CC(MAX)
)V ) N
OUT
SW(MAX)
F
where:
N = transformer turns ratio, primary over secondary.
When the power switch turns off, there exists a voltage
spike superimposed on top of the steady−state voltage.
Usually this voltage spike is caused by transformer leakage
Frequency (LOG)
Figure 32. Bode Plot of the Compensation Network
Shown in Figure 31
inductance charging stray capacitance between the V and
SW
PGND pins. To prevent the voltage at the V
pin from
SW
Negative Voltage Feedback
exceeding the maximum rating, a transient voltage
suppressor in series with a diode is paralleled with the
primary windings. Another method of clamping switch
voltage is to connect a transient voltage suppressor between
Since the negative error amplifier has finite input
impedance as shown in Figure 33, its induced error has to be
considered. If a voltage divider is used to scale down the
negative output voltage for the NFB pin, the equation for
calculating output voltage is:
the V pin and ground.
SW
*2.5 (R1 ) R2)
+ ǒ
Ǔ*10 mA R1
*V
OUT
R2
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12
CS5171, CS5172, CS5173, CS5174
I
L
Magnetic Component Selection
I
IN
When choosing a magnetic component, one must consider
factors such as peak current, core and ferrite material, output
voltage ripple, EMI, temperature range, physical size and
cost. In boost circuits, the average inductor current is the
+
−
V
CC
C
IN
product of output current and voltage gain (V
/V ),
OUT CC
assuming 100% energy transfer efficiency. In continuous
conduction mode, inductor ripple current is
R
ESR
V
(V
CC OUT
* V
)
CC
I
+
RIPPLE
(f)(L)(V
OUT)
where:
f = 280 kHz for CS5171/2 and 560 kHz for CS5173/4.
Figure 35. Boost Circuit Effective Input Filter
The peak inductor current is equal to average current plus
half of the ripple current, which should not cause inductor
saturation. The above equation can also be referenced when
selecting the value of the inductor based on the tolerance of
the ripple current in the circuits. Small ripple current
provides the benefits of small input capacitors and greater
output current capability. A core geometry like a rod or
barrel is prone to generating high magnetic field radiation,
but is relatively cheap and small. Other core geometries,
such as toroids, provide a closed magnetic loop to prevent
EMI.
The situation is different in a flyback circuit. The input
current is discontinuous and a significant pulsed current is
seen by the input capacitors. Therefore, there are two
requirements for capacitors in a flyback regulator: energy
storage and filtering. To maintain a stable voltage supply to
the chip, a storage capacitor larger than 20 mF with low ESR
is required. To reduce the noise generated by the inductor,
insert a 1.0 mF ceramic capacitor between V and ground
CC
as close as possible to the chip.
Output Capacitor Selection
Input Capacitor Selection
In boost circuits, the inductor becomes part of the input
filter, as shown in Figure 35. In continuous mode, the input
current waveform is triangular and does not contain a large
pulsed current, as shown in Figure 34. This reduces the
requirements imposed on the input capacitor selection.
During continuous conduction mode, the peak to peak
inductor ripple current is given in the previous section. As
we can see from Figure 34, the product of the inductor
current ripple and the input capacitor’s effective series
V
I
ripple
OUT
resistance (ESR) determine the V
ripple. In most
CC
L
applications, input capacitors in the range of 10 mF to 100 mF
with an ESR less than 0.3 W work well up to a full 1.5 A
switch current.
Figure 36. Typical Output Voltage Ripple
By examining the waveforms shown in Figure 36, we can
see that the output voltage ripple comes from two major
V
ripple
CC
sources,
charging/discharging of the output capacitor. In boost
circuits, when the power switch turns off, I flows into the
namely
capacitor
ESR
and
the
L
I
IN
output capacitor causing an instant DV = I × ESR. At the
IN
same time, current I − I
charges the capacitor and
L
OUT
increases the output voltage gradually. When the power
switch is turned on, I is shunted to ground and I
I
L
L
OUT
discharges the output capacitor. When the I ripple is small
L
enough, I can be treated as a constant and is equal to input
L
current I .
IN
Figure 34. Boost Input Voltage and Current
Ripple Waveforms
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13
CS5171, CS5172, CS5173, CS5174
Summing up, the output voltage peak−peak ripple can be
calculated by:
Unfortunately, such a simple circuit is not generally
acceptable if V is loosely regulated.
IN
(I * I
(1 * D)
(f)
IN
OUT)
OUT)
V
IN
V
+
OUT(RIPPLE)
(C
V
CC
I
D
OUT
(C
)
) I ESR
IN
)(f)
OUT
R2
R3
The equation can be expressed more conveniently in
V
C
terms of V , V
follows:
and I
for design purposes as
CC
OUT
OUT
D1
I
(V
OUT OUT
* V
)(f)
)
CC
1
V
+
OUT(RIPPLE)
(C
(C
)(f)
OUT
OUT
(I
)(V
)(ESR)
OUT OUT
)
V
R1
CC
C1
The capacitor RMS ripple current is:
Ǹ
2
2
) (D)
OUT
I
+
(I * I
) (1 * D))(I
C2
RIPPLE
IN
OUT
V
* V
OUT
V
CC
OUT Ǹ
+ I
CC
Figure 37. Current Limiting using a Diode Clamp
Although the above equations apply only for boost
circuits, similar equations can be derived for flyback
circuits.
Another solution to the current limiting problem is to
externally measure the current through the switch using a
sense resistor. Such a circuit is illustrated in Figure 38.
Reducing the Current Limit
V
CC
In some applications, the designer may prefer a lower
limit on the switch current than 1.5 A. An external shunt can
be connected between the V pin and ground to reduce its
C
V
PGND
AGND
C
clamp voltage. Consequently, the current limit of the
internal power transistor current is reduced from its nominal
value.
+
−
V
IN
The voltage on the V pin can be evaluated with the
equation
C
R1
C2
C1
V
+ I R A
SW E V
R2
C3
C
Q1
where:
R = .063W, the value of the internal emitter resistor;
Output
Ground
E
R
SENSE
A = 5 V/V, the gain of the current sense amplifier.
V
Figure 38. Current Limiting using a Current Sense
Resistor
Since R and A cannot be changed by the end user, the
E
V
only available method for limiting switch current below
1.5 A is to clamp the V pin at a lower voltage. If the
The switch current is limited to
C
maximum switch or inductor current is substituted into the
equation above, the desired clamp voltage will result.
A simple diode clamp, as shown in Figure 37, clamps the
V
R
BE(Q1)
SENSE
I
+
SWITCH(PEAK)
where:
V voltage to a diode drop above the voltage on resistor R3.
C
V
BE(Q1)
= the base−emitter voltage drop of Q1, typically
0.65 V.
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CS5171, CS5172, CS5173, CS5174
The improved circuit does not require a regulated voltage
The dashed box contains the normal compensation
circuitry to limit the bandwidth of the error amplifier.
to operate properly. Unfortunately, a price must be paid for
this convenience in the overall efficiency of the circuit. The
designer should note that the input and output grounds are
no longer common. Also, the addition of the current sense
Resistors R2 and R3 form a voltage divider off of the V
SW
pin. In normal operation, V
looks similar to a square
SW
wave, and is dependent on the converter topology. Formulas
for calculating V in the boost and flyback topologies are
resistor, R , results in a considerable power loss which
SENSE
SW
increases with the duty cycle. Resistor R2 and capacitor C3
form a low−pass filter to remove noise.
given in the section “V Voltage Limit.” The voltage on
SW
V
SW
charges capacitor C3 when the switch is off, causing
the voltage at the V pin to shift upwards. When the switch
turns on, C3 discharges through R3, producing a negative
C
Subharmonic Oscillation
Subharmonic oscillation (SHM) is a problem found in
current−mode control systems, where instability results
when duty cycle exceeds 50%. SHM only occurs in
switching regulators with a continuous inductor current.
This instability is not harmful to the converter and usually
does not affect the output voltage regulation. SHM will
increase the radiated EM noise from the converter and can
cause, under certain circumstances, the inductor to emit
high−frequency audible noise.
SHM is an easily remedied problem. The rising slope of
the inductor current is supplemented with internal “slope
compensation” to prevent any duty cycle instability from
carrying through to the next switching cycle. In the CS517x
family, slope compensation is added during the entire switch
on−time, typically in the amount of 180 mA/ms.
slope at the V pin. This negative slope provides the slope
compensation.
The amount of slope compensation added by this circuit
C
is
*(1*D)
R
f
3
SW
(1 * D)R A
E V
DI
DT
R C f
3 SW
3
SW ǒ
Ǔ
ǒ1 * e Ǔǒ
Ǔ
+ V
R )R
2 3
where:
DI/DT = the amount of slope compensation added (A/s);
= the voltage at the switch node when the transistor
V
SW
is turned off (V);
= the switching frequency, typically 280 kHz
f
SW
(CS5171/3) or 560 kHz (CS5172/4) (Hz);
D = the duty cycle;
R = 0.063 W, the value of the internal emitter resistor;
E
In some cases, SHM can rear its ugly head despite the
presence of the onboard slope compensation. The simple
cure to this problem is more slope compensation to avoid the
unwanted oscillation. In that case, an external circuit, shown
in Figure 39, can be added to increase the amount of slope
compensation used. This circuit requires only a few
components and is “tacked on” to the compensation
network.
A = 5 V/V, the gain of the current sense amplifier.
V
In selecting appropriate values for the slope compensation
network, the designer is advised to choose a convenient
capacitor, then select values for R2 and R3 such that the
amount of slope compensation added is 100 mA/ms. Then
R2 may be increased or decreased as necessary. Of course,
the series combination of R2 and R3 should be large enough
to avoid drawing excessive current from V . Additionally,
SW
to ensure that the control loop stability is improved, the time
constant formed by the additional components should be
chosen such that
V
SW
V
SW
1 * D
V
C
R C t
3 3
f
SW
Finally, it is worth mentioning that the added slope
compensation is a tradeoff between duty cycle stability and
transient response. The more slope compensation a designer
adds, the slower the transient response will be, due to the
external circuitry interfering with the proper operation of the
error amplifier.
R1
R2
C1
C2
Soft−Start
Through the addition of an external circuit, a Soft−Start
function can be added to the CS5171/2/3/4 family of
components. Soft−Start circuitry prevents the V pin from
slamming high during startup, thereby inhibiting the
inductor current from rising at a high slope.
C3
C
R3
Figure 39. Technique for Increasing Slope
Compensation
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15
CS5171, CS5172, CS5173, CS5174
This circuit, shown in Figure 40, requires a minimum
when the switch is turned off. The specifications section of
number of components and allows the Soft−Start circuitry to
activate any time the SS pin is used to restart the converter.
this datasheet reveals that the typical operating current, I ,
Q
due to this circuitry is 5.5 mA. Additional guidance can be
found in the graph of operating current vs. temperature. This
graph shows that IQ is strongly dependent on input voltage,
V
IN
V , and temperature. Then
IN
V
CC
C
P
+ V
I
IN Q
BIAS
SS
Since the onboard switch is an NPN transistor, the base
drive current must be factored in as well. This current is
SS
V
drawn from the V pin, in addition to the control circuitry
IN
current. The base drive current is listed in the specifications
as DI /DI , or switch transconductance. As before, the
CC
SW
designer will find additional guidance in the graphs. With
that information, the designer can calculate
D2
D1
R1
I
CC
C1
P
+ V
I
IN SW
D
DRIVER
DI
SW
C2
C3
where:
= the current through the switch;
I
SW
D = the duty cycle or percentage of switch on−time.
and D are dependent on the type of converter. In a
I
SW
boost converter,
Figure 40. Soft Start
1
I
^ I D
LOAD
SW(AVG)
Efficiency
Resistor R1 and capacitors C1 and C2 form the
compensation network. At turn on, the voltage at the V pin
starts to come up, charging capacitor C3 through Schottky
C
V
* V
IN
OUT
OUT
V
D ^
diode D2, clamping the voltage at the V pin such that
C
In a flyback converter,
switching begins when V reaches the V threshold,
C
C
V
I
OUT LOAD
1
typically 1.05 V (refer to graphs for detail over temperature).
I
^
SW(AVG)
V
Efficiency
IN
V
+ V
)V
F(D2) C3
C
V
OUT
Therefore, C3 slows the startup of the circuit by limiting
D ^
N
V
)
S V
IN
N
P
OUT
the voltage on the V pin. The Soft−Start time increases with
C
the size of C3.
The switch saturation voltage, V
, is the last major
(CE)SAT
Diode D1 discharges C3 when SS is low. If the shutdown
function is not used with this part, the cathode of D1 should
source of on−chip power loss.
collector−emitter voltage of the internal NPN transistor
when it is driven into saturation by its base drive current. The
V
is the
(CE)SAT
be connected to V .
IN
value for V
can be obtained from the specifications
(CE)SAT
Calculating Junction Temperature
or from the graphs, as “Switch Saturation Voltage.” Thus,
To ensure safe operation of the CS5171/2/3/4, the
designer must calculate the on−chip power dissipation and
determine its expected junction temperature. Internal
thermal protection circuitry will turn the part off once the
junction temperature exceeds 180°C ± 30°. However,
repeated operation at such high temperatures will ensure a
reduced operating life.
Calculation of the junction temperature is an imprecise
but simple task. First, the power losses must be quantified.
There are three major sources of power loss on the CS517x:
P
^ V
I
D
SAT
(CE)SAT SW
Finally, the total on−chip power losses are
P
+ P
)P
BIAS
)P
DRIVER SAT
D
Power dissipation in a semiconductor device results in the
generation of heat in the junctions at the surface of the chip.
This heat is transferred to the surface of the IC package, but
a thermal gradient exists due to the resistive properties of the
package molding compound. The magnitude of the thermal
gradient is expressed in manufacturers’ data sheets as q
or junction−to−ambient thermal resistance. The on−chip
junction temperature can be calculated if q , the air
temperature near the surface of the IC, and the on−chip
power dissipation are known.
,
JA
• biasing of internal control circuitry, P
BIAS
• switch driver, P
DRIVER
JA
• switch saturation, P
SAT
The internal control circuitry, including the oscillator and
linear regulator, requires a small amount of power even
http://onsemi.com
16
CS5171, CS5172, CS5173, CS5174
transitions that can cause problems. Therefore the following
guidelines should be followed in the layout.
T + T )(P q
)
J
A
D JA
where:
T = IC or FET junction temperature (°C);
1.
In boost circuits, high AC current circulates within the
loop composed of the diode, output capacitor, and
on−chip power transistor. The length of associated
traces and leads should be kept as short as possible. In
the flyback circuit, high AC current loops exist on both
sides of the transformer. On the primary side, the loop
consists of the input capacitor, transformer, and
on−chip power transistor, while the transformer,
rectifier diodes, and output capacitors form another
loop on the secondary side. Just as in the boost circuit,
all traces and leads containing large AC currents
should be kept short.
Separate the low current signal grounds from the
power grounds. Use single point grounding or ground
plane construction for the best results.
Locate the voltage feedback resistors as near the IC as
possible to keep the sensitive feedback wiring short.
Connect feedback resistors to the low current analog
ground.
J
T = ambient temperature (°C);
A
P = power dissipated by part in question (W);
D
q
= junction−to−ambient thermal resistance (°C/W).
JA
For the CS517x, q =165°C/W.
JA
Once the designer has calculated T , the question of
J
whether the CS517x can be used in an application is settled.
If T exceeds 150°C, the absolute maximum allowable
J
junction temperature, the CS517x is not suitable for that
application.
If T approaches 150°C, the designer should consider
J
possible means of reducing the junction temperature.
Perhaps another converter topology could be selected to
reduce the switch current. Increasing the airflow across the
2.
3.
surface of the chip might be considered to reduce T .
A
Circuit Layout Guidelines
In any switching power supply, circuit layout is very
important for proper operation. Rapidly switching currents
combined with trace inductance generates voltage
ORDERING INFORMATION
†
Device
CS5171ED8
Operating Temperature Range
Package
Shipping
95 Units/Rail
CS5171EDR8
CS5172ED8
2500 Tape & Reel
95 Units/Rail
SOIC−8
CS5172EDR8
CS5173ED8
2500 Tape & Reel
95 Units/Rail
−40°C < T < 125°C
J
CS5173EDR8
CS5173EDR8G
2500 Tape & Reel
2500 Tape & Reel
SOIC−8
(Pb−Free)
CS5174ED8
95 Units/Rail
2500 Tape & Reel
95 Units/Rail
CS5174EDR8
CS5171GD8
CS5171GDR8
CS5171GDR8G
SOIC−8
2500 Tape & Reel
2500 Tape & Reel
SOIC−8
(Pb−Free)
CS5172GD8
CS5172GDR8
CS5173GD8
CS5173GDR8
CS5174GD8
CS5174GDR8
95 Units/Rail
2500 Tape & Reel
95 Units/Rail
0°C < T < 125°C
J
SOIC−8
2500 Tape & Reel
95 Units/Rail
2500 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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CS5171, CS5172, CS5173, CS5174
R2
4.87 k
D1
C4
V
OUT
−12 V
1
8
V
C
V
SW
+
MBRS120T3
22 mF
2
3
7
6
5
Test
NFB
PGND
AGND
C1
0.01 mF
+
C3
L1
4
22 mF
SS
V
CC
SS
22 mH
D2
MBRS120T3
V
5.0 V
CC
R3
+
R1
5.0 k
C2
22 mF
1.27 k
Figure 41. Additional Application Diagram, 5.0 V to −12 V/ 75 mA Inverting Converter
22 mH
MBRS120T3
3.3 V
5.0 V
GND
IN
O
10 mF
22 mF
3.6 k
V
(5)
CC
GND
PGND (7)
AGND (6)
V
SW
(8)
CS5171/3
(1 )
V
C
FB (2)
0.1 mF
1.3 k
200 pF
5.0 k
Figure 42. Additional Application Diagram, 3.3 V Input, 5.0 V/ 400 mA Output Boost Converter
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CS5171, CS5172, CS5173, CS5174
MBRS140T3
V
−12 V
GND
CC
P6KE−15A
1N4148
T1
47 mF
47 mF
+
+
+
1.0 mF
22 mF
V
(5)
CC
1:2
GND
PGND (7)
AGND (6)
V
(8)
+12 V
SW
MBRS140T3
10.72 k
CS5171/3
V
(1 )
FB (2)
C
47 nF
1.28 k
4.7 nF
2.0 k
Figure 43. Additional Application Diagram, 2.7 to 13 V Input, + 12 V/ 200 mA Output Flyback Converter
GND
V
(5)
GND
−5.0
V
C
(1 )
CC
1.1 k
5.0 k
22 mF
2.2 mF
CS5171/3
200 pF
Low
ESR
15 mH
V
SW
(8)
.01 mF
V
OUT
V
IN
AGND (6)
PGND (7)
FB (2)
300
Figure 44. Additional Application Diagram, −9.0 V to −28 V Input, −5.0 V/700 mA Output Inverted Buck Converter
22 mH
V
CC
22 mF
V
CC
(5)
PGND (7)
AGND (6)
GND
V
(8)
5.0 V
GND
SW
+
22 mF
+
37.24 k
CS5171/3
(1 )
22 mF
22 mH
V
C
Low
ESR
FB (2)
200 pF
.01 mF
5.0 k
12.76 k
Figure 45. Additional Application Diagram, 2.7 V to 28 V Input, 5.0 V Output SEPIC Converter
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19
CS5171, CS5172, CS5173, CS5174
R1
R2
1.245 k/0.1 W, 1%
99.755 k/0.1 W, 1%
GND
C1
.1 m
50 V
D1
C2
.1 m
50 V
D1
C3
.1 m
50 V
D1
D1
D1
D1
D1
1
8
V
C
V
SW
100 V
O
C10
.1 m
7
1N4148 1N4148 1N4148 1N4148 1N4148 1N4148 1N4148
2
3
PGND
FB
C11
.01 m
6
R3
2.0 k
Test
AGND
C4
C5
C6
C9
.1 m
C8
10 m
.1 m
50 V
.1 m
50 V
.1 m
50 V
C7
5
4
V
CC
SS
.1 m
50 V
GND
4.0 V
Figure 46. Additional Application Diagram, 4.0 V Input, 100 V/ 10 mA Output Boost Converter with
Output Voltage Multiplier
200 pF
D1
C6
C1
R1
1
8
V
SW
V
C
−12 V
5.0 k
0.01 mF
22 mF
2
3
4
7
6
5
FB
PGND
AGND
L1
15 mH
Test
SS
C3
+ 22 mF
D3
D2
SS
V
CC
+5.0 V
GND
C4
0.1 mF
GND
C5
22 mF
+
R2
R3
10.72 k
+12 V
1.28 k
Figure 47. Additional Application Diagram, 5.0 V Input, ± 12 V
Output Dual Boost Converter
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20
CS5171, CS5172, CS5173, CS5174
PACKAGE DIMENSIONS
SOIC−8
D SUFFIX
CASE 751−07
ISSUE AB
NOTES:
−X−
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
A
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
8
5
4
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
C
N X 45
_
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
SEATING
PLANE
−Z−
0.10 (0.004)
1.27 BSC
0.050 BSC
M
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
J
H
D
8
0
_
_
_
_
M
S
S
X
0.25 (0.010)
Z
Y
0.25
5.80
0.50 0.010
6.20 0.228
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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21
CS5171, CS5172, CS5173, CS5174
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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CS5171/D
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