CS5323-D_技术文档

CS5323

Three-Phase Buck

Controller with 5-Bit DAC

The CS5323 is a three–phase step down controller that incorporates

all control functions required to power next generation processors.

Proprietary multi–phase architecture guarantees balanced load current

distribution and reduces overall solution cost in high current

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2

applications. Enhanced V control architecture provides the fastest

possible transient response, excellent overall regulation, and ease of

use.

The multi–phase architecture reduces input and output filter ripple,

allowing for a reduction in filter size and inductor values with a

corresponding increase in the output inductor current slew rate.

20

1

SO–20L

DW SUFFIX

CASE 751D

Features

• Enhanced V Control Method

2

• 5–Bit DAC with 1.0% Tolerance

• Adjustable Output Voltage Positioning

• Programmable Frequency Set by Single Resistor

• 200 kHz to 800 kHz Operation (Per Phase)

• Current Sensed through Sense Resistors, or Buck Inductors

• Adjustable Current Sense Threshold

• Hiccup Mode Current Limit

• Over–Voltage Protection through Synchronous MOSFET’s

• Individual Current Limits for Each Phase

• On–Board Current Sense Amplifiers

• 3.3 V, 1.0 mA Reference Output

PIN CONNECTIONS AND

MARKING DIAGRAM

1

R

V

CC

OSC

COMP

GATE1

GATE2

GATE3

GND

V

FB

V

DRP

CS1

CS2

CS3

V

ID4

V

ID3

ID2

CS

REF

I

LIM

ID1

ID0

REF

V

A

WL, L

YY, Y

= Assembly Location

= Wafer Lot

= Year

• 5.0 V and/or 12 V Operation

• On/Off Control (through COMP Pin)

WW, W = Work Week

ORDERING INFORMATION

Device

Package

Shipping

CS5323GDW20

37 Units/Rail

SO–20L

CS5323GDWR20

1000 Tape & Reel

Semiconductor Components Industries, LLC, 2002

1

Publication Order Number:

August, 2002 – Rev. 6

CS5323/D

CS5323

L1

12 V

IN

300 nH

+

C13

D1

C4

3 × 16S0180M

5 V

IN

C5

1.0 µF

BAS40LT1

1.0 µF

Q1

MTD3302

R1

10 Ω

ENABLE

C12

1.0 nF

R10

8.0 k

L2

V

OUT

U1

C17

850 nH

C4

0.1 µF

Q2

R12

75 k

.01 µF

+ C16

8 ×

4SP560M

C11

U2

2.0 nF

C28

1.0 nF

V

CC

R

C18

OSC

D3

BAS40LT1

U3

R9

1.0 k

GATE1

GATE2

GATE3

Gnd

COMP

R6

7.5 k

V

C19

1.0 µF

Q3

FB

1.0 µF

V

DRP

MTD3302

L3

CS1

CS2

850 nH

V

ID4

Q4

CS3

CS

ID3

C20

3 ×

10 µF

R13

10 k

V

ID2

ID1

REF

V

I

C23

C24

LIM

C22

REF

ID0

.01 µF

C26

D5

V

C21

.01 µF

ID0

C27

1.0 µF

BAS40LT1

1.0 µF

Q5

Q6

V

R14

2.7 k

ID1

R17

30.1 k

MTD3302

R16

30.1 k

ID2

ID3

R15

30.1 k

L4

C25

0.1 µF

850 nH

U4

V

ID4

R18

1.0 k

R19

10 k

Figure 1. Application Diagram, 12 V to 1.7 V Converter

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CS5323

MAXIMUM RATINGS*

Rating

Value

150

Unit

°C

Operating Junction Temperature

Lead Temperature Soldering:

Storage Temperature Range

Reflow: (SMD styles only) (Note 1)

230 peak

–65 to +150

2.0

°C

ESD Susceptibility (Human Body Model)

kV

1. 60 second maximum above 183°C.

*The maximum package power dissipation must be observed.

MAXIMUM RATINGS

Pin Number

Pin Symbol

V

MAX

V

MIN

I

SINK

SOURCE

1

2

R

6.0 V

0 V

–0.3 V

0 V

1.0 mA

50 mA

1.0 mA

N/A

OSC

COMP

1.0 mA

3

V

FB

4

V

DRP

5–7

8

CS1–CS3

CS

REF

9

I

LIM

10

11–15

16

REF

VID0–4

Gnd

0.4 A, 1.0 µs, 100 mA

DC

17–19

20

GATE 1–3

16 V

–0.3 V

0.1 A, 1.0 µs, 25 mA DC 0.1 A, 1.0 µs, 25 mA DC

V

CC

N/A

0.4 A, 1.0 µs, 100 mA

DC

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CS5323

ELECTRICAL CHARACTERISTICS (0°C < T < 70°C; 0°C < T < 85°C; 4.7 V < V < 14 V; C = 100 pF,

GATE

A

J

CC

R

= 53.6 k, C

= 0.1 µF, C

= 0.1µF, DAC Code 10000, C

= 0.1 µF, I

≥ 1.0 V; unless otherwise specified.)

LIM

R(OSC)

COMP

REF

VCC

Characteristic

Voltage Identification DAC (0 = Connected to V ; 1 = Open or Pull–up to 3.3 V)

Test Conditions

Min

Typ

Max

Unit

SS

Accuracy (all codes)

Measure V = COMP

± 1.0

%

FB

V

ID4

V

ID3

V

ID2

V

ID1

V

ID0

1

–

1.064

1.089

1.114

1.139

1.163

1.188

1.213

1.238

1.262

1.287

1.312

1.337

1.361

1.386

1.411

1.436

1.460

1.485

1.510

1.535

1.559

1.584

1.609

1.634

1.658

1.683

1.708

1.733

1.757

1.782

1.807

1.832

1.00

1.075

1.100

1.125

1.150

1.175

1.200

1.225

1.250

1.275

1.300

1.325

1.350

1.375

1.400

1.425

1.450

1.475

1.500

1.525

1.550

1.575

1.600

1.625

1.650

1.675

1.700

1.725

1.750

1.775

1.800

1.825

1.850

1.25

1.086

1.111

1.136

1.162

1.187

1.212

1.237

1.263

1.288

1.313

1.338

1.364

1.389

1.414

1.439

1.465

1.490

1.515

1.540

1.566

1.591

1.616

1.641

1.667

1.692

1.717

1.742

1.768

1.793

1.818

1.843

1.869

1.50

V

kΩ

V

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Input Threshold

V

, V , V , V , V

ID3 ID2 ID1

ID4

ID0

Input Pull–up Resistance

Pull–up Voltage

, V , V , V , V

25

50

100

ID4

ID3

ID2

ID1

ID0

–

3.15

3.30

3.45

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CS5323

ELECTRICAL CHARACTERISTICS (continued) (0°C < T < 70°C; 0°C < T < 85°C; 4.7 V < V < 14 V; C

= 100 pF,

A

J

CC

GATE

R

53.6 k, C

= 0.1 µF, C

= 0.1µF, DAC Code 10000, C

= 0.1 µF, I

≥ 1.0 V; unless otherwise specified.)

LIM

R(OSC) =

COMP

REF

VCC

Characteristic

Voltage Feedback Error Amplifier

Bias Current (Note 2)

Test Conditions

Min

Typ

Max

Unit

0.9 V < V < 1.9 V

V

FB

17.6

15

19.0

30

20.6

60

µA

FB

COMP Source Current

COMP = 0.5 V to 2.0 V; V = 1.8 V; DAC = 00000

FB

COMP Sink Current

15

30

60

µA

COMP = 0.5 V to 2.0 V; V = 1.9 V; DAC = 00000

FB

COMP Discharge Threshold Voltage

–

0.20

0.27

0.34

V

–10 µA < I

< +10 µA

Transconductance

Output Impedance

Open Loop DC Gain

–

32

2.5

90

–

mmho

MΩ

COMP

–

Note 3

60

dB

0.01 µF

Unity Gain Bandwidth

PSRR @ 1 kHz

–

400

70

–

kHz

dB

V

–

V

= 1.8 V; COMP Open; DAC = 00000

= 1.9 V; COMP Open; DAC = 00000

COMP Max Voltage

COMP Min Voltage

2.4

–

2.7

0.1

–

FB

0.2

V

FB

Hiccup Latch Discharge Current

COMP Discharge Ratio

–

2.0

4.0

5.0

6.0

10

µA

–

PWM Comparators

Minimum Pulse Width

–

350

0.4

500

0.5

ns

V

Measured from CSx to GATE(H) with 60 mV step

between CSx and CS

REF

Channel Start Up Offset

V(CS1) = V(CS2) = V(CS3) = V(V

)

0.3

FB

V(CS ) = 0 V; Measure V(COMP) when

REF

GATE (H) 1, 2 switch high

GATEs

High Voltage

Measure V – GATEx, I

= 1.0 mA

GATEx

–

1.2

0.25

30

2.1

0.50

60

V

CC

Low Voltage

Measure GATEx, I

= 1.0 mA

GATEx

Rise Time GATE

Fall Time GATE

Oscillator

1.0 V < GATE < 8.0 V; V = 10 V

ns

CC

8.0 V > GATE > 1.0 V; V = 10 V

30

60

CC

Switching Frequency

R

= 53.6 k

220

300

600

–

250

400

800

1.00

120

280

500

1000

–

kHz

V

OSC

Note 3 R

= 32.4 k

= 16.2 k

OSC

R

Voltage

–

OSC

Phase Delay

Rising edge only

105

135

deg

Adaptive Voltage Positioning

V

Offset

CS1 = CS2 = CS3 = CS

, V = COMP

–20

360

–

20

mV

DRP

REF FB

Measure V

– COMP

DRP

Maximum V

Voltage

|(CS1 = CS2 = CS3) – C

| = 50 mV,

REF

465

570

DRP

V

FB

= COMP, Measure V

– COMP

DRP

Current Share Amp to V

Gain

–

2.7

3.0

3.5

V/V

DRP

2. The V Bias Current changes with the value of R

per Figure 4.

OSC

FB

3. Guaranteed by design. Not tested in production.

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CS5323

ELECTRICAL CHARACTERISTICS (continued) (0°C < T < 70°C; 0°C < T < 85°C; 4.7 V < V < 14 V; C

= 100 pF,

A

J

CC

GATE

R

53.6 k, C

= 0.1 µF, C

= 0.1µF, DAC Code 10000, C

= 0.1 µF, I

≥ 1.0 V; unless otherwise specified.)

LIM

R(OSC) =

COMP

REF

VCC

Characteristic

Test Conditions

Min

Typ

Max

Unit

Current Sensing and Sharing

CS1–CS3 Input Bias Current

V(CSx) = V(CS

) = 0 V

–

0.2

0.6

4.2

2.0

4.7

µA

REF

CS

Input Bias Current

–

REF

Current Sense Amplifier Gain

3.7

V/V

Current Sense Amp Mismatch

(The sum of gain and offset errors)

0 < (CSx – CS

Note 4

) < 50 mV

REF

–5.0

–

5.0

mV

Current Sense Amplifiers Input

Common Mode Range Limit

0

–

V

– 2

V

CC

Current Sense Input to I

Gain

0.25 V < 1.20 V

Note 4

5.0

7.5

–

6.5

15

8.0

V/V

mV/µs

µA

LIM

Current Limit Filter Slew Rate

Bias Current

40

1.0

115

I

0 < I

< 1.0 V

0.1

105

LIM

Single Phase Pulse by Pulse

Current Limit: V(CSx) –

–

75

mV

V(CS

)

REF

Current Share Amplifier Bandwidth

Note 4

1.0

3.2

–

mHz

V

Reference Output

V

REF

Output Voltage

3.3

3.4

0 mA < I(V

) < 1.0 mA

REF

General Electrical Specifications

V

CC

V

CC

V

CC

V

CC

Operating Current

Start Threshold

Stop Threshold

Hysteresis

V

= COMP(no switching)

–

23

4.60

4.4

28

mA

V

FB

GATEs switching, COMP charging

4.05

3.75

100

4.70

4.65

300

GATEs stop switching, COMP discharging

GATEs not switching, COMP not charging

V

200

mV

4. Guaranteed by design. Not tested in production.

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CS5323

PACKAGE PIN DESCRIPTION

PACKAGE PIN #

20 Lead SO Wide

1

PIN SYMBOL

FUNCTION

R

A resistor from this pin to ground sets operating frequency

OSC

and V bias current.

FB

2

3

COMP

Output of the error amplifier and input for the PWM

comparators.

V

FB

Voltage Feedback Pin. To use Adaptive Positioning, set the

light load offset voltage by connecting a resistor between V

FB

and CS

. The resistor and the V bias current determine

REF

FB

the offset. For no adaptive positioning connect V directly to

FB

CS

.

REF

4

V

DRP

Current sense output for adaptive voltage positioning (AVP).

The level of this pin above the DAC voltage is proportional to

the output current. Connect a resistor from this pin to V to

FB

set AVP or leave this pin open for no AVP.

5–7

CS1–CS3

Current sense inputs. Connect current sense network for the

corresponding phase to each CSx pin.

Reference for Current Sense Amplifiers. To balance input

offset voltages between the inverting and noninverting inputs

of the Current Sense Amplifiers, connect a resistor between

CS

and the output voltage. The value should be 1/3 of

REF

the value of the resistors connected to the CSx pins.

8

9

CS

REF

I

Sets the threshold for hiccup mode current limit. Connect to

reference through a resistive divider.

LIM

Reference output. Decouple with 0.1 µF.

10

REF

11–15

VID0–VID4

Voltage ID DAC inputs. These pins are internally pulled up to

3.3 V if left open.

16

17–19

20

Gnd

IC Gnd.

GATE1–3

GATE drive signal.

Power for IC.

V

CC

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CS5323

V

CC

V

CC

V

CC

3.3 V

REF

I

LIM

−

PH 1

Start

Stop

V

ID0

+

DAC

OUT

S

R

GATE

ID1

+

−

4.6 V

4.4 V

DAC

−

V

ID2

PWMC1

+

ID3

CO1

+

V

ID4

MAXC1

−

+

PH 2

FAULT

CO1

−

0.44 V

S

R

GATE

OVIC

−

+

−

R

PWMC2

+

CO2

+

MAXC2

−

PH 3

−

+

−

RESC

FAULT

0.44 V

+

S

R

CO2

−

CO1

CO2

CSA1

+

−

+

CS1

CS2

−

0.27 V

PWMC3

+

−

CO3

CSA2

+

V

ITotal

MAXC3

−

×

1.5

+

−

FAULT

Current

Source

Gen

FAULT

CO3

−

+

−

0.44 V

CO3

+

BIAS

CSA3

AVPA

OFFSET

CS3

−

2

1

DAC

OUT

5 µA

CS

REF

−

2

1

EA

PH 1

+

DAC

OUT

PH 2

PH 3

FAULT

OSC

R

OSC

V

FB

Gnd

V

DRP

COMP

Figure 2. Block Diagram

TYPICAL PERFORMANCE CHARACTERISTICS

900

800

700

80

60

40

20

0

600

500

400

300

200

100

10

20

30

40

50

60

70

10

20

30

40

50

Value, kΩ

60

70

80

R

Value, kΩ

R

OSC

Figure 3. Oscillator Frequency

Figure 4. V_FBBias Current vs. R_OSCValue

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CS5323

APPLICATIONS INFORMATION

FIXED FREQUENCY MULTI–PHASE CONTROL

comparator rises and terminates the pwm cycle. If the

inductor starts the cycle with a higher current the PWM

cycle will terminate earlier providing negative feedback.

In a multi–phase converter, multiple converters are

connected in parallel and are switched on at different times.

This reduces output current from the individual converters

and increases the apparent ripple frequency. Because several

converters are connected in parallel, output current can ramp

up or down faster than a single converter (with the same

value output inductor) and heat is spread among multiple

components.

The CS5323 provides a C input for each phase, but the

X

CS , V and COMP inputs are common to all phases.

REF

FB

Current sharing is accomplished by referencing all phases to

the same V and COMP pins, so that a phase with a larger

FB

current signal will turn off earlier than phases with a smaller

current signal.

Including both current and voltage information in the

feedback signal allows the open loop output impedance of

the power stage to be controlled. If the COMP pin is held

steady and the inductor current changes there must also be

a change in the output voltage. Or, in a closed loop

configuration when the output current changes, the COMP

pin must move to keep the same output voltage. The required

change in the output voltage or COMP pin depends on the

scaling of the current feedback signal and is calculated as

The CS5323 uses a three–phase, fixed frequency,

enhanced V architecture. Each phase is delayed 120° from

2

the previous phase. Normally the GATE transitions high at

the beginning of each oscillator cycle. Inductor current

ramps up until the combination of the current sense signal

and the output ripple trip the PWM comparator and bring the

GATE low. Once the GATE goes low, it will remain low until

the beginning of the next oscillator cycle. While the GATE

2

is high, the enhanced V loop will respond to line and load

DV + R CSA Gain DI

S

transients. Once the GATE is low, the loop will not respond

again until the beginning of the next cycle. Therefore,

The single–phase power stage output impedance is;

2

constant frequency, enhanced V will typically respond

Single Stage Impedance + DVńDI + R CSA Gain.

within the off–time of the converter.

The enhanced V architecture measures and adjusts

current in each phase. An additional input (C ) for inductor

current information has been added to the V loop for each

S

2

The multi–phase power stage output impedance is the

single–phase output impedance divided by the number of

phases. The output impedance of the power stage determines

how the converter will respond during the first few µs of a

transient before the feedback loop has repositioned the

COMP pin.

X

2

phase as shown in Figure 5.

The peak output current of each phase can also be

calculated from;

SWNODE

CS

L

X

R

L

+

CSA

+

V

* V

OFFSET

R

COMP

R

FB

CSA Gain

S

OFFSET

I

(per phase) +

pkout

S

CS

REF

PWM

COMP

Figure 6 shows the step response of a single phase with the

COMP pin at a fixed level. Before T1 the converter is in

normal steady state operation. The inductor current provides

the pwm ramp through the Current Share Amplifier. The

pwm cycle ends when the sum of the current signal, voltage

signal and OFFSET exceed the level of the COMP pin. At

T1 the output current increases and the output voltage sags.

The next pwm cycle begins and the cycle continues longer

than previously while the current signal increases enough to

V

OUT

+

V

FB

+

E.A.

+

DAC

OUT

+

COMP

Figure 5. Enhanced V²Feedback and Current

Sense Scheme

make up for the lower voltage at the V pin and the cycle

FB

ends at T2. After T2 the output voltage remains lower than

at light load and the current signal level is raised so that the

sum of the current and voltage signal is the same as with the

original load. In a closed loop system the COMP pin would

move higher to restore the output voltage to the original

level.

The inductor current is measured across R , amplified by

S

CSA and summed with the OFFSET and Output Voltage at

the non–inverting input of the PWM comparator. The

inductor current provides the PWM ramp and as inductor

current increases the voltage on the positive pin of the pwm

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9

CS5323

considered when setting the I

threshold. If a more

LIM

accurate current sense is required than inductive sensing can

provide, current can be sensed through a resistor as shown

in Figure 5.

SWNODE

Current Sharing Accuracy

PCB traces that carry inductor current can be used as part

of the current sense resistance depending on where the

current sense signal is picked off. For accurate current

sharing, the current sense inputs should sense the current at

the same point for each phase and the connection to the

V

FB

(V

)

OUT

CSA Out

CS

should be made so that no phase is favored. (In some

REF

COMP – Offset

CSA Out + V

cases, especially with inductive sensing, resistance of the

pcb can be useful for increasing the current sense

resistance.) The total current sense resistance used for

calculations must include any pcb trace between the CS

FB

T1

T2

Figure 6. Open Loop Operation

inputs and the CS

input that carries inductor current.

REF

Current Sense Amplifier Input Mismatch and the value of

the current sense element will determine the accuracy of

current sharing between phases. The worst case Current

Sense Amplifier Input Mismatch is 5 mV and will typically

be within 3 mV. The difference in peak currents between

phases will be the CSA Input Mismatch divided by the

current sense resistance. If all current sense elements are of

equal resistance a 3 mV mismatch with a 2 mΩ sense

resistance will produce a 1.5 A difference in current between

phases.

Inductive Current Sensing

For lossless sensing current can be sensed across the

inductor as shown below in Figure 7. In the diagram, L is the

output inductance and R is the inherent inductor resistance.

L

To compensate the current sense signal the values of R1 and

C1 are chosen so that L/R = R1 × C1. If this criteria is met

L

the current sense signal will be the same shape as the

inductor current, the voltage signal at Cx will represent the

instantaneous value of inductor current and the circuit can be

analyzed as if a sense resistor of value R was used as a sense

L

Operation at > 50% Duty Cycle

For operation at duty cycles above 50% Enhanced V

resistor (R ).

2

S

will exhibit subharmonic oscillation unless a compensation

ramp is added to each phase. A circuit like the one on the left

side of Figure 8 can be added to each current sense network

to implement slope compensation. The value of R1 can be

varied to adjust the ramp size.

R1

SWNODE

CS

X

+

L

+

CSA

C1

OFFSET

R

L

CS

REF

PWM

Switch Node

GATE(L)X

COMP

+

V

OUT

V

FB

E.A.

+

DAC

OUT

COMP

R1

25 k

3 k

CS

X

Figure 7. Lossless Inductive Current Sensing with

Enhanced V²

1.0 nF

0.1 µF

.01 µF

When choosing or designing inductors for use with

inductive sensing, tolerances and temperature effects should

be considered. Cores with a low permeability material or a

large gap will usually have minimal inductance change with

temperature and load. Copper magnet wire has a

temperature coefficient of 0.39% per °C. The increase in

winding resistance at higher temperatures should be

CS

REF

MMBT2222LT1

Existing Current

Sense Circuit

Slope Comp

Circuit

Figure 8. External Slope Compensation Circuit

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10

CS5323

Ramp Size and Current Sensing

Because the current ramp is used for both the PWM ramp

and to sense current, the inductor and sense resistor values

will be constrained. A small ramp will provide a quick

transient response by minimizing the difference over which

the COMP pin must travel between light and heavy loads,

but a steady state ramp of 25 mV

or greater is typically

P–P

required to prevent pulse skipping and minimize pulse width

jitter. For resistive current sensing the combination of the

inductor and sense resistor values must be chosen to provide

a large enough steady state ramp. For large inductor values

the sense resistor value must also be increased.

For inductive current sensing the RC network must meet

the requirement of L/R = R × C to accurately sense the AC

L

and DC components of the current the signal. Again the

values for L and R will be constrained in order to provide

L

a large enough steady state ramp with a compensated current

sense signal. A smaller L, or a larger R than optimum might

L

Figure 9. Inductive Sensing waveform during a Step

be required. But unlike resistive sensing, with inductive

sensing small adjustments can be made easily with the

values of R and C to increase the ramp size if needed.

with Fast RC Time Constant (50 ms/div)

If RC is chosen to be smaller (faster) than L/R , the AC

Current Limit

L

portion of the current sensing signal will be scaled larger

than the DC portion. This will provide a larger steady state

ramp, but circuit performance will be affected and must be

evaluated carefully. The current signal will overshoot during

transients and settle at the rate determined by R × C. It will

eventually settle to the correct DC level, but the error will

decay with the time constant of R × C. If this error is

excessive it will effect transient response, adaptive

positioning and current limit. During transients the COMP

pin will be required to overshoot along with the current

Two levels of overcurrent protection are provided. Any

time the voltage on a Current Sense pin exceeds CS

by

REF

more than the Single Phase Pulse by Pulse Current Limit, the

pwm comparator for that phase is turned off. This provides

fast peak current protection for individual phases. The

outputs of all the currents are also summed and filtered to

compare an averaged current signal to the voltage on the

I

pin. If this voltage is exceeded, the fault latch trips and

LIM

the SS capacitor is discharged by a 5 µA source until the

COMP pin reaches 0.2 V. Then soft–start begins. The

converter will continue to operate in this mode until the fault

condition is corrected.

signal in order to maintain the output voltage. The V

DRP

will also overshoot during transients and possibly slow the

response. Single phase overcurrent will trip earlier than it

would if compensated correctly and hiccup mode current

limit will have a lower threshold for fast rise step loads than

for slowly rising output currents.

Overvoltage Protection

Overvoltage protection (OVP) is provided as a result of

2

the normal operation of the enhanced V control topology

with synchronous rectifiers. The control loop responds to an

overvoltage condition within 400 ns, causing the top

MOSFET’s to shut off, and the synchronous MOSFET’s to

turn on. This results in a “crowbar” action to clamp the

output voltage and prevents damage to the load. The

regulator will remain in this state until the overvoltage

condition ceases or the input voltage is pulled low.

The waveforms in Figure 9 show a simulation of the

current sense signal and the actual inductor current during

a positive step in load current with values of L = 500 nH,

R = 1.6 mΩ, R1 = 20 k and C1 = .01 µF. For ideal current

L

signal compensation the value of R1 should be 31 kΩ. Due

to the faster than ideal RC time constant there is an

overshoot of 50% and the overshoot decays with a 200 µs

time constant. With this compensation the I

LIM

Transient Response and Adaptive Positioning

For applications with fast transient currents the output

filter is frequently sized larger than ripple currents require in

threshold must be set more than 50% above the full load

current to avoid triggering hiccup mode during a large

output load step.

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11

CS5323

order to reduce voltage excursions during transients.

increases the V

pin increases proportionally and the

DRP

Adaptive voltage positioning can reduce peak–peak output

voltage deviations during load transients and allow for a

smaller output filter. The output voltage can be set higher at

light loads to reduce output voltage sag when the load

current is stepped up and set lower during heavy loads to

reduce overshoot when the load current is stepped up. For

low current applications a droop resistor can provide fast

accurate adaptive positioning. However at high currents, the

loss in a droop resistor becomes excessive. For example; in

a 50 A converter a 1 mΩ resistor to provide a 50 mV change

in output voltage between no load and full load would

dissipate 2.5 Watts.

V

pin current offsets the V bias current and causes the

DRP FB

output voltage to further decrease.

The V and V pins take care of the slower and DC

FB

DRP

voltage positioning. The first few µs are controlled primarily

by the ESR and ESL of the output filter. The transition

between fast and slow positioning is controlled by the ramp

size and the error amp compensation. If the ramp size is too

large or the error amp too slow there will be a long transition

to the final voltage after a transient. This will be most

apparent with lower capacitance output filters.

Note: Large levels of adaptive positioning can cause pulse

width jitter.

Lossless adaptive positioning is an alternative to using a

droop resistor, but must respond quickly to changes in load

current. Figure 10 shows how adaptive positioning works.

The waveform labeled normal shows a converter without

adaptive positioning. On the left, the output voltage sags

when the output current is stepped up and later overshoots

when current is stepped back down. With fast (ideal)

adaptive positioning the peak to peak excursions are cut in

half. In the slow adaptive positioning waveform the output

voltage is not repositioned quickly enough after current is

stepped up and the upper limit is exceeded.

Error Amp Compensation

The transconductance error amplifier can be configured to

provide both a slow soft–start and a fast transient response.

C4 in the main applications diagram controls soft–start. A

0.1 µF capacitor with the 30 µA error amplifier output

capability will allow the output to ramp up at 0.3 V/ms or

1.5 V in 5 ms.

R10 is connected in series with C4 to allow the error

amplifier to slew quickly over a narrow range during load

transients. Here the 30 µA error amplifier output capability

works against 8 kΩ (R10) to limit the window of fast slewing

too 240 mV – enough to allow for fast transients, but not

enough to interfere with soft–start. This window will be

noticeable as a step in the COMP pin voltage at start–up. The

size of this step must be kept smaller than the Channel

Start–Up Offset (nominally 0.4 V) for proper soft–start

operation. If adaptive positioning is used the R9 and R8 form

Normal

a divider with the V

end held at the DAC voltage during

DRP

Fast Adaptive Positioning

SlowAdaptive Positioning

Limits

start–up, which effectively makes the Channel Start–Up

Offset larger.

C12 is included for error amp stability. A capacitive load

is required on the error amp output. Use of values less than

1 nF may result in error amp oscillation of several MHz.

Figure 10. Adaptive Positioning

The CS5323 uses two methods to provide fast and

accurate adaptive positioning. For low frequency

C11 and the parallel resistance of the V resistor (R9)

FB

positioning the V and V

pins are used to adjust the

FB

DRP

and the V

resistor (R6) are used to roll off the error amp

DRP

output voltage with varying load currents. For high

frequency positioning, the current sense input pins can be

used to control the power stage output impedance. The

transition between fast and slow positioning is adjusted by

the error amp compensation.

The CS5323 can be configured to adjust the output

voltage based on the output current of the converter. The

adaptive positioning circuit is designed to select the DAC

setting as the maximum output voltage. (Refer to Figure 1 on

page 2.)

gain. C28 adds a zero to the error amp response to boost the

phase near the crossover frequency.

UVLO

The CS5323 has one undervoltage lockout function

connected to the V

pin. In applications where the

CC

converter is powered from multiple voltages, additional

UVLO protection might be required if the voltage powering

the controller can turn on before other voltages.

For the 12 V converter in Figure 1, the CS5323 UVLO

IN

function monitors the 5.0 V supply. If the 5.0 V supply

comes up before the 12 V supply, the COMP pin will rise

until it reaches the upper rail or until the 12 V supply comes

up and the converter comes into regulation. If the delay

between the 5.0 V and 12 V supplies is too long, soft–start

will be compromised. A diode connected from the 12 V

supply to the COMP pin can hold the COMP pin down until

the 12 V supply starts to come up. Or, if a higher UVLO

To set the no–load positioning a resistor (R9) is placed

between the output voltage and V pin. The V bias

FB

current will develop a voltage across the resistor to decrease

the output voltage. The V bias current is dependent on the

FB

value of ROSC. See Figure 4 on the datasheet.

During no load conditions the V

pin is at the same

DRP

voltage as the V pin, so none of the V bias current flows

FB

through the V

resistor (R6). When output current

DRP

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12

CS5323

threshold is needed, a circuit like the one in Figure 11 will

lock out the converter until the 12 V supply reaches about

7.0 V.

controller. The slots should typically not be placed between

the controller and the output voltage or in the return path of

the gate drive. Additional power and ground planes or

islands can be added as required for a particular layout.

Output filter components should be placed on wide planes

connected directly to the load to minimize resistive drops

during heavy loads and inductive drops and ringing during

transients. If required, the planes for the output voltage and

return can be interleaved to minimize inductance between

the filter and load.

+12 V

+5 V

50 k

COMP

Voltage feedback should be taken from a point of the

output or the output filter that doesn’t favor any one phase.

If the feedback connection is closer to one inductor than the

others the ripple associated with that phase may appear

larger than the ripple associated with the other phases and

poor current sharing can result.

100 k

The current sense signal is typically tens of milli–volts.

Noise pick–up should be avoided wherever possible.

Current feedback traces should be routed away from noisy

areas such as switch nodes and gate drive signals. The paths

should be matched as well as possible. It is especially

important that all current sense signals be picked off at

similar points for accurate current sharing. If the current

signal is taken from a place other than directly at the inductor

any additional resistance between the pick–off point and the

inductor appears as part of the inherent inductor resistance

and should be considered in design calculations. Capacitors

for the current feedback networks should be placed as close

to the current sense pins as practical.

Figure 11. External UVLO Circuit

Remote Sense

In some applications that require remote output voltage

sensing, there are conditions when the path of the feedback

signal can be broken. In a voltage regulator module (VRM)

the remote voltage feedback sense point is typically off the

module. If the module is powered apart from the intended

application, the feedback will be left open. On a

motherboard, the feedback path might be broken when the

processor socket is left open. Without the feedback

connection the output voltage is likely to exceed the

intended voltage. To protect the circuit from overvoltage

conditions, a resistor can be connected between the local

output voltage and the remote sense line as shown in Figure

12.

DESIGN PROCEDURE

Current Sensing, Power Stage and

Output Filter Components

Local V

Remote V

OUT

1. Choose the output filter components to meet peak

transient requirements. The formula below can be

used to provide an approximate starting point for

capacitor choice, but will be inadequate to calculate

actual values.

DV

+ (DIńDT) ESL ) DI ESR

100 Ω

PEAK

Ideally the output filter should be simulated with

models including ESR, ESL, circuit board parasitics

and delays due to switching frequency and converter

response. Typically both bulk capacitance

(electrolytic, Oscon, etc,) and low impedance

capacitance (ceramic chip) will be required. The bulk

capacitance provides “hold up” during the converter

response. The low impedance capacitance reduces

steady state ripple and bypasses the bulk capacitance

during slewing of output current.

CS

Network

V

Network

FB

REF

Figure 12. Remote Sense Connection

Layout Guidelines

With the fast rise, high output currents of microprocessor

applications parasitic inductance and resistance should be

considered when laying out the power, filter and feedback

signal sections of the board. Typically a multi–layer board

with at least one ground plane is recommended. If the layout

is such that high currents can exist in the ground plane

underneath the controller or control circuitry, the ground

plane can be slotted to reroute the currents away from the

2. For inductive current sensing (only) choose the

current sense network RC to provide a 25 mV

minimum ramp during steady state operation.

V

ńV

OUT IN

R + (V * V

IN

)

OUT

F C 25 mV

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13

CS5323

Then choose the inductor value and inherent resistance

I

is the current limit threshold.

OUT(LIM)

to satisfy L/R = R × C.

L

For the overcurrent to work properly the inductor time

constant (L/R) should be ≤ the Current sense RC. If the

RC is too fast, during step loads the current waveform

will appear larger than it is (typically for a few hundred

µs) and may trip the current limit at a level lower than

the DC limit.

For ideal current sense compensation the ratio of L and

R

L

is fixed, so the values of L and R will be a

L

compromise typically with the maximum value R

L

limited by conduction losses or inductor temperature

rise and the minimum value of L limited by ripple

current.

Adaptive Positioning

3. For resistive current sensing choose L and R to

S

7. To set the amount of voltage positioning below the

DAC setting at no load connect a resistor (R ( ))

provide a steady state ramp greater than 25 mV.

V FB

LńR + (V * V

IN

) T

OUT

ń25 mV

ON

S

between the output voltage and the V pin. Choose

FB

R ( ) as;

V FB

Again the ratio of L and R is fixed and the values of

L

R

+ NL PositionńV

Bias Current

FB

V(FB)

L and R will be a compromise.

S

4. Calculate the high frequency output impedance

(ConverterZ) of the converter during transients. This

is the impedance of the Output filter ESR in parallel

with the power stage output impedance (PwrstgZ)

and will indicate how far from the original level

(∆VR) the output voltage will typically recover to

within one switching cycle. For a good transient

response ∆VR should be less than the peak output

voltage overshoot or undershoot.

See Figure 4 for V Bias Current.

FB

8. To set the difference in output voltage between no load

and full load, connect a resistor (R ) between the

V(DRP)

V

DRP

and V pins. R

can be calculated in two

FB

V(DRP)

steps. First calculate the difference between the V

DRP

and V pin at full load. (The V voltage should be

FB

the same as the DAC voltage during closed loop

operation.) Then choose the R to source enough

V(DRP)

current across R ( ) for the desired change in output

V FB

voltage.

DVR + ConverterZ ESR

DV

+ I

OUTFL

R CS to V

Gain

DRP

V(DRP)

PwrstgZ ESR

ConverterZ +

where:

PwrstgZ ) ESR

R = R or R for one phase;

L

S

where:

I

is the full load output current.

OUTFL

PwrstgZ + R CSA Gainń3

S

R

+ DV

R

ńDV

V(FB) OUT

V(DRP)

DRP

Multiply the converterZ by the output current step size

to calculate where the output voltage should recover to

within the first switching cycle after a transient. If the

ConverterZ is higher than the value required to recover

to where the adaptive positioning is set the remainder

of the recovery will be controlled by the error amp

compensation and will typically recover in 10 – 20 µs.

Calculate Input Filter Capacitor Current Ripple

The procedure below assumes that phases do not overlap

and output inductor ripple current (P–P) is less than the

average output current of one phase.

9. Calculate Input Current

V

I

OUT

Efficiency V

DVR + DI

OUT

ConverterZ

I

IN

+

(

)

IN

Make sure that ∆VR is less than the expected peak

transient for a good transient response.

10. Calculate Duty Cycle (per phase).

V

5. Adjust L and R or R as required to meet the best

OUT

L

S

Duty Cycle +

(

)

Efficiency V

combination of transient response, steady state output

voltage ripple and pulse width jitter.

IN

11. Calculate Apparent Duty Cycle.

Current Limit

Apparent Duty Cycle + Duty Cycle # of Phases

When the sum of the Current Sense amplifiers (V

)

ITOTAL

12. Calculate Input Filter Capacitor Ripple Current. Use

the chart in Figure 13 to calculate the normalized

exceeds the voltage on the I

pin the part will enter hiccup

LIM

mode. For inductive sensing the I

pin voltage should be

LIM

ripple current (K ) based on the reciprocal of

RMS

set based on the inductor resistance (or current sense

resistor) at max temperature and max current. To set the level

Apparent Duty Cycle. Then multiply the input current

by K to obtain the Input Filter Capacitor Ripple

RMS

of the I

pin:

LIM

Current.

6. V

+ R I

CS to I Gain

LIM

I(LIM)

OUT(LIM)

Ripple (RMS) + I K

IN

RMS

where:

R is R or R

L

S;

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14

CS5323

4.00

3.50

3.00

2.50

2.00

1.50

3. n/a

4. PwrstgZ

+ R CSA Gainń3

L

+ 1.5 mW 4.2ń3 + 2.1 mW

PwrstgZ ESR

+

ConverterZ

PwrstgZ ) ESR

2.8 mW 1.5 mW

2.8 mW ) 1.5 mW

^ 1.0 mW

1.00

0.50

DVR + 1.0 mW 60 A + 60 mV

5. n/a

0.00

0

15

10

5

Current Limit

1/ Apparent Duty Cycle

6.

V

+ R I

OUT(LIM)

CS to I Gain

LIM

I(LIM)

L

Figure 13. Normalized Input Filter Capacitor

Ripple Current

+ 1.5 mW 75 A 6.5 + 731 mV

Adaptive Positioning

DESIGN EXAMPLE

R

7.

8.

+ NL PositionńV

FB

+ 20 mVń19 mA ^ 1.00 kW

Bias Current

V(FB)

Choose the component values for lossless current sensing,

adaptive positioning and current limit for a 12 V to 1.5 V 60

A converter. The adaptive positioning is chosen 20 mV

+ R I

+ 2 mW 60 A 3 + 360 mV

Current Sense to V

Gain

DRP

DV

L

OUT

DRP

below the maximum V

at no load and 70 mV below the

OUT

no–load position with 60 A out. The peak output voltage

transient is 100 mV max during a 60 A step current. The

overcurrent limit is nominally 75 A.

+ DV R ńDV

OUT

+ 360 mV 1.00 kWń50 mV + 7.2 kW

R

DRP

V(FB)

V(DRP)

1.6 V 60 A

9.

I

IN

+

+ 9.4 A

Current Sensing, Power Stage

and Output Filter Components

1. Assume 1.5 mΩ of output filter ESR.

(

)

0.85 12V

IN

1.6 V

)

0.85 12 V

IN

Duty Cycle +

+ 0.16

10.

(

+ (V * V

) (V

OUT

ńV ń(F C 25 mV)

OUT IN)

2. R

IN

+ (12 * 1.5) (1.5ń12)ń(250 k .01 mF 25 mV)

+ 21 kW å Choose 20 kW

11. Apparent Duty Cycle + 0.16 3.0 + 0.48

12.RMS ripple is 9.4 A 1.0 + 9.4 A

LńR + .01 mF 20 kW + 200 ms

L

Choose R + 2.0 mW

L

L + 2 mW 200 ms + 400 nH

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15

CS5323

PACKAGE DIMENSIONS

SO–20L

DW SUFFIX

CASE 751D–05

ISSUE F

D

A

q

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES

PER ASME Y14.5M, 1994.

20

11

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD

PROTRUSION.

E

B

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION SHALL

BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT

MAXIMUM MATERIAL CONDITION.

1

10

MILLIMETERS

DIM MIN

MAX

2.65

0.25

0.49

0.32

12.95

7.60

20X B

A

A1

B

C

D

E

2.35

0.10

0.35

0.23

12.65

7.40

M

S

B

T

0.25

A

e

1.27 BSC

A

H

h

10.05

0.25

0.50

0

10.55

0.75

0.90

7

L

SEATING

PLANE

q

_

^18Xe

A1

C

T

PACKAGE THERMAL DATA

Parameter

SO–20L

17

Unit

°C/W

R

Typical

Θ

JC

JA

90

2

V is a trademark of Switch Power, Inc.

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make

changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any

particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all

liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be

validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.

SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death

may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC

and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees

arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that

SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATION

Literature Fulfillment:

JAPAN: ON Semiconductor, Japan Customer Focus Center

2–9–1 Kamimeguro, Meguro–ku, Tokyo, Japan 153–0051

Phone: 81–3–5773–3850

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada

Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada

Email: ONlit@hibbertco.com

Email: r14525@onsemi.com

ON Semiconductor Website: http://onsemi.com

For additional information, please contact your local

Sales Representative.

N. American Technical Support: 800–282–9855 Toll Free USA/Canada

CS5323/D

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16


型号：	CS5323-D
厂家：	ONSEMI
描述：	Three-Phase Buck Controller with 5-Bit DAC 三相降压控制器，5位DAC 控制器
文件：	总16页 (文件大小：137K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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