DM74ALS273WM [ONSEMI]
D Flip-Flop;
| 型号： | DM74ALS273WM |
| 厂家： | 
ONSEMI |
| 描述： | D Flip-Flop 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总7页 (文件大小：84K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 1984
Revised February 2000
DM74ALS273
Octal D-Type Edge-Triggered Flip-Flop with Clear
General Description
These monolithic, positive-edge-triggered flip-flops utilize
TTL circuitry to implement D-type flip-flop logic with a direct
clear input.
Features
■ Switching specifications at 50 pF
■ Switching specifications guaranteed over full tempera-
ture and VCC range
Information at the D inputs meeting the setup requirements
is transferred to the Q outputs on the positive-going edge
of the clock pulse. Clock triggering occurs at a particular
voltage level and is not directly related to the transition time
of the positive-going pulse. When the clock input is at
either the HIGH or LOW level, the D input signal has no
effect at the output.
■ Buffer-type outputs and improved AC offer significant
advantage over DM74LS273.
■ Advanced oxide-isolated, ion-implanted Schottky TTL
process
■ Functionally
and
pin-for-pin
compatible
with
DM74LS273.
Ordering Code:
Order Number
DM74ALS273WM
DM74ALS273SJ
DM74ALS273MSA
DM74ALS273N
Package Number
M20B
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
M20D
MSA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
N20A
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
© 2000 Fairchild Semiconductor Corporation
DS006216
www.fairchildsemi.com
Function Table
Logic Diagram
(Each Flip-Flop)
Inputs
Output
Clear
Clock
D
X
H
L
Q
L
L
H
H
H
X
↑
H
↑
L
L
X
Q0
L = LOW State
H = HIGH State
X = Don’t Care
↑ = Positive Edge Transition
= Previous Condition of Q
Q
0
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2
Absolute Maximum Ratings(Note 1)
Supply Voltage
Input Voltage
7V
7V
Operating Free Air Temperature Range
Storage Temperature Range
Typical θJA
0°C to +70°C
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
−65°C to +150°C
N Package
60.0°C/W
79.0°C/W
M Package
Recommended Operating Conditions
Symbol
Parameter
Min
4.5
2
Nom
Max
Units
V
VCC
VIH
VIL
Supply Voltage
5
5.5
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Current
LOW Level Output Current
Clock Frequency
V
0.8
−2.6
24
V
IOH
IOL
mA
mA
MHz
ns
fCLK
0
14
14
10
10↑
15↑
0↑
0
35
tW(CLK)
Width of Clock Pulse
HIGH
LOW
LOW
ns
tW
Width of Clear Pulse
ns
tSU
Data Setup Time (Note 2)
ns
Clear Inactive
tH
Data Hold Time
ns
TA
Free Air Operating Temperature
70
°C
Note 2: The (↑) arrow indicates the positive edge of the Clock is used for reference.
Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at VCC = 5V, T = 25°C.
A
Symbol
Parameter
Input Clamp Voltage
Conditions
= 4.5V, I = −18 mA
Min
Typ
Max
Units
V
V
V
V
V
−1.5
V
V
IK
CC
CC
CC
I
HIGH Level
= 4.5V
I
= −2.6 mA
= −400 µA
= 12 mA
OL
2.4
3.3
OH
OH
Output Voltage
= 4.5V to 5.5V
I
V
− 2
V
OH
CC
V
LOW Level
I
0.25
0.35
0.4
0.5
0.1
20
V
OL
V
= 4.5V
CC
Output Voltage
I
= 24 mA
V
OL
I
I
I
I
I
Input Current @ Maximum Input Voltage
HIGH Level Input Current
LOW Level Input Current
Output Drive Current
Supply Current
V
V
V
V
V
= 5.5V, V = 7V
mA
µA
mA
mA
mA
mA
I
CC
CC
CC
CC
CC
IH
= 5.5V, V = 2.7V
IH
IL
IH
= 5.5V, V = 0.4V
−0.2
−112
20
IL
= 5.5V
= 5.5V
V
= 2.25V
−30
O
O
Outputs HIGH
Outputs LOW
11
19
CC
Outputs OPEN
29
Switching Characteristics
over recommended operating free air temperature range.
Symbol
Parameter
Conditions
From
To
Min
Max
Units
f
Maximum Clock Frequency
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
V
R
C
= 4.5V to 5.5V
35
MHz
MAX
CC
t
t
t
= 500Ω
= 50 pF
PHL
PLH
PHL
L
L
Clear
Clock
Clock
Any Q
Any Q
Any Q
4
2
3
18
12
15
ns
ns
ns
3
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Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
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4
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
Package Number MSA20
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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7
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