EFC2K103NUZTDG [ONSEMI]
双 N 沟道，功率 MOSFET，12V，40A，1.8mΩ;
| 型号： | EFC2K103NUZTDG |
| 厂家： | 
ONSEMI |
| 描述： | 双 N 沟道，功率 MOSFET，12V，40A，1.8mΩ |
| 文件： | 总8页 (文件大小：614K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MOSFET - Power for 1-Cell
Lithium-ion Battery
Protection
EFC2K103NUZ
12 V, 1.8 mW, 40 A, Dual N-Channel
www.onsemi.com
This power MOSFET features a low on−state resistance. This
device is suitable for applications such as power switches of portable
machines. Best suited for 1−cell lithium−ion battery applications.
V
SSS
R
MAX
I MAX
S
SS(ON)
12 V
1.8 mW @ 4.5 V
1.9 mW @ 3.8 V
2.6 mW @ 3.1 V
4.2 mW @ 2.5 V
40 A
Features
• 2.5 V drive
• Common−Drain type
• ESD Diode−Protected Gate
• Pb−Free, Halogen Free and RoHS Compliance
ELECTRICAL CONNECTION
N−Channel
Typical Applications
• 1−Cell Lithium−ion Battery Charging and Discharging Switch
6, 7, 9, 10
SPECIFICATIONS
1 : Source1
Rg
ABSOLUTE MAXIMUM RATINGS at T = 25°C
A
2 : Source1
3 : Gate1
8
3
Parameter
Source to Source Voltage
Gate to Source Voltage
Source Current (DC)
Symbol
Value
12
Unit
V
4 : Source1
5 : Source1
6 : Source2
7 : Source2
8 : Gate2
9 : Source2
10 : Source2
V
SSS
GSS
V
8
V
Rg
I
S
40
A
Source Current (Pulse)
I
SP
140
A
PW ≤ 10 mS, Duty Cycle ≤ 1%
Rg = 300 W
1, 2, 4, 5
Total Dissipation (Note 1)
Junction Temperature
Storage Temperature
P
3.3
150
W
°C
°C
T
T
PIN ASSIGNMENT
J
T
stg
−55 to +150
3
1
2
4
5
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
6
7
9
8
10
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
MARKING DIAGRAM
Junction to Ambient (Note 1)
R
37
°C/W
q
JA
PB
AYWZZ
2
1. Surface mounted on ceramic substrate (5000 mm × 0.8 mm)
WLCSP10
PB = Specific Device Code
3.54x1.77x0.140
CASE 567XB
A
Y
= Assembly Location
= Year
W
= Work Week
ZZ = Assembly Lot
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
September, 2019 − Rev. 1
EFC2K103NUZ/D
EFC2K103NUZ
ELECTRICAL CHARACTERISTICS at T = 25°C
A
Value
Typ
−
Min
12
Max
−
Parameter
Symbol
Conditions
Unit
V
Source to Source Breakdown Voltage
Zero Gate Voltage Source Current
Gate to Source Leakage Current
Gate Threshold Voltage
V
I
= 1 mA, V = 0 V
Test Circuit 1
Test Circuit 1
Test Circuit 2
Test Circuit 3
Test Circuit 4
Test Circuit 4
Test Circuit 4
(BR)SSS
S
GS
I
V
V
V
I
= 10 V, V = 0 V
−
−
1
mA
mA
V
SSS
SS
GS
SS
GS
I
=
8 V, V = 0 V
−
−
1
GSS
SS
V
R
(th)
= 6 V, I = 1 mA
0.4
0.8
0.85
1.0
−
1.3
1.8
1.9
2.6
GS
S
Static Source to Source On−State
Resistance
(on)
= 5 A, V = 4.5 V
1.25
1.35
1.7
mW
mW
mW
SS
S
GS
I
S
I
S
= 5 A, V = 3.8 V
GS
= 5 A, V = 3.1 V
GS
I
S
= 5 A, V = 2.5 V
Test Circuit 4
1.2
2.1
4.2
mW
GS
Turn−ON Delay Time
Rise Time
t (on)
V
R
= 6 V, V = 3.8 V, I = 5 A,
= 10 kW
−
−
−
−
−
25
100
165
148
62
−
−
−
−
−
ms
ms
ms
ms
nC
d
SS
GS
S
G
t
r
Test Circuit 5
Turn−OFF Delay Time
Fall Time
t (off)
d
t
f
Total Gate Charge
Qg
V
= 6 V, V = 3.8 V, I = 5 A
SS GS S
Test Circuit 6
Forward Source to Source Voltage
V
F(S−S)
I
S
= 3 A, V = 0 V
Test Circuit 7
−
0.75
1.2
V
GS
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
ORDERING INFORMATION
†
Device
Marking
Package
Shipping (Qty / Packing)
EFC2K103NUZTDG
PB
WLCSP10, 3.54 × 1.77 × 0.140
(Pb−Free / Halogen Free)
5,000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
2
EFC2K103NUZ
TYPICAL CHARACTERISTICS
10
6
4.5 V
3.8 V
V
SS
= 6 V
9
8
7
6
5
4
3
2
1
0
3.1 V
Single Pulse
5
4
3
2
2.5 V
T
= 75°C
= 25°C
A
T
A
T
A
= −25°C
T
A
= 25°C
1
Single Pulse
0
0.0000
0.0050
0.0100
0.0150 0.0200
0
0.3
0.6
0.9
1.2
1.5
1.8
Gate-to-Source Voltage, V (V)
Source-to-Source Voltage, V (V)
GS
SS
Figure 1. IS − VSS
Figure 2. IS − VGS
5
5
4.5
4
I
S
= 5 A
I
= 5 A
4.5
S
Single Pulse
Single Pulse
4
3.5
3
3.5
3
T
A
= 75°C
2.5
2
2.5
2
V
= 2.5 V
T
= 25°C
GS
A
T
A
= −25°C
1.5
1
1.5
1
V
GS
= 3.1 V
V
= 3.8 V
GS
V
GS
= 4.5 V
0.5
0.5
−60 −40 −20
0
20 40 60 80 100 120 140 160
1
2
3
4
5
6
7
8
Gate-to-Source Voltage, V (V)
Ambient Temperature, T (5C)
GS
A
Figure 3. RSS(on) − VGS
Figure 4. RSS(on) − TA
10
1
V
= 0 V
GS
t
d(off)
Single Pulse
100
10
1
t
f
T
A
= 75°C
t
T
A
= 25°C
r
T
A
= −25°C
T
V
V
= 25°C
= 6 V
= 3.8 V
A
0.1
t
SS
d(on)
GS
I
S
= 5 A
Single Pulse
0.01
0
0.2
0.4
0.6
0.8
1.0
1.2
1
10
Forward Source-to-Source Voltage, V
(V)
Gate Resistance, R (kW)
F(S-S)
G
Figure 5. IS − VF(S-S)
Figure 6. SW Time − RG
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3
EFC2K103NUZ
TYPICAL CHARACTERISTICS (Continued)
4
3.5
3
3.5
3
T
= 25°C
SS
= 5 A
A
Surface mounted on
ceramic substrate
(5000 mm × 0.8 mm)
V
I
= 6 V
2
S
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
0
10
20
30
40
50
60
0
25
50
75
100
125
150 175
Total Gate Charge, Q (nC)
Ambient Temperature, T (5C)
G
A
Figure 7. VGS − QG
Figure 8. PT − TA
1000
100
10
I
= 140 A (PW ≤ 10 ms)
SP
10 ms
I
= 40 A
S
100 ms
1 ms
10 ms
DC
Operation
Operation in this
area is limited by R
100 ms
1
0.1
SS(on)
T
= 25°C
A
Single pulse
When mounted on ceramic substrate
2
(5000 mm x 0.8 mm)
0.01
0.01
0.1
0
10
Source-to-Source Voltage, V (V)
SS
Figure 9. Safe Operating Area
100
10
Duty Cycle = 0.5
0.2
0.1
0.05
0.02
1
0.01
Single Pulse
0.1
0.00001
0.0001
0.001
0.01
Pulse Time, P (s)
0.1
1
10
T
Figure 10. Thermal Response
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4
EFC2K103NUZ
TEST CIRCUITS ARE EXAMPLES OF MEASURING FET1 SIDE
V
/ I
I
GSS
(BR)SSS SSS
S2
S2
G2
G1
G2
G1
A
V
SS
A
S1
S1
V
GS
When FET1 is measured,
Gate and Source of FET2
are short−circuited.
Figure 12. Test Circuit
2
Figure 11. Test Circuit
1
V
GS
(th)
R
(on)
SS
S2
S2
IS
G2
G2
G1
A
When FET1 is measured,
Gate and Source of FET2
are short−circuited.
V
G1
V
SS
S1
S1
V
GS
V
GS
Figure 13. Test Circuit
3
Figure 14. Test Circuit
4
t (on), t t (off), t
f
Qg
S2
G2
d
r, d
RL
S2
A
G2
When FET1 is measured,
Gate and Source of FET2
are short−circuited.
V
I
G
= 1 mA
RL
SS
G1
G1
R
g
S1
S1
When FET1 is measured,
Gate and Source of FET2
are short−circuited.
V
V
SS
PG
Figure 15. Test Circuit
5
Figure 16. Test Circuit
6
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5
EFC2K103NUZ
V
F(S−S)
S2
I
S
G2
G1
V
S1
When FET1 is mea-
sured, + 4.5 V is added
to V of FET2.
GS
Figure 17. Test Circuit
7
NOTE: When FET2 is measured, the position of FET1 and FET2 is switched.
NOTE: Since the EFC2K103NUZ is a MOSFET product, please avoid using this device in the vicinity of highly charged objects. Please
contact sales for use except the designated application.
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6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WLCSP10, 3.54x1.77x0.14
CASE 567XB
ISSUE O
DATE 09 OCT 2018
4
5
6
7
1
2
9 10
3
8
3
8
1
2
9 10
4
5
6
7
GENERIC
XXXX = Specific Device Code
MARKING DIAGRAM*
A
Y
W
ZZ
G
= Assembly Location
= Year
= Work Week
= Assembly Lot Code
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
XXXXXG
AYWZZG
(Note: Microdot may be in either location)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON98952G
WLCSP10, 3.54x1.77x0.14
PAGE 1 OF 1
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