ESD7104 [ONSEMI]
Transient Voltage Suppressors;
| 型号： | ESD7104 |
| 厂家： | 
ONSEMI |
| 描述： | Transient Voltage Suppressors |
| 文件： | 总9页 (文件大小：314K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ESD7104
Transient Voltage
Suppressors
Low Capacitance ESD Protection for
High Speed Data
www.onsemi.com
The ESD7104 transient voltage suppressor is designed to protect
high speed data lines from ESD. Ultra−low capacitance and low ESD
clamping voltage make this device an ideal solution for protecting
voltage sensitive high speed data lines. The flow−through style
package allows for easy PCB layout and matched trace lengths
necessary to maintain consistent impedance between high speed
differential lines such as USB 3.0 and HDMI.
MARKING
DIAGRAM
UDFN10
CASE 517BB
7M MG
G
7M
M
G
= Specific Device Code (tbd)
= Date Code
= Pb−Free Package
Features
• Low Capacitance (0.3 pF Typical, I/O to GND)
• Low ESD Clamping Voltage
(Note: Microdot may be in either location)
• Protection for the Following IEC Standards:
PIN CONFIGURATION
AND SCHEMATIC
IEC 61000−4−2 (Level 4)
• UL Flammability Rating of 94 V−0
N/C N/C GND N/C N/C
• SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
10
9
8
7
6
1
2
3
4
5
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
I/O I/O GND I/O I/O
Typical Applications
• USB 3.0
I/O
Pin 1 Pin 2
I/O
I/O
Pin 4 Pin 5
I/O
• eSATA 3.0
• Thunderbolt (Light Peak)
• HDMI 1.3/1.4
• Display Port
GND
Pin 3
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
Rating
Symbol
Value
−55 to +125
−55 to +150
260
Unit
°C
Operating Junction Temperature Range
Storage Temperature Range
T
J
=
T
stg
°C
Lead Solder Temperature −
Maximum (10 Seconds)
T
L
°C
IEC 61000−4−2 Contact (ESD)
IEC 61000−4−2 Air (ESD)
ESD
ESD
15
15
kV
kV
ORDERING INFORMATION
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
Device
ESD7104MUTAG
Package
Shipping
UDFN10
(Pb−Free)
3000 / Tape &
Reel
SZESD7104MUTAG UDFN10
(Pb−Free)
3000 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
See Application Note AND8308/D for further description of
survivability specs.
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
October, 2016 − Rev. 3
ESD7104/D
ESD7104
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)
A
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
V
Reverse Working Voltage
Breakdown Voltage
V
RWM
I/O Pin to GND
I = 1 mA, I/O Pin to GND
5.0
V
BR
5.5
V
T
Reverse Leakage Current
Clamping Voltage (Note 1)
Clamping Voltage (Note 2)
Clamping Voltage (Note 3)
I
V
= 5 V, I/O Pin to GND
1.0
10
mA
V
R
RWM
V
I
PP
= 1 A, I/O Pin to GND (8 x 20 ms pulse)
C
C
C
V
V
IEC61000−4−2, 8 KV Contact
See Figures 1 and 2
V
I
PP
I
PP
=
=
8 A
16 A
14.1
19.5
V
Junction Capacitance
Junction Capacitance
C
C
V
V
= 0 V, f = 1 MHz between I/O Pins
0.2
0.3
0.35
pF
pF
J
J
R
= 0 V, f = 1 MHz between I/O Pins and GND
0.3
R
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Surge current waveform per Figure 5.
2. For test procedure see Figures 3 and 4 and application note AND8307/D.
3. ANSI/ESD STM5.5.1 − 2008 Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z = 50 W, t = 100 ns, t = 4 ns, averaging window; t = 30 ns to t = 60 ns.
0
p
r
1
2
80
70
10
0
60
50
40
−10
−20
−30
30
−40
20
10
−50
−60
−70
−80
0
−10
−20
0
20
40
60
TIME (ns)
80
100 120 140
−20
0
20
40
60
80
100 120 140
TIME (ns)
Figure 1. IEC61000−4−2 +8 KV Contact
Clamping Voltage
Figure 2. IEC61000−4−2 −8 KV Contact
Clamping Voltage
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2
ESD7104
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
I
peak
First Peak
Current
(A)
100%
90%
Test Volt-
age (kV)
Current at
30 ns (A)
Current at
60 ns (A)
Level
1
2
3
4
2
4
6
8
7.5
15
4
8
2
4
6
8
I @ 30 ns
22.5
30
12
16
I @ 60 ns
10%
t
P
= 0.7 ns to 1 ns
Figure 3. IEC61000−4−2 Spec
Oscilloscope
ESD Gun
TVS
50 W
Cable
50 W
Figure 4. Diagram of ESD Clamping Voltage Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
100
t
r
PEAK VALUE I
@ 8 ms
RSM
90
80
70
60
50
40
30
20
PULSE WIDTH (t ) IS DEFINED
P
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
HALF VALUE I /2 @ 20 ms
RSM
t
P
10
0
0
20
40
t, TIME (ms)
60
80
Figure 5. 8 X 20 ms Pulse Waveform
www.onsemi.com
3
ESD7104
22
20
18
16
14
12
10
8
−22
−20
−18
−16
−14
−12
−10
−8
6
−6
4
2
0
−4
−2
0
0
2
4
6
8
10 12 14 16 18 20 22 24
VOLTAGE (V)
0
−2 −4 −6 −8 −10 −12 −14 −16 −18 −20 −22 −24
VOLTAGE (V)
Figure 6. Positive TLP I−V Curve
Figure 7. Negative TLP I−V Curve
50 W Coax
Cable
Transmission Line Pulse (TLP) Measurement
L
Attenuator
S
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 8. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 9 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels.
÷
50 W Coax
Cable
I
M
V
M
10 MW
DUT
V
C
Oscilloscope
Figure 8. Simplified Schematic of a Typical TLP
System
Figure 9. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
www.onsemi.com
4
ESD7104
Without ESD
With ESD7104
Figure 10. USB3.0 Eye Diagram with and without ESD7104. 5.0 Gb/s, 400 mVPP
Without ESD
With ESD7104
Figure 11. HDMI1.4 Eye Diagram with and without ESD7104. 3.4 Gb/s, 400 mVPP
Without ESD
With ESD7104
Figure 12. ESATA3.0 Eye Diagram with and without ESD7104. 6 Gb/s, 400 mVPP
www.onsemi.com
5
ESD7104
4
2
ESD7104 IO−GND
0
−2
−4
−6
−8
−10
1.E+06
1.E+07
1.E+08
1.E+09
1.E+10
FREQUENCY (Hz)
Figure 13. ESD7104 Insertion Loss
www.onsemi.com
6
ESD7104
USB 3.0 Type A
Connector
StdA_SSTX+
Vbus
StdA_SSTX−
ESD7104
D−
ESD7L5.0
GND_DRAIN
StdA_SSRX+
D+
GND
StdA_SSRX−
Figure 14. USB3.0 Standard A Connector Layout Diagram
USB 3.0 Micro B
Connector
ESD7104
Vbus
D−
D+
ID
GND
ESD7104
MicB_SSTX−
MicB_SSTX+
GND_DRAIN
MicB_SSRX−
MicB_SSRX+
Figure 15. USB3.0 Micro B Connector Layout Diagram
www.onsemi.com
7
ESD7104
HDMI
Type A Connector
ESD7104
D2+
GND
D2−
D1+
GND
D1−
ESD7104
D0+
GND
D0−
CLK+
GND
CLK−
CEC
N/C (or HEC_DAT – HDMI1.4)
SCL
SDA
GND
5V
HPD (and HEC_DAT – HDMI1.4)
NUP4114
Figure 16. HDMI Layout Diagram
e S ATA
Connector
GND
A+
ESD7104
A−
GND
B−
B+
GND
Figure 17. eSATA Layout Diagram
www.onsemi.com
8
ESD7104
PACKAGE DIMENSIONS
UDFN10 2.5x1, 0.5P
CASE 517BB
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM TERMINAL.
L
L
D
B
E
A
L1
PIN ONE
REFERENCE
DETAIL A
OPTIONAL
CONSTRUCTIONS
MILLIMETERS
2X
0.10 C
DIM
A
MIN
0.45
0.00
MAX
0.55
0.05
A1
A3
b
2X
0.10
C
MOLD CMPD
TOP VIEW
EXPOSED Cu
0.13 REF
0.15
0.35
0.25
0.45
b2
D
DETAIL B
2.50 BSC
1.00 BSC
0.50 BSC
A3
A
A3
E
0.10
0.08
C
C
e
L
0.30
---
0.40
0.05
A1
L1
DETAIL B
OPTIONAL
10X
A1
SEATING
PLANE
CONSTRUCTION
C
SIDE VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
2X b2
10X
L
10X
0.50
DETAIL A
2X
0.45
5
1
10
6
1.30
e
8X b
PACKAGE
OUTLINE
0.10
0.05
C
C
A
B
8X
0.25
NOTE 3
0.50
PITCH
BOTTOM VIEW
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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ESD7104/D
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