ESD7361XV2T1G [ONSEMI]
ESD Protection Diodes;
| 型号： | ESD7361XV2T1G |
| 厂家： | 
ONSEMI |
| 描述： | ESD Protection Diodes |
| 文件： | 总9页 (文件大小：132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ESD7361, SZESD7361
ESD Protection Diodes
Low Capacitance ESD Protection Diode
for High Speed Data Line
The ESD7361 Series ESD protection diodes are designed to protect
high speed data lines from ESD. Ultra−low capacitance make this
device an ideal solution for protecting voltage sensitive high speed
data lines.
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MARKING
DIAGRAMS
Features
• Low Capacitance (0.55 pF Max, I/O to GND)
• Protection for the Following IEC Standards:
♦ IEC61000−4−2 (ESD): Level 4 15 kV Contact
♦ IEC61000−4−4 (EFT): 40 A −5/50 ns
♦ IEC61000−4−5 (Lightning): 1 A (8/20 ms)
• ISO 10605 (ESD) 330 pF/2 kW 15 kV Contact
• SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
2
SOD−323
CASE 477
7H
M
1
1
2
SOD−523
CASE 502
7X
1
2
SOD−923
CASE 514AB
2 M
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
X, XX = Specific Device Code
M
= Date Code
• Wireless Charger
• Near Field Communications
PIN CONFIGURATION
AND SCHEMATIC
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
Rating
Symbol
Value
−55 to +125
−55 to +150
260
Unit
°C
Operating Junction Temperature Range
Storage Temperature Range
T
J
1
2
T
stg
°C
Cathode
Anode
Lead Solder Temperature −
Maximum (10 Seconds)
T
L
°C
IEC 61000−4−2 Contact (ESD)
IEC 61000−4−2 Air (ESD)
ISO 10605 330 pF/2 kW Contact (ESD)
ESD
ESD
ESD
15
15
15
kV
kV
kV
ORDERING INFORMATION
See detailed ordering and shipping information on page 6 of
this data sheet.
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
November, 2016 − Rev. 3
ESD7361/D
ESD7361, SZESD7361
ELECTRICAL CHARACTERISTICS
I
(T = 25°C unless otherwise noted)
A
I
F
Symbol
Parameter
Maximum Reverse Peak Pulse Current
Clamping Voltage @ I
I
PP
V
C
PP
V
C
V V
BR RWM
V
Working Peak Reverse Voltage
RWM
V
I
V
F
R
T
I
R
Maximum Reverse Leakage Current @ V
I
RWM
V
Breakdown Voltage @ I
Test Current
BR
T
I
T
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
I
PP
Uni−Directional TVS
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)
A
Parameter
Reverse Working Voltage
Breakdown Voltage
Symbol
Conditions
Min
Typ
Max
Unit
V
V
RWM
5
16
V
BR
I = 1 mA; pin 1 to pin 2
16.5
V
T
Reverse Leakage Current
I
R
V
RWM
V
RWM
= 5.0 V
= 15 V
<1
20
1000
1000
nA
nA
Clamping Voltage (Note 2)
Clamping Voltage (Note 2)
Junction Capacitance
V
I
I
= 8 A
31
34
V
V
C
PP
PP
V
C
= 16 A
C
V
V
= 0 V, f = 1 MHz
= 0 V, f < 1 GHz
0.55
0.55
pF
J
R
R
Dynamic Resistance
Insertion Loss
R
TLP Pulse
0.735
W
DYN
f = 1 MHz
f = 5 GHz
0.01
2
dB
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. For test procedure see Figures 9 and 10 and application note AND8307/D.
2. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z = 50 W, t = 100 ns, t = 4 ns, averaging window; t = 30 ns to t = 60 ns.
0
p
r
1
2
1.E−03
1.E−04
1.E−05
1.E−06
1.E−07
1.E−08
1.E−09
1.E−10
1.E−11
1.E−12
1.E−13
1
0.8
0.6
0.4
0.2
0
6
8
10
(V)
12
0
5
10
15
VOLTAGE (V)
20
25
30
0
2
4
14
16
18
V
Bias
Figure 1. Typical IV Characteristics
Figure 2. Typical CV Characteristics
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2
ESD7361, SZESD7361
1
0.5
0
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
−0.5
−1
−1.5
−2
−2.5
−3
−3.5
−4
1.E+07
1.E+08
1.E+09
1.E+07 5.E+08 1.E+09 2.E+09 2.E+09 3.E+09
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 3. Typical Insertion Loss
ESD7361HT1G (SOD323)
Figure 4. Typical Capacitance Over Frequency
ESD7361HT1G (SOD323)
1
0.5
0
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
−0.5
−1
−1.5
−2
−2.5
−3
−3.5
−4
1.E+07
1.E+08
1.E+09
1.E+07
1.E+09 2.E+09
3.E+09 4.E+09
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 5. Typical Insertion Loss
ESD7361XV2T1G (SOD523)
Figure 6. Typical Capacitance Over Frequency
ESD7361XV2T1G (SOD523)
1
0.5
0
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
−0.5
−1
−1.5
−2
−2.5
−3
−3.5
−4
1.E+07
1.E+08
FREQUENCY (Hz)
1.E+09
1.E+07
1.E+09 2.E+09
3.E+09 4.E+09
FREQUENCY (Hz)
Figure 7. Typical Insertion Loss
ESD7361P2T5G (SOD923)
Figure 8. Typical Capacitance Over Frequency
ESD7361P2T5G (SOD923)
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3
ESD7361, SZESD7361
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
I
peak
First Peak
Current
(A)
100%
90%
Test Volt-
age (kV)
Current at
30 ns (A)
Current at
60 ns (A)
Level
1
2
3
4
2
4
6
8
7.5
15
4
8
2
4
6
8
I @ 30 ns
22.5
30
12
16
I @ 60 ns
10%
t
P
= 0.7 ns to 1 ns
Figure 9. IEC61000−4−2 Spec
Oscilloscope
ESD Gun
TVS
50 W
Cable
50 W
Figure 10. Diagram of ESD Clamping Voltage Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
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4
ESD7361, SZESD7361
25
20
15
10
5
−25
−20
−15
−10
−5
0
0
0
5
10
15
20
25
30
35
40
0
−2
−4
−6
−8
−10
−12
−14
V , VOLTAGE (V)
C
V , VOLTAGE (V)
C
Figure 11. Positive TLP I−V Curve
Figure 12. Negative TLP I−V Curve
NOTE: TLP parameter: Z = 50 W, t = 100 ns, t = 300 ps, averaging window: t = 30 ns to t = 60 ns. V is the equivalent voltage
IEC
0
p
r
1
2
stress level calculated at the secondary peak of the IEC 61000−4−2 waveform at t = 30 ns with 2 A/kV. See TLP description
below for more information.
50 W Coax
Cable
Transmission Line Pulse (TLP) Measurement
L
Attenuator
S
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 13. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 14 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels.
÷
50 W Coax
Cable
I
M
V
M
10 MW
DUT
V
C
Oscilloscope
Figure 13. Simplified Schematic of a Typical TLP
System
Figure 14. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
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5
ESD7361, SZESD7361
ORDERING INFORMATION
Device
†
Package
Shipping
ESD7361HT1G
SOD−323
(Pb−Free)
3000 / Tape & Reel
3000 / Tape & Reel
8000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
8000 / Tape & Reel
ESD7361XV2T1G
ESD7361P2T5G
SOD−523
(Pb−Free)
SOD−923
(Pb−Free)
SZESD7361HT1G
SZESD7361XV2T1G
SZESD7361P2T5G
SOD−323
(Pb−Free)
SOD−523
(Pb−Free)
SOD−923
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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6
ESD7361, SZESD7361
PACKAGE DIMENSIONS
SOD−323
CASE 477−02
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
H
E
2. CONTROLLING DIMENSION: MILLIMETERS.
3. LEAD THICKNESS SPECIFIED PER L/F DRAWING
WITH SOLDER PLATING.
D
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
5. DIMENSION L IS MEASURED FROM END OF RADIUS.
1
E
b
2
MILLIMETERS
DIM MIN NOM MAX
0.80
INCHES
NOM MAX
1.00 0.031 0.035 0.040
0.10 0.000 0.002 0.004
0.006 REF
MIN
A
0.90
0.05
A1 0.00
A3
A
A3
0.15 REF
0.32
0.12 0.177 0.003 0.005 0.007
1.70
1.25
b
C
D
E
L
0.25
0.089
1.60
1.15
0.08
2.30
0.4 0.010 0.012 0.016
1.80 0.062 0.066 0.070
1.35 0.045 0.049 0.053
0.003
H
2.50
2.70 0.090 0.098 0.105
E
L
A1
C
NOTE 5
NOTE 3
SOLDERING FOOTPRINT*
0.63
0.025
0.83
0.033
1.60
0.063
2.85
0.112
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
ESD7361, SZESD7361
PACKAGE DIMENSIONS
SOD−523
CASE 502
ISSUE E
−X−
D
NOTES:
6. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
−Y−
7. CONTROLLING DIMENSION: MILLIMETERS.
8. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH.
MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF
BASE MATERIAL.
E
9. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PRO-
TRUSIONS, OR GATE BURRS.
1
2
2X b
MILLIMETERS
M
0.08
X Y
DIM
A
b
c
D
E
HE
L
MIN
0.50
0.25
0.07
1.10
0.70
1.50
NOM
0.60
0.30
0.14
1.20
MAX
0.70
0.35
0.20
1.30
0.90
1.70
TOP VIEW
0.80
1.60
A
0.30 REF
0.20
L2
0.15
0.25
c
HE
RECOMMENDED
SOLDERING FOOTPRINT*
SIDE VIEW
1.80
2X
0.48
2X
0.40
2X
L
PACKAGE
OUTLINE
DIMENSION: MILLIMETERS
2X
L2
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
BOTTOM VIEW
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8
ESD7361, SZESD7361
PACKAGE DIMENSIONS
SOD−923
CASE 514AB
ISSUE C
NOTES:
−X−
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH.
MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF
BASE MATERIAL.
−Y−
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PRO-
TRUSIONS, OR GATE BURRS.
E
1
2
MILLIMETERS
DIM MIN NOM MAX
INCHES
NOM MAX
2X b
MIN
0.08 X
Y
A
b
c
0.34
0.15
0.07
0.75
0.55
0.95
0.37
0.20
0.12
0.80
0.60
0.40
0.25
0.17
0.85
0.65
1.05
0.013 0.015 0.016
0.006 0.008 0.010
0.003 0.005 0.007
0.030 0.031 0.033
0.022 0.024 0.026
0.037 0.039 0.041
0.007 REF
TOP VIEW
D
E
A
H
1.00
E
L
0.19 REF
0.10
L2 0.05
0.15
0.002 0.004 0.006
c
H
SOLDERING FOOTPRINT*
E
SIDE VIEW
1.20
2X
2X
0.25
0.36
2X
L
PACKAGE
OUTLINE
DIMENSIONS: MILLIMETERS
2X
L2
See Application Note AND8455/D for more mounting details
BOTTOM VIEW
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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◊
ESD7361/D
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