ESD8016MUTAG_技术文档

ESD8016

ESD Protection Diode

Low Capacitance Array for High Speed

Data Lines

The ESD8016 surge protection is specifically designed to protect

USB 3.0/3.1 and Thunderbolt interfaces from ESD. Ultra−low

capacitance and low ESD clamping voltage make this device an ideal

solution for protecting voltage sensitive high speed data lines. The

flow−through style package allows for easy PCB layout and matched

trace lengths necessary to maintain consistent impedance between

high speed differential lines.

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MARKING

DIAGRAM

UDFN8

CASE 517CX

6AMG

G

Features

6A

M

G

= Specific Device Code

= Date Code

= Pb−Free Package

• Low Capacitance (0.32 pF Max, I/O to GND)

• Protection for the Following IEC Standards:

(Note: Microdot may be in either location)

IEC 61000−4−2 (Level 4)

• Low ESD Clamping Voltage

PIN CONFIGURATION

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

I/O

8

I/O

7

I/O

6

I/O

5

Compliant

Typical Applications

• USB 3.0/3.1

• Thunderbolt

• Display Port

1

2

3

4

I/O

GND

GND I/O

MAXIMUM RATINGS (T = 25°C unless otherwise noted)

J

ORDERING INFORMATION

Rating

Symbol

Value

−55 to +125

−55 to +150

260

Unit

°C

†

Device

ESD8016MUTAG

Package

Shipping

Operating Junction Temperature Range

Storage Temperature Range

T

J

UDFN8

(Pb−Free)

3000 / Tape & Reel

T

stg

°C

Lead Solder Temperature −

Maximum (10 Seconds)

T

L

°C

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

IEC 61000−4−2 Contact (ESD)

IEC 61000−4−2 Air (ESD)

ESD

15

kV

Stresses exceeding those listed in the Maximum Ratings table may damage the

device. If any of these limits are exceeded, device functionality should not be

assumed, damage may occur and reliability may be affected.

See Application Note AND8308/D for further description of

survivability specs.

1

Publication Order Number:

October, 2017 − Rev. 1

ESD8016/D

ESD8016

I/O I/O

I/O

I/O I/O

I/O

Pin 1 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8

Pins 2, 3

Note: Common GND − Only Minimum of 1 GND connection required

=

Figure 1. Pin Schematic

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2

ESD8016

ELECTRICAL CHARACTERISTICS

A

I

(T = 25°C unless otherwise noted)

I

PP

Symbol

Parameter

R

DYN

V

RWM

Working Peak Voltage

I

R

Maximum Reverse Leakage Current @ V

RWM

V

BR

V

Breakdown Voltage @ I

V

RWM HOLD

C

BR

T

I

V

R

T

C

I

Test Current

I

T

V

HOLD

Holding Reverse Voltage

Holding Reverse Current

Dynamic Resistance

Maximum Peak Pulse Current

HOLD

I

R

DYN

R

DYN

−I

PP

I

PP

V

C

= V

+ (I * R

)

HOLD

PP

DYN

V

Clamping Voltage @ I

PP

C

V

C

= V

+ (I * R

)

HOLD

PP

DYN

ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)

A

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

V

Reverse Working Voltage

Breakdown Voltage

V

RWM

I/O Pin to GND

I = 1 mA, I/O Pin to GND

3.3

V

BR

5.5

7.0

V

T

Reverse Leakage Current

Holding Reverse Voltage

Holding Reverse Current

Clamping Voltage (Note 1)

I

V

= 3.3 V, I/O Pin to GND

1.0

mA

V

R

RWM

V

I/O Pin to GND

1.19

25

HOLD

I

I/O Pin to GND

mA

V

IEC61000−4−2, 8 KV Contact

See Figures 2 and 3

C

Clamping Voltage

TLP (Note 2)

See Figures 6 through 9

4.9

−5.0

V

I

PP

I

PP

= 8 A

= −8 A

IEC 61000−4−2 Level 2 equivalent

( 4 kV Contact, 4 kV Air)

C

I

PP

I

PP

= 16 A

= −16 A

8.4

−9.5

IEC 61000−4−2 Level 4 equivalent

( 8 kV Contact, 15 kV Air)

Dynamic Resistance

Junction Capacitance

R

I/O Pin to GND

GND to I/O Pin

0.44

0.49

W

DYN

C

V

R

V

R

V

R

V

R

= 0 V, f = 1 MHz between I/O Pins and GND

= 0 V, f = 2.5 GHz between I/O Pins and GND

= 0 V, f = 5.0 GHz between I/O Pins and GND

= 0 V, f = 1 MHz, between I/O Pins

0.32

pF

J

0.25

0.16

1. For test procedure see Figures 4 and 5 and application note AND8307/D.

2. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.

TLP conditions: Z = 50 W, t = 100 ns, t = 4 ns, averaging window; t = 30 ns to t = 60 ns.

0

p

r

1

2

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

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3

ESD8016

TIME (ns)

Figure 2. IEC61000−4−2 +8 kV Contact ESD

Clamping Voltage

Figure 3. IEC61000−4−2 −8 kV Contact

Clamping Voltage

IEC61000−4−2 Waveform

IEC 61000−4−2 Spec.

I

peak

First Peak

Current

(A)

100%

90%

Test Volt-

age (kV)

Current at

30 ns (A)

Current at

60 ns (A)

Level

1

2

3

4

2

4

6

8

7.5

15

4

8

2

4

6

8

I @ 30 ns

22.5

30

12

16

I @ 60 ns

10%

t

P

= 0.7 ns to 1 ns

Figure 4. IEC61000−4−2 Spec

Oscilloscope

ESD Gun

50 W

Cable

50 W

Figure 5. Diagram of ESD Clamping Voltage Test Setup

The following is taken from Application Note

AND8307/D − Characterization of ESD Clamping

Performance.

systems such as cell phones or laptop computers it is not

clearly defined in the spec how to specify a clamping voltage

at the device level. ON Semiconductor has developed a way

to examine the entire voltage waveform across the ESD

protection diode over the time domain of an ESD pulse in the

form of an oscilloscope screenshot, which can be found on

the datasheets for all ESD protection diodes. For more

information on how ON Semiconductor creates these

screenshots and how to interpret them please refer to

AND8307/D and AND8308/D.

ESD Voltage Clamping

For sensitive circuit elements it is important to limit the

voltage that an IC will be exposed to during an ESD event

to as low a voltage as possible. The ESD clamping voltage

is the voltage drop across the ESD protection diode during

an ESD event per the IEC61000−4−2 waveform. Since the

IEC61000−4−2 was written as a pass/fail spec for larger

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4

ESD8016

V

C

= V

+ (I * R

)

HOLD

PP

DYN

V , VOLTAGE (V)

C

V , VOLTAGE (V)

C

Figure 6. Positive TLP I−V Curve

Figure 7. Negative TLP I−V Curve

NOTE: TLP parameter: Z = 50 W, t = 100 ns, t = 300 ps, averaging window: t = 30 ns to t = 60 ns. V is the equivalent voltage

IEC

0

p

r

1

2

stress level calculated at the secondary peak of the IEC 61000−4−2 waveform at t = 30 ns with 2 A/kV. See TLP description

below for more information.

50 W Coax

Cable

Transmission Line Pulse (TLP) Measurement

L

Attenuator

S

Transmission Line Pulse (TLP) provides current versus

voltage (I−V) curves in which each data point is obtained

from a 100 ns long rectangular pulse from a charged

transmission line. A simplified schematic of a typical TLP

system is shown in Figure 8. TLP I−V curves of ESD

protection devices accurately demonstrate the product’s

ESD capability because the 10s of amps current levels and

under 100 ns time scale match those of an ESD event. This

is illustrated in Figure 9 where an 8 kV IEC 61000−4−2

current waveform is compared with TLP current pulses at

8 A and 16 A. A TLP I−V curve shows the voltage at which

the device turns on as well as how well the device clamps

voltage over a range of current levels. For more information

on TLP measurements and how to interpret them please

refer to AND9007/D.

÷

50 W Coax

Cable

I

M

V

M

10 MW

DUT

V

C

Oscilloscope

Figure 8. Simplified Schematic of a Typical TLP

System

Figure 9. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms

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5

ESD8016

IO−GND

Figure 10. IV Characteristics

Figure 11. CV Characteristics

Figure 12. RF Insertion Loss

Figure 13. Capacitance over Frequency

TABLE 1. RF Insertion Loss: Application Description

rd

Data Rate

(Gb/s)

Fundamental Frequency

3

Harmonic Frequency

(GHz)

ESD8016 Insertion Loss

(dB)

(GHz)

Interface

USB 3.0

5.0

10

2.5 (m1)

5.0 (m2)

7.5 (m3)

15 (m4)

m1 = 0.098

m2 = 0.240

m3 = 0.479

m4 = 3.732

Thunderbolt,

USB 3.1

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6

ESD8016

Without ESD8016

With ESD8016

Figure 14. USB 3.0 Eye Diagram with and without ESD8016. 5 Gb/s

With ESD8016

Without ESD8016

Figure 15. Thunderbolt and USB 3.1 Eye Diagram with and without ESD8016. 10 Gb/s

See application note AND9075/D for further description of eye diagram testing methodology.

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7

ESD8016

PCB Layout Guidelines

more information on latchup considerations, see

below description on Page 11.

• Make sure to use differential design methodology and

impedance matching of all high speed signal traces.

♦ Use curved traces when possible to avoid unwanted

reflections.

Steps must be taken for proper placement and signal trace

routing of the ESD protection device in order to ensure the

maximum ESD survivability and signal integrity for the

application. Such steps are listed below.

• Place the ESD protection device as close as possible to

the I/O connector to reduce the ESD path to ground and

improve the protection performance.

♦ Keep the trace lengths equal between the positive

and negative lines of the differential data lanes to

avoid common mode noise generation and

impedance mismatch.

♦ Place grounds between high speed pairs and keep as

much distance between pairs as possible to reduce

crosstalk.

♦ In USB 3.0/3.1 applications, the ESD protection

device should be placed between the AC coupling

capacitors and the I/O connector on the TX

differential lanes. In this configuration, no DC

current can flow through the ESD protection device

preventing any potential latch-up condition. For

USB 3.0/3.1 Type A

Connector

StdA_SSTX+

Vbus

StdA_SSTX−

D−

ESD8016

GND_DRAIN

D+

StdA_SSRX+

GND

StdA_SSRX−

Figure 16. USB 3.0/3.1 Type−A Layout Diagram

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8

ESD8016

Type−C Hybrid Top Mount Connector

Top Layer

GND

TX1+

TX1−

Vbus

CC1

(Config. detect: Vconn or PD comm.)

D+

D−

SBU1

Sideband use: AUX signal

Vbus

RX2−

RX2+

GND

Type−C Hybrid Top Mount Connector

Bottom Layer

GND

ESD9X

RX1+

RX2+

SBU2

Vbus

D−

D+

Vbus

CC2

TX2−

TX2+

GND

ESD9X

Black = Top layer

Red = Bottom layer

Figure 17. USB 3.1 Type−C Layout Diagram

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9

ESD8016

Thunderbolt Connector

Top Layer

GND

ML0+

ML0−

GND

ML1+

ML1−

GND

ML2+

ML2−

GND

ESD8016

Thunderbolt Connector

Bottom Layer

ESD9X

Hot Plug Detect

CONFIG1

ESD8016

CONFIG2

GND

ML3+

ML3−

AUX+

AUX−

PWR

Black = Top layer

Red = Bottom layer

ESD9X

Figure 18. Thunderbolt Layout Diagram

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10

ESD8016

Latch-Up Considerations

therefore latch-up free. Please note that for USB 3.0/3.1

applications, ESD8016 latch-up free considerations are

explained in more detail in the above PCB layout guidelines.

In the non-latch up free load line case, the IV characteristic

of the snapback protection device intersects the load-line in

ON Semiconductor’s 8000 series of ESD protection

devices utilize a snap-back, SCR type structure. By using

this technology, the potential for a latch-up condition was

taken into account by performing load line analysis of

common high speed serial interfaces. Example load lines for

latch-up free applications and applications with the potential

for latch-up are shown below with a generic IV

characteristic of a snapback, SCR type structured device

overlaid on each. In the latch-up free load line case, the IV

characteristic of the snapback protection device intersects

two points (V

, I ) and (V

, I

). Therefore in this

OPA OPA

OPB OPB

case, the potential for latch-up exists if the system settles at

(V , I ) after a transient. Because of this, ESD8016

OPB OPB

should not be used for HDMI applications – ESD8114 or

ESD8040 have been designed to be acceptable for HDMI

applications without latch-up. Please refer to Application

Note AND9116/D for a more in-depth explanation of

latch-up considerations using ESD8000 series devices.

the load-line in one unique point (V , I ). This is the only

stable operating point of the circuit and the system is

OP OP

I

I_SSMAX

I_OPB

I_SSMAX

I_OP

I_OPA

V

V_OPV_DD

V_OPB

V_OPAV_DD

ESD8016 Latch−up free:

USB 2.0 LS/FS, USB 2.0 HS, USB 3.0 SS,

DisplayPort

ESD8016 Potential Latch−up:

HDMI 2.0/1.4/1.3a TMDS

Figure 19. Example Load Lines for Latch-up Free Applications and Applications with the Potential for Latch-up

Table 1. SUMMARY OF SCR REQUIREMENTS FOR LATCH-UP FREE APPLICATIONS

VBR (min)

IH (min)

(mA)

VH (min)

ON Semiconductor ESD8000 Series

Recommended PN

(V)

Application

HDMI 2.0/1.4/1.3a TMDS

USB 2.0 LS/FS

USB 2.0 HS

3.465

3.301

0.482

2.800

3.600

54.78

1.76

N/A

1.0

ESD8114, ESD8040

ESD8014

USB 3.0/3.1 SS

DisplayPort

N/A

ESD8014, ESD8016, ESD8018

ESD8014, ESD8016

25.00

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11

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

UDFN8 2.0x1.2, 0.4P

CASE 517CX

ISSUE O

SCALE 4:1

DATE 31 JUL 2014

NOTES:

A

B

D

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

L

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED TERMINAL

AND IS MEASURED BETWEEN 0.15 AND

0.20 mm FROM TERMINAL.

PIN ONE

REFERENCE

L1

E

DETAIL A

2X

0.10

C

ALTERNATE TERMINAL

CONSTRUCTIONS

MILLIMETERS

DIM MIN

0.45

A1 0.00

MAX

0.55

0.05

A

2X

0.10 C

TOP VIEW

SIDE VIEW

A3

b

D

E

e

0.13 REF

0.15

0.25

A

2.00 BSC

1.20 BSC

0.40 BSC

(A3)

0.05

C

L

L1

L2 0.40

0.15

−−−

0.35

0.10

0.60

8X

A1

NOTE 4

SEATING

PLANE

C

GENERIC

MARKING DIAGRAM*

e

DETAIL A

2X L2

XXMG

e

1

G

6X L

XX

M

G

= Specific Device Code

= Date Code

= Pb−Free Package

8

8X b

e

0.10

0.05

C

A B

(Note: Microdot may be in either location)

e/2

BOTTOM VIEW

NOTE 3

*This information is generic. Please refer

to device data sheet for actual part

marking. Pb−Free indicator, “G”, may

or not be present.

RECOMMENDED

SOLDERING FOOTPRINT*

0.40

PITCH

8X

0.25

6X

0.40

PACKAGE

OUTLINE

1.40

1

2X

0.65

0.40

PITCH

0.40

PITCH

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON88710F

UDFN8 2.0X1.2, 0.4P

PAGE 1 OF 1

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

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


型号：	ESD8016MUTAG
厂家：	ONSEMI
描述：	低电容 ESD 保护二极管阵列，Thunderbolt 二极管
文件：	总13页 (文件大小：721K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ESD8016MUTAG [ONSEMI]

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