ESD8708MUTAG [ONSEMI]
3.3 V, 8 Channel Unidirectional ESD Protection Array;
| 型号： | ESD8708MUTAG |
| 厂家： | 
ONSEMI |
| 描述： | 3.3 V, 8 Channel Unidirectional ESD Protection Array |
| 文件： | 总10页 (文件大小：382K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ESD8708
ESD Protection Diode
Low Capacitance Array for High Speed
Data Lines
The ESD8708 is designed specifically to protect four high speed
differential pairs. Ultra−low capacitance and low ESD clamping
voltage make this device an ideal solution for protecting voltage
sensitive high speed data lines. The flow−through style package
allows for easy PCB layout and matched trace lengths necessary to
maintain consistent impedance for the high speed lines.
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MARKING
DIAGRAM
14
1
8708M
UDFN14
CASE 517CN
G
Features
• Integrated 4 Pairs (8 Lines) High Speed Data
• Single Connect, Flow through Routing
• Low Capacitance (0.5 pF Max, I/O to GND)
8708
M
= Specific Device Code
= Date Code
= Pb−Free Package
G
• Protection for the Following IEC Standards:
IEC 61000−4−2 Level 4 (ESD) 30 kV (Contact)
IEC 61000−4−5 (Lightning) 6.5 A (8/20 ms)
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
ORDERING INFORMATION
Compliant
Device
ESD8708MUTAG
Package
Shipping
Typical Applications
• Gigabit Ethernet
• V−by−One HS
• LVDS
UDFN14
(Pb−Free)
3000 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
• Display Port
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
Rating
Symbol
Value
−55 to +125
−55 to +150
260
Unit
°C
Operating Junction Temperature Range
Storage Temperature Range
T
J
T
stg
°C
Lead Solder Temperature −
Maximum (10 Seconds)
T
L
°C
IEC 61000−4−2 Contact (ESD)
IEC 61000−4−2 Air (ESD)
ESD
ESD
30
30
kV
kV
Maximum Peak Pulse Current
I
PP
6.5
A
8/20 ms @ T = 25°C (I/O−GND)
A
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
See Application Note AND8308/D for further description of
survivability specs.
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
June, 2019 − Rev. 0
ESD8708/D
ESD8708
I/O
Pin 1
I/O
Pin 2
I/O
Pin 4
I/O
Pin 5
I/O
Pin 7
I/O
Pin 8
I/O
I/O
Pin 10 Pin 11
Center Pins, Pin 3, 6, 9, 12, 13, 14
Note: Common GND − Only Minimum of 1 GND connection required
=
Figure 1. Pin Schematic
I/O
I/O
1
2
3
4
5
6
7
GND
I/O
14
13
12
GND
GND
GND
I/O
GND
I/O
I/O
8
9
GND
I/O
10
11
I/O
Figure 2. Pin Configuration
Note: Only minimum of one pin needs to be connected to
ground for functionality of all pins.
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2
ESD8708
I
ELECTRICAL CHARACTERISTICS
A
I
(T = 25°C unless otherwise noted)
PP
Symbol
Parameter
R
DYN
V
RWM
Working Peak Voltage
I
R
Maximum Reverse Leakage Current @ V
RWM
V
Breakdown Voltage @ I
Test Current
BR
T
V
BR
V
V
V
V
RWM HOLD
C
I
T
I
V
R
T
C
I
I
V
HOLD
HOLD
Holding Reverse Voltage
Holding Reverse Current
Dynamic Resistance
HOLD
I
R
DYN
R
DYN
I
PP
Maximum Peak Pulse Current
V
C
Clamping Voltage @ I
−I
PP
DYN
PP
V
= V
+ (I * R
)
C
HOLD
PP
V
C
= V
+ (I * R
)
HOLD
PP
DYN
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)
A
Parameter
Symbol
Conditions
Min
Typ
Max
3.3
Unit
Reverse Working Voltage
Breakdown Voltage
V
RWM
I/O Pin to GND
= 1 mA, I/O Pin to GND
V
V
V
BR
I
T
4.0
5.0
6.0
Holding Reverse Voltage
Holding Reverse Current
Reverse Peak Current
Clamping Voltage (Note 1)
Clamping Voltage
V
I/O Pin to GND
I/O Pin to GND
1.19
20
V
HOLD
HOLD
I
mA
A
I
PP
IEC61000−4−5 (8/20 ms)
6.5
7.5
V
C
V
C
V
C
V
C
V
C
IEC61000−4−2, 8 KV Contact
See Figures 3 and 4
V
I
PP
I
PP
I
PP
= 1.5 A, Any I/O to GND (8/20 ms pulse)
2.6
3.9
4.9
3.2
5.2
6.8
V
Clamping Voltage
= 5 A, Any I/O to GND (8/20 ms pulse)
= 6.5 A, Any I/O to GND (8/20 ms pulse)
V
Clamping Voltage
V
Clamping Voltage
TLP (Note 2)
See Figures 7 through 10
V
4.5
−3.8
I
PP
I
PP
= 8 A
= −8 A
IEC 61000−4−2 Level 2 equivalent
( 4 kV Contact, 4 kV Air)
I
PP
I
PP
= 16 A
= −16 A
6.5
−6.3
IEC 61000−4−2 Level 4 equivalent
( 8 kV Contact, 15 kV Air)
Dynamic Resistance
Junction Capacitance
R
I/O Pin to GND
GND to I/O Pin
0.25
0.31
W
DYN
C
V
R
V
R
V
R
V
R
= 0 V, f = 1 MHz between I/O Pins and GND
= 0 V, f = 2.5 GHz between I/O Pins and GND
= 0 V, f = 5.0 GHz between I/O Pins and GND
= 0 V, f = 1 MHz, between I/O Pins
0.34
0.30
0.31
0.5
pF
J
0.18
0.25
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. For test procedure see Figures 5 and 6 and application note AND8307/D.
2. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z = 50 W, t = 100 ns, t = 1 ns, averaging window; t = 70 ns to t = 90 ns.
0
p
r
1
2
90
80
70
60
50
40
30
20
10
0
10
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−10
−20
−100
−20
0
20
40
60
TIME (ns)
80
100
120 140
0
20
40
60
80
100
120 140
TIME (ns)
Figure 3. IEC61000−4−2 +8 kV Contact ESD
Figure 4. IEC61000−4−2 −8 kV Contact
Clamping Voltage
Clamping Voltage
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3
ESD8708
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
I
peak
First Peak
Current
(A)
100%
90%
Test Volt-
age (kV)
Current at
30 ns (A)
Current at
60 ns (A)
Level
1
2
3
4
2
4
6
8
7.5
15
4
8
2
4
6
8
I @ 30 ns
22.5
30
12
16
I @ 60 ns
10%
t
P
= 0.7 ns to 1 ns
Figure 5. IEC61000−4−2 Spec
Oscilloscope
ESD Gun
TVS
50 W
Cable
50 W
Figure 6. Diagram of ESD Clamping Voltage Test Setup
The following is taken from Application Note
AND8307/D − Characterization of ESD Clamping
Performance.
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
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4
ESD8708
20
18
16
14
12
10
8
−20
−18
−16
−14
−12
−10
−8
6
−6
4
−4
2
0
−2
0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
0
−1 −2 −3 −4 −5 −6 −7 −8 −9 −10 −11 −12 −13 −14
V , VOLTAGE (V)
C
V , VOLTAGE (V)
C
Figure 7. Positive TLP I−V Curve
Figure 8. Negative TLP I−V Curve
50 W Coax
Cable
Transmission Line Pulse (TLP) Measurement
L
Attenuator
S
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 9. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 10 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels. For more information
on TLP measurements and how to interpret them please
refer to AND9007/D.
÷
50 W Coax
Cable
I
M
V
M
10 MW
DUT
V
C
Oscilloscope
Figure 9. Simplified Schematic of a Typical TLP
System
Figure 10. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
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5
ESD8708
7
6
5
4
3
2
1
0
t = rise time to peak value [8 ms]
t = decay time to half value [20 ms]
f
r
Peak
Value
100
Half Value
50
0
0 t
r
t
f
0
1
2
3
4
5
6
7
8
9
10
I
PP
(A)
TIME (ms)
Figure 11. IEC61000−4−5 8/20 ms Pulse
Figure 12. Clamping Voltage vs. Peak Pulse Current
Waveform
(tp = 8/20 ms per Figure 11)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.0
−0.5
−1.0
−1.5
−2.0
−2.5
−3.0
1.E+07
1.E+08
1.E+09
1.E+10
1.E+07
1.E+08
1.E+09
1.E+10
Frequency (Hz)
Frequency (Hz)
Figure 14. Insertion Loss
Figure 13. Capacitance over Frequency
1
ESD8708
2
3
4
5
6
7
8
Figure 15. Gigabit Ethernet
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6
ESD8708
ESD8708
Rx0p
Rx0n
Rx1p
Rx1n
Rx2p
Rx2n
Rx3p
Rx3n
ESD8708
Rx4p
Rx4n
Rx5p
Rx5n
Rx6p
Rx6n
Rx7p
Rx7n
Figure 16. V−by−One HS Layout Diagram (for LCD Panel)
PCB Layout Guidelines
♦ Use curved traces when possible to avoid unwanted
reflections.
♦ Keep the trace lengths equal between the positive
and negative lines of the differential data lanes to
avoid common mode noise generation and
impedance mismatch.
♦ Place grounds between high speed pairs and keep as
much distance between pairs as possible to reduce
crosstalk.
Steps must be taken for proper placement and signal trace
routing of the ESD protection device in order to ensure the
maximum ESD survivability and signal integrity for the
application. Such steps are listed below.
• Place the ESD protection device as close as possible to
the I/O connector to reduce the ESD path to ground and
improve the protection performance.
• Make sure to use differential design methodology and
impedance matching of all high speed signal traces.
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7
ESD8708
Latch-Up Considerations
stable operating point of the circuit and the system is
therefore latch-up free. In the non-latch up free load line
case, the IV characteristic of the snapback protection device
ON Semiconductor’s 8000 series of ESD protection
devices utilize a snap-back, SCR type structure. By using
this technology, the potential for a latch-up condition was
taken into account by performing load line analyses of
common high speed serial interfaces. Example load lines for
latch-up free applications and applications with the potential
for latch-up are shown below with a generic IV
characteristic of a snapback, SCR type structured device
overlaid on each. In the latch-up free load line case, the IV
characteristic of the snapback protection device intersects
intersects the load-line in two points (V
, I
OPA OPA
) and
(V , I ). Therefore in this case, the potential for
OPB OPB
latch-up exists if the system settles at (V
, I
) after a
OPB OPB
transient. Because of this, ESD8708 should not be used for
HDMI applications – ESD8104 or ESD8040 have been
designed to be acceptable for HDMI applications without
latch-up. Please refer to Application Note AND9116/D for
a more in-depth explanation of latch-up considerations
using ESD8000 series devices.
the load-line in one unique point (V , I ). This is the only
OP OP
I
I
ISSMAX
IOPB
ISSMAX
IOP
IOPA
V
V
VOP VDD
VOPB
VOPA VDD
ESD8708 Latch−up free:
ESD8708 Potential Latch−up:
V−by−One HS, DisplayPort, LVDS
HDMI 1.4/1.3a TMDS
Figure 17. Example Load Lines for Latch-up Free Applications and Applications with the Potential for Latch-up
Table 1. SUMMARY OF SCR REQUIREMENTS FOR LATCH-UP FREE APPLICATIONS
VBR (min)
IH (min)
(mA)
VH (min)
ON Semiconductor ESD8000 Series
Recommended PN
(V)
(V)
Application
HDMI TMDS
DisplayPort
V−by−One HS
LVDS
3.465
3.600
1.980
1.829
54.78
25.00
21.70
9.20
1.0
1.0
1.0
1.0
ESD8104, ESD8040
ESD8004, ESD8006, ESD8708
ESD8708
ESD8708
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8
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
UDFN14, 5.5x1.5, 0.5P
CASE 517CN
14
ISSUE O
1
DATE 30 OCT 2012
SCALE 2:1
NOTES:
L
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
D
A B
PIN ONE
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.10 AND 0.20 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
REFERENCE
L1
DETAIL A
2X
0.10
C
OPTIONAL
CONSTRUCTION
E
2X
0.10
C
MILLIMETERS
TOP VIEW
DIM MIN
MAX
0.55
0.05
A
A1
A3
b
0.45
0.00
0.13 REF
EXPOSED Cu
MOLD CMPD
DETAIL B
(A3)
0.15
0.25
A
0.05
0.10
C
C
D
D2
E
DETAIL B
E2
e
L
0.50
0.50 BSC
0.20
0.00
0.70
OPTIONAL
NOTE 4
SEATING
PLANE
A1
C
CONSTRUCTION
SIDE VIEW
0.40
0.05
L1
DETAIL A
e
DETAIL C
GENERIC
MARKING DIAGRAM*
L
1
11
0.10
REF
XXXXM
E2
12
14
G
D2
DETAIL C
14X b
M
0.10
C
C
A B
XXXX = Specific Device Code
M
NOTE 3
0.05
M
= Date Code
BOTTOM VIEW
G
= Pb−Free Package
RECOMMENDED
SOLDERING FOOTPRINT*
*This information is generic. Please refer
to device data sheet for actual part
marking.
6X
0.43
3X
0.56
PACKAGE
OUTLINE
1.80
3X
0.62
14X
0.50
14X
0.26
0.50
PITCH
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON84523E
UDFN14, 5.5X1.5, 0.5P
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
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rights of others.
© Semiconductor Components Industries, LLC, 2019
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