FAM65CR51DZ2 [ONSEMI]
功率集成模块 (PIM) 升压转换器级，用于多相和半无桥 PFC;
| 型号： | FAM65CR51DZ2 |
| 厂家： | 
ONSEMI |
| 描述： | 功率集成模块 (PIM) 升压转换器级，用于多相和半无桥 PFC 升压转换器 功率因数校正 |
| 文件： | 总16页 (文件大小：740K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Boost Converter Stage in
APM16 Series for Multiphase
and Semi-Bridgeless PFC
FAM65CR51DZ1,
FAM65CR51DZ2
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Features
• Integrated SIP or DIP Boost Converter Stage Power Module for
On−board Charger (OBC) in EV or PHEV
• 5 kV/1 sec Electrically Isolated Substrate for Easy Assembly
• Creepage and Clearance per IEC60664−1, IEC 60950−1
• Compact Design for Low Total Module Resistance
• Module Serialization for Full Traceability
• Lead Free, RoHS and UL94V−0 Compliant
• Automotive Qualified per AEC Q101 and AQG324 Guidelines
APMCD−A16
12 LEAD
CASE MODGG
Applications
• PFC Stage of an On−board Charger in PHEV or EV
Benefits
• Enable Design of Small, Efficient and Reliable System for Reduced
Vehicle Fuel Consumption and CO Emission
2
• Simplified Assembly, Optimized Layout, High Level of Integration,
and Improved Thermal Performance
APMCD−B16
12 LEAD
CASE MODGK
MARKING DIAGRAM
XXXXXXXXXXX
ZZZ ATYWW
NNNNNNN
XXXX = Specific Device Code
ZZZ = Lot ID
AT
Y
= Assembly & Test Location
= Year
W
= Work Week
NNN = Serial Number
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
June, 2021 − Rev. 3
FAM65CR51DZ1/D
FAM65CR51DZ1, FAM65CR51DZ2
ORDERING INFORMATION
Pb−Free and
RoHS Compliant Temperature (T )
Operating
Packing
Method
Part Number
FAM65CR51DZ1
FAM65CR51DZ2
Package
Lead Forming
Y−Shape
DBC Material
A
APM16−CDA
APM16−CDB
Al O
Yes
Yes
−40°C ~ 125°C
−40°C ~ 125°C
Tube
Tube
2
3
3
L−Shape
Al O
2
Pin Configuration and Description
Figure 1. Pin Configuration
Table 1. PIN DESCRIPTION
Pin Number
Pin Name
AC1
Pin Description
1, 2
3
Phase 1 Leg of the PFC Bridge
Not Connected
NC
4
NC
Not Connected
5, 6
7, 8
9
B+
Positive Battery Terminal
Source Terminal of Q1
Gate Terminal of Q1
Gate Terminal of Q2
Source Terminal of Q2
Not Connected
Q1 Source
Q1 Gate
Q2 Gate
Q2 Source
NC
10
11, 12
13
14
NC
Not Connected
15, 16
AC2
Phase 2 Leg of the PFC Bridge
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2
FAM65CR51DZ1, FAM65CR51DZ2
INTERNAL EQUIVALENT CIRCUIT
Figure 2. Internal Block Diagram
Table 2. ABSOLUTE MAXIMUM RATINGS OF MOSFET (T = 25°C, Unless Otherwise Specified)
J
Symbol
Parameter
Max
650
Unit
V
V
V
(Q1~Q2)
(Q1~Q2)
Drain−to−Source Voltage
Gate−to−Source Voltage
DS
GS
20
V
I
D
(Q1~Q2)
Drain Current Continuous (T = 25°C, V = 10 V) (Note 1)
33
A
C
GS
Drain Current Continuous (T = 100°C, V = 10 V) (Note 1)
23
A
C
GS
E
AS
(Q1~Q2)
Single Pulse Avalanche Energy (Note 2)
623
mJ
W
°C
°C
°C
P
D
Power Dissipation (Note 1)
Maximum Junction Temperature
Maximum Case Temperature
Storage Temperature
160
T
J
−55 to +150
−40 to +125
−40 to +125
T
C
T
STG
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Maximum continuous current and power, without switching losses, to reach T = 150°C respectively at T = 25°C and T = 100°C; defined
J
C
C
by design based on MOSFET R
and R
and not subject to production test
q
DS(ON)
JC
2. Starting T = 25°C, I = 6.5 A, R = 25 W
J
AS
G
DBC Substrate
Compliance to RoHS Directives
0.63 mm Al O alumina with 0.3 mm copper on both sides.
DBC substrate is NOT nickel plated.
The power module is 100% lead free and RoHS compliant
2000/53/C directive.
2
3
Lead Frame
Solder
OFC copper alloy, 0.50 mm thick. Plated with 8 um to
25.4 um thick Matte Tin
Solder used is a lead free SnAgCu alloy.
Solder presents high risk to melt at temperature beyond
210°C. Base of the leads, at the interface with the package
body, should not be exposed to more than 200°C during
mounting on the PCB or during welding to prevent the
re−melting of the solder joints.
Flammability Information
All materials present in the power module meet UL
flammability rating class 94V−0.
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3
FAM65CR51DZ1, FAM65CR51DZ2
Table 3. ELECTRICAL SPECIFICATIONS OF MOSFET (T = 25°C, Unless Otherwise Specified)
J
Symbol
Parameter
Conditions
I = 1 mA, V = 0 V
D
Min
650
3.0
−
Typ
−
Max
−
Unit
V
BV
Drain−to−Source Breakdown Voltage
Gate−to−Source Threshold Voltage
Q1 Low Side MOSFET
DSS
GS
V
GS(th)
V
GS
= V , I = 3.3 mA
−
5.0
51
51
−
V
DS
D
R
R
R
R
Q1
V
GS
= 10 V, I = 20 A
44
44
79
79
30
−
mW
mW
mW
mW
S
DS(ON)
DS(ON)
DS(ON)
DS(ON)
D
Q2
Q1
Q2
Q2 Low Side MOSFET
−
Q1 Low Side MOSFET
V
GS
= 10 V, I = 20 A, T = 125°C (Note 3)
−
D
J
Q2 Low Side MOSFET
−
−
g
FS
Forward Transconductance
Gate−to−Source Leakage Current
Drain−to−Source Leakage Current
V
DS
= 20 V, I = 20 A (Note 3)
−
−
D
I
V
=
20 V, V = 0 V
−100
−
+100
10
nA
mA
GSS
GS
DS
DS
I
V
= 650 V, V = 0 V
−
DSS
GS
DYNAMIC CHARACTERISTICS (Note 3)
C
Input Capacitance
V
V
= 400 V
−
−
−
−
4864
109
16
−
−
−
−
pF
pF
pF
pF
iss
DS
= 0 V
GS
C
Output Capacitance
oss
f = 1 MHz
= 0 to 520 V
DS
C
Reverse Transfer Capacitance
Effective Output Capacitance
rss
C
V
652
oss(eff)
V
GS
= 0 V
R
Gate Resistance
f = 1 MHz
−
−
−
−
2
−
−
−
−
W
g
Q
Total Gate Charge
V
= 380 V
= 20 A
123
37.5
49
nC
nC
nC
g(tot)
DS
I
D
Q
Gate−to−Source Gate Charge
Gate−to−Drain “Miller” Charge
gs
gd
V
= 0 to 10 V
GS
Q
SWITCHING CHARACTERISTICS (Note 3)
t
Turn−on Time
V
= 400 V
= 20 A
−
−
−
−
−
−
87
47
−
−
−
−
−
−
ns
ns
ns
ns
ns
ns
on
DS
I
D
t
Turn−on Delay Time
Turn−on Rise Time
Turn−off Time
d(on)
V
= 10 V
GS
t
r
43
R
= 4.7 Ohm
G
t
148
118
29
off
d(off)
t
Turn−off Delay Time
Turn−off Fall Time
t
f
BODY DIODE CHARACTERISTICS
V
Source−to−Drain Diode Voltage
Reverse Recovery Time
I
= 20 A, V = 0 V
−
−
−
0.95
133
669
−
−
−
V
SD
SD
GS
T
V
= 520 V, I = 20 A,
ns
nC
rr
DS
t
D
d /d = 100 A/ms (Note 3)
I
Q
Reverse Recovery Charge
rr
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Defined by design, not subject to production test
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4
FAM65CR51DZ1, FAM65CR51DZ2
Table 4. ABSOLUTE MAXIMUM RATINGS OF THE BOOST DIODE (T = 25°C, Unless Otherwise Specified)
J
Symbol
Parameter
Peak Repetitive Reverse Voltage (Note 4)
Rating
Unit
V
V
600
RRM
RWM
V
Working Peak Reverse Voltage (Note 4)
DC Blocking Voltage
600
V
V
R
600
15
V
I
Average Rectified Forward Current T = 25°C
A
F(AV)
C
I
Non−Repetitive Peak Surge Current (Half Wave 1 Phase 60 Hz)
Maximum Junction Temperature
45
A
FSM
T
−55 to +175
−40 to +125
−40 to +125
4
°C
°C
°C
mJ
J
C
T
Maximum Case Temperature
T
Storage Temperature
STG
E
Avalanche Energy (2.85 A, 1 mH)
AVL
4. V
and I
value referenced to TO220−2L Auto Qualified Package Device ISL9R1560P_F085
RRM
F(AV)
Table 5. ELECTRICAL SPECIFICATIONS OF THE BOOST DIODE (T = 25°C, Unless Otherwise Specified)
J
Symbol
Parameter
Test Conditions
Min
−
Typ
−
Max
100
1
Unit
mA
mA
V
I
R
Instantaneous Reverse Current
V
= 600 V
T
C
= 25°C
= 125°C
= 25°C
= 125°C
= 25°C
= 25°C
= 25°C
R
T
C
−
−
V
FM
Instantaneous Forward Voltage (Note 5)
I =15 A
T
C
−
1.65
1.24
29
2.2
1.7
−
F
T
C
−
V
t
rr
Reverse Recovery Time
I = 15 A
d /dt = 200 A/ms
T
C
T
C
T
C
−
ns
ns
n
F
IF
t
a
Time to reach peak reverse current
−
16
−
V =390 V
(Note 3)
R
t
b
Time from peak I
to projected zero cross-
−
13
−
RRM
ing of I
based on a straight line from peak
RRM
I
through 25% of I
RRM
RRM
Q
Reverse Recovered Charge
T
C
= 25°C
−
43
−
nC
rr
5. Test pulse width = 300 ms, Duty Cycle = 2%
Table 6. THERMAL RESISTANCE
Parameters
Min
−
Typ
Max
Unit
°C/W
°C/W
°C/W
°C/W
R
R
(per MOSFET chip)
(per MOSFET chip)
(per DIODE chip)
Q1,Q2 Thermal Resistance Junction−to−Case (Note 6)
Q1,Q2 Thermal Resistance Junction−to−Sink (Note 7)
D1,D2 Thermal Resistance Junction−to−Case (Note 6)
D1,D2 Thermal Resistance Junction−to−Sink (Note 7)
0.66
1.20
1.98
2.97
0.92
−
θ
JC
JS
−
θ
R
R
−
2.72
−
θ
JC
(per DIODE chip)
−
θ
JS
6. Test method compliant with MIL STD 883−1012.1, from case temperature under the chip to case temperature measured below the package
at the chip center, Cosmetic oxidation and discoloration on the DBC surface allowed
7. Defined by thermal simulation assuming the module is mounted on a 5 mm Al−360 die casting material with 30 um of 1.8 W/mK thermal
interface material
Table 7. ISOLATION (Isolation resistance at tested voltage between the base plate and to control pins or power terminals.)
Test
Test Conditions
Isolation Resistance
Unit
Leakage @ Isolation Voltage (Hi−Pot)
V
AC
= 5 kV, 60 Hz
100M <
W
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5
FAM65CR51DZ1, FAM65CR51DZ2
PARAMETER DEFINITIONS
Reference to Table 3: Parameter of MOSFET Electrical
Specifications
BV
DSS
Q1, Q2 MOSFET Drain−to−Source Breakdown Voltage
The maximum drain−to−source voltage the MOSFET can endure without the avalanche breakdown of the body− drain
P−N junction in off state.
The measurement conditions are to be found in Table 3.
The typ. Temperature behavior is described in Figure 14
V
GS(th)
Q1, Q2 MOSFET Gate to Source Threshold Voltage
The gate−to−source voltage measurement is triggered by a threshold ID current given in conditions at Table 4.
The typ. Temperature behavior can be found in Figure 11
R
DS(ON)
Q1, Q2 MOSFET On Resistance
RDS(on) is the total resistance between the source and the drain during the on state.
The measurement conditions are to be found in Table 3.
The typ behavior can be found in Figure 12 and Figure 13 as well as Figure 18
g
FS
Q1, Q2 MOSFET Forward Transconductance
Transconductance is the gain in the MOSFET, expressed in the Equation below.
It describes the change in drain current by the change in the gate−source bias voltage: g = [ DI / DV ]
fs
DS
GS VDS
I
GSS
Q1, Q2 MOSFET Gate−to−Source Leakage Current
The current flowing from Gate to Source at the maximum allowed VGS
The measurement conditions are described in the Table 3.
I
DSS
Q1, Q2 MOSFET Drain−to−Source Leakage Current
Drain – Source current is measured in off state while providing the maximum allowed drain−to-source voltage and the
gate is shorted to the source.
IDSS has a positive temperature coefficient.
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6
FAM65CR51DZ1, FAM65CR51DZ2
Figure 3. Timing Measurement Variable Definition
Table 8. PARAMETER OF SWITCHING CHARACTERISTICS
Turn−On Delay (t
)
d(on)
This is the time needed to charge the input capacitance, Ciss, before the load current ID starts flowing.
The measurement conditions are described in the Table 3.
For signal definition please check Figure 3 above.
Rise Time (t )
The rise time is the time to discharge output capacitance, Coss.
After that time the MOSFET conducts the given load current ID.
The measurement conditions are described in the Table 3.
For signal definition please check Figure 3 above.
r
Turn−On Time (t
)
Is the sum of turn−on−delay and rise time
on
Turn−Off Delay (t
)
td(off) is the time to discharge Ciss after the MOSFET is turned off.
During this time the load current ID is still flowing
d(off)
The measurement conditions are described in the Table 3.
For signal definition please check Figure 3 above.
Fall Time (t )
f
The fall time, tf, is the time to charge the output capacitance, Coss.
During this time the load current drops down and the voltage VDS rises accordingly.
The measurement conditions are described in the Table 3.
For signal definition please check Figure 3 above.
Turn−Off Time (t
)
Is the sum of turn−off−delay and fall time
off
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7
FAM65CR51DZ1, FAM65CR51DZ2
Figure 4. Dynamic Parameters of Silicon Diode (not in scale)
Reference to Table 5: Parameter of Diode Electrical
Specifications
Instantaneous Reverse Current
Current flowing in reverse after the reverse recovery time t ..
rr
(I )
R
I is shown in Figure 4 above
R
The behaviour over voltage can be seen in Figure 23.
Instantaneous Forward Voltage
Voltage drop over the diode in a dynamic condition given in Note 5.
The voltage is measured after the given test pulse width.
V
FM
To avoid self heating effects a small duty cycle is used
The behaviour over voltage can be seen in Figure 22.
During this transition time,from conduction to blocking, the current is flowing in reverse direction
and diode generates switching losses. The time is characterized on the scope by using the ta and
tb approximation method
Reverse Recovery Time
t
rr
ta + tb = trr parameter result in Table 3
The parameter is dependent on temperature and initial dI/dt
Figure 25 shows the dependency on dI/dt
Time to reach peak reverse current
ta is the transition time from the moment the current starts to flow in reverse direction until the
diode voltage drops (also the reverse current peak)
t
a
Time from peak IRRM to zero crossing
b
tb is defined by using a linear approximation from the peak IRM to a projected zero crossing of IR
by crossing IR at 25% of IRRM
t
trr
Reverse Recovered Charge
rr
The reverse recovery charge is defined as Q = ∫ I (t) dt
rr
r
Q
This parameter is highly depend on temperature and dI/dt
See Figure 27.
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FAM65CR51DZ1, FAM65CR51DZ2
TYPICAL CHARACTERISTICS − MOSFETs
1.2
1.0
0.8
0.6
0.4
40
35
30
25
20
15
V
GS
= 10 V
10
R
= 0.92°C/W
q
JC
R
= 0.92°C/W
0.2
0
q
JC
5
0
0
3
0
25
50
75
100
125
150
25
50
75
100
125
150
175
T , CASE TEMPERATURE (°C)
T , CASE TEMPERATURE (°C)
C
C
Figure 5. Normalized Power Dissipation vs.
Case
Figure 6. Maximum Continuous ID vs. Case
Temperature
V = 0 V
GS
60
50
40
30
20
V
= 20 V
DS
100
10
1
T = 25°C
J
T = 150°C
T = 25°C
J
J
0.1
T = 150°C
J
10
0
T = −55°C
J
0.01
4
5
6
7
8
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
V
, GATE−TO−SOURCE VOLTAGE (V)
V
, BODY DIODE FORWARD VOLTAGE (V)
GS
SD
Figure 7. Transfer Characteristics
Figure 8. Forward Diode
100
90
80
70
60
50
40
30
20
80
70
60
50
40
30
20
V
= 15 V
10 V
GS
8.0 V
V
= 15 V
GS
10 V
7.0 V
6.0 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
5.5 V
5.0 V
10
0
10
0
1
2
3
4
5
6
7
8
9
10
0
10 20 30
40 50 60 70
80 90 100
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 9. On Region Characteristics (255C)
Figure 10. On Region Characteristics (1505C)
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FAM65CR51DZ1, FAM65CR51DZ2
TYPICAL CHARACTERISTICS − MOSFETs
200
150
100
2.5
I
V
= 20 A
I
D
= 20 A
D
= 10 V
GS
2.0
1.5
1.0
T = 150°C
J
T = 25°C
J
50
0
0.5
0
5.5
6.5
7.5
8.5
9.5
−75 −50 −25
0
25
50 75 100 125 150 175
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
T , JUNCTION TEMPERATURE (°C)
J
Figure 11. On−Resistance vs. Gate−to−Source
Figure 12. RDS(norm) vs. Junction Temperature
Voltage
1.2
1.0
1.2
1.1
1.0
I
D
= 3.3 mA
I = 10 A
D
0.8
0.6
0.9
0.8
−75 −50 −25
0
25 50 75 100 125 150 175
−75 −50 −25
0
25 50 75 100 125 150 175
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 13. Normalized Gate Threshold Voltage
vs. Temperature
Figure 14. Normalized Breakdown Voltage vs.
Temperature
30
25
20
15
10
100K
10K
1K
C
ISS
C
C
OSS
100
RSS
V
= 0 V
GS
10
1
5
0
f = 1 MHz
0
100
200
300
400
500
600
700
0.1
1
10
100
1000
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 15. Eoss vs. Drain−to−Source Voltage
Figure 16. Capacitance Variation
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FAM65CR51DZ1, FAM65CR51DZ2
TYPICAL CHARACTERISTICS − MOSFETs
10
8
0.060
T
C
= 25°C
V
DD
= 130 V
0.055
0.050
V
DD
= 400 V
V
GS
= 10 V
6
4
V
GS
= 20 V
0.045
0.040
2
0
0
40
80
120
160
0
20
40
60
80
Q , GATE CHARGE (nC)
G
I , DRAIN CURRENT (A)
D
Figure 17. Gate Charge Characteristics
Figure 18. ON−Resistance Variation with Drain
Current and Gage Voltage
10,000
1000
For temperatures above 25°C
V
= 10 V
GS
derate peak current as follows:
100
10
150 * T
C
Ǹ
I + I
25
125
100 ms
T
C
= 25°C
T
= 25°C
1 ms
C
Limited I
206 A
DM
Single Pulse
R
10 ms
100
10
= 0.92°C/W
q
JC
1
NOTES:
= 0.92°C/W
R
Limit
DS(on)
R
q
JC
Thermal Limit
Package Limit
100 ms
100
Duty Cycle, D = t /t
1
2
1 s
Single Pulse
Peak T = P
x Z (t) + T
q
JC C
J
DM
0.1
1
10
1000
0.000001 0.00001 0.0001
0.001
0.01
0.1
1
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
t, PULSE WIDTH (sec)
Figure 19. Safe Operating Area
Figure 20. Peak Current Capability
10
1
Duty Cycle = 0.5
0.2
0.1
0.05
0.02
0.1
0.01 0.01
Single Pulse
0.00001
0.001
0.0001
0.001
0.01
0.1
1
10
100
t, RECTANGULAR PULSE DURATION (sec)
Figure 21. Transient Thermal Impedance
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FAM65CR51DZ1, FAM65CR51DZ2
TYPICAL CHARACTERISTICS − DIODES
100
1000
100
T = 100°C
A
125°C
10
1
T = 125°C
A
T = 25°C
A
10
0.1
25°C
0.01
0.001
1
0.0001
0.2
0.7
1.2
1.7
2.2
2.7
3.2
100
500
100
200
300
400
500
600
500
500
V , FORWARD VOLTAGE (V)
V , REVERSE VOLTAGE (V)
F
R
Figure 22. Typical Forward Voltage Drop vs.
Forward Current
Figure 23. Typical Reverse Current vs.
Reverse Voltage
500
400
300
200
150
100
125°C
25°C
50
0
100
0
0.1
1
10
100
200
300
400
V , REVERSE VOLTAGE (V)
di/dt (A/ms)
R
Figure 24. Capacitance
Figure 25. Reverse Recovery Time vs. di/dt
15
10
500
400
300
200
125°C
125°C
25°C
5
0
25°C
100
0
100
200
300
400
100
200
300
400
di/dt (A/ms)
di/dt (A/ms)
Figure 26. Reverse Recovery Current vs. di/dt
Figure 27. Reverse Recovery Charge vs. di/dt
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FAM65CR51DZ1, FAM65CR51DZ2
TYPICAL CHARACTERISTICS − DIODES
1
Duty Cycle = 0.5
0.2
0.1
0.05
0.1
0.02
0.01
0.01
Single Pulse
0.001
0.00001
0.001
0.1
10
1000
t, RECTANGULAR PULSE DURATION (sec)
Figure 28. Transient Thermal Impedance
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
APMCD−A16 / 12LD, AUTOMOTIVE MODULE
CASE MODGG
ISSUE C
DATE 03 NOV 2021
GENERIC
MARKING DIAGRAM*
XXXX = Specific Device Code
ZZZ = Lot ID
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
AT
Y
= Assembly & Test Location
= Year
XXXXXXXXXXXXXXXX
ZZZ ATYWW
NNNNNNN
WW = Work Week
NNN = Serial Number
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON94738G
APMCD−A16 / 12LD, AUTOMOTIVE MODULE
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2018
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
APMCD−B16 / 12LD, AUTOMOTIVE MODULE
CASE MODGK
ISSUE D
DATE 04 NOV 2021
GENERIC
MARKING DIAGRAM*
XXXX = Specific Device Code
ZZZ = Lot ID
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
AT
Y
W
= Assembly & Test Location
= Year
= Work Week
XXXXXXXXXXXXXXXX
ZZZ ATYWW
NNNNNNN
NNN = Serial Number
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON97134G
APMCD−B16 / 12LD, AUTOMOTIVE MODULE
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2018
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