FAN105BM6X [ONSEMI]

PSR Quasi-Resonant Valley Switch Controller;


型号：	FAN105BM6X
厂家：	ONSEMI
描述：	PSR Quasi-Resonant Valley Switch Controller
文件：	总19页 (文件大小：659K)
中文：	中文翻译
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FAN105BM6X

Offline Primary-Side-Regulation

(PSR) Quasi-Resonant Valley

Switch Controller

FAN105B is offline Primary-Side-Regulation (PSR) PWM controller with

Quasi-Resonant (QR) mode controller to achieved constant-voltage (CV)

and constant-current (CC) control for Travel Adaptor (TA) requirement,

and provide cost-effective, simplified circuit for energy-efficient power

supplies.

www.onsemi.com

MARKING DIAGRAM

FAN105B integrates proprietary operation of energy saving feature at no

load, mWSaver Technology that combines our most energy efficient

process and circuit technologies for power adapter design.

FAN105B can be used in Travel Adapter design by stand-alone or co-work

with secondary-side SR controller FAN6292B. When paired FAN105B with

FAN6292B, both SR and USB Type-C connector are compatible to

achieve higher power and advanced control applications.

PXXEX

- - -

Features

· · · = Year Code



mWSaver® Technology Provides Ultra-Low Standby

Power Consumption for Energy Star’s 5-Star Level

(<30 mW with HV FET)

PXX = 5A0 : FAN105BM6X

= 5B0 : FAN105BM6X

E X = Die Run Code



Constant-Current (CC) and Constant-Voltage(CV) with

Primary-Side Regulation Eliminates Secondary-Side

Feedback Component

- - - = Week Code



Valley Switch Operation for Highest Average Efficiency

PIN CONNECTIONS

Programmable Cable Drop Compensation(CDC) with One

External Resistor



Integrated Dynamic Response Enhanceement(DRE)

Function

AUX



Low EMI Emissions and Common Mode Noise

Cycle-by-Cycle Current Limiting

GND

GATE

Output Short-Circuit Protection

VDD

Scondary side Rectifier Short Detection via Current Sense

Protection(CSP)



Integrated Constant Current Compensation for Precise CC

Regulation

ORDERING INFORMATION



Output Over-Voltage Protection (VSOVP)

Output under-Voltage Protection (VSUVP)

VDD Over-Voltage Protection (VDD OVP)

Internal Thermal-Shutdown Protection (OTP)

Programmable Brown-In and Brown-Out Protection

Operating

Temperature

Range

Packing

Method

Part Number

Package

6-Lead,

SOT23

FAN105BM6X -40 ºC ~125ºC

Tap & Reel

For information on tape and reel specifications,

including part orientation and tape sizes,

please refer to our Tape and Reel Packaging

Typical Applications

Specifications

Brochure,

BRD8011/D.



Travel Adapter for Smart Phones, Feature Phones, and Tablet

PCs



AC-DC Adapters for Portable Devices that Require CV/CC

Control

Publication Order Number:

May 2017- Rev. 1.0

FAN105BM6X

Load

Switch

V_BUS

Bridge

L_π

N_P

N_S

R_SN1

R_Start

C_SN2

C_o1

USB Type-C

C_o2

C_DL1

C_DL2

V_ac

GND

RX1+

RX1-

V_BUS

SBU2

D-

SR MOSFET

TX1+

TX1-

V_BUS

D_SN1

R_LPC1

V_BUS

CC1

V_BUS

Fuse

Depletion

MOSFET

CC1

R_LPC2

D_VDD

MOSFET

D+

LPC GATE GND VIN

D-

D+

Opto-

coupler

Rot

R_FB

C_VDD

CC2

V_BUS

TX2-

TX2+

GND

SBU1

V_BUS

FAN6292B

CC2

V_BUS

D_R

R_Gate

BLD

/AUX

CC2 CC1

LGATE

V_BUS

R_CDC

FAN105B

RX2-

RX2+

GND

N_A

Opto-

AUX

VDD

Gate

coupler

R_VS1

CC1

CC2

R_cs

GND

C_VS

R_VS2

Figure 1. FAN105B Typical Application Schematic

VDD

AUX

V_CS-LIM

OCP

Cable Drop

T_DIS

LEB

Compensation

Internal

Regulator

VDD ON/OFF

DRE Detection

OCP

OTP

AR Mode

Protection

Brown Out/In

VS OVP/UVP

V_DDOVP

Peak Current

Detection

Current Monitor

I_VS

VDD

V_{CS_CTRL}

V_{CS_PK}

Diode

Discharge

Detection

T_DIS

DYN

I_OEstimator

PWM

Block

GATE

COMI

COMV

OSC

2.5V

EAV

7.5V

Compensator

VS Sample/Hold

No-Load

Control

Maximum

On Time

GND

Valley

Detection

Figure 2.FAN105B Function Block Diagram

Publication Order Number:

May 2017- Rev. 1.0

FAN105BM6X

PIN FUNCTION DESCRIPTION

Pin # Name Description

Current Sense. This pin connects to a current-sense resistor to detect the MOSFET

current for Peak-Current-Mode control for output regulation. The current-sense

information is also used to estimate the output current for CC regulation.

Ground

GND

PWM Signal Output. This pin has an internal totem-pole output driver to drive the power

MOSFET. The gate driving voltage is internally clamped at 7.5 V.

GATE

Power Supply. IC operating current and MOSFET driving current are supplied through

this pin. This pin is typically connected to an external V_DDcapacitor.

VDD

Voltage Sense. This pin detects the output voltage information and diode current

discharge time based on the voltage of auxiliary winding. It also senses sink current

through the auxiliary winding to detect input voltage information.

Auxiliary Function. This pin generates one voltage level proportional to output current

AUX to compensate output voltage drop due to cable resistance. The pin is also used for

startup with external HV FET.

Publication Order Number:

May 2017- Rev. 1.0

FAN105BM6X

ABSOLUTE MAXIMUM RATINGS (Note 1,2,3,4)

Parameter

Symbol Min. Max. Unit

DC Supply Voltage

V_VDD

V_AUX

V_VS

V_CS

P_D

-0.3

AUX Pin Input Voltage

VS Pin Input Voltage

6.0

CS Pin Input Voltage

6.0

0.391

+150

+260

C

Power Dissipation (T_A=25C)

Operating Junction Temperature

Storage Temperature Range

Lead Temperature (Soldering, 10 Seconds)

T_J

-40

-60

T_STG

T_L

Human Body Model,

ANSI/ESDA/JEDEC, JESD22_A114

>1.5

Electrostatic Discharge Capability

ESD

Charged Device Model,

JEDEC:JESD22_C101

>0.5

1. Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable

above stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the

recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.

2. All voltage values, except differential voltages, are given with respect to the GND pin.

3. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

4. Meets JEDEC standards JS-001-2012 and JESD 22-C101.

THERMAL CHARACTERISTICS (Note 5)

Parameter

Symbol

θ_JA

Min.

Max.

242

Unit

°C/W

Junction-to-Ambient Thermal Impedance

Junction-to-Top Thermal Impedance

θ_JT

5. T_A=25°C unless otherwise specified.

RECOMMENDED OPERATING RANGES (Note 6)

Parameter

Symbol

V_CS

Min.

Max.

0.8

8.0

Unit

CS Pin Input Voltage

Gate Pin Input Voltage

VDD Pin Input Voltage

VS Pin Input Voltage

AUX Pin Input Voltage

V_GATE

V_DD

7.0

1.6

5.0

V_VS

3.2

V_AUX

6. The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance. On Semiconductor does not recommend exceeding

them or designing to Absolute Maximum Ratings.

Publication Order Number:

May 2017- Rev. 1.0

FAN105BM6X

ELECTRICAL CHARACTERISTICS

V_DD=12 V and T_A=-40~85C unless noted

Parameter

VDD Section

Test Conditions

Symbol

Min

Typ

Max

Unit

Turn-On Threshold Voltage

Turn-Off Threshold Voltage

V_DDOver-Voltage-Protection Level

V_DD-ON

V_DD-OFF

V_DD-OVP

16.5

6.1

17.5

6.5

18.5

6.9

26.5

28.0

29.5

V_DDOver-Voltage-Protection De-

bounce Time

t_D-VDD-OVP

120

200

µs

Startup Current⁽⁸⁾

I_DD-ST

I_DD-OP

1.7

525

µA

Operating Current

1.4

450

Deep Green-Mode Operating Current

Oscillator Section

I_DD-DPGN

375

Maximum Voltage-Mode Quasi-

Resonant Blanking Frequency

f_OSC-BNK-MAX

f_OSC-BNK-MIN

f_OSC-DPGN

4.5

320

5.0

420

5.5

480

kHz

Minimum Current-Mode Time-Out

Blankig Frequency

Deep Green Mode Operating

Frequency⁽⁸⁾

Minimum CCM Prevention

Frequency⁽⁷⁾

f_{OSC-CCM-PRVENT}

kHz

Over-Temperature Protection Section

Over-Temperature Protection

Threshold⁽⁷⁾

T_OTP-H

T_OTP-L

120

100

C

Over-Temperature Protection

Recovery Threshold⁽⁷⁾

Continues on next page…

Publication Order Number:

FAN105BM6X

May 2017- Rev. 1.0

ELECTRICAL CHARACTERISTICS

V_DD=12 V and T_A=-40~85C unless noted

Parameter

Test Conditions

Symbol

Min

Typ

Max

Unit

Voltage Sampling Section

Reference Voltage of Constant

Voltage Feedback

V_VR

2.475 2.500 2.525

VS Sampling Phase-Shift Resistance⁽⁷⁾

R_VS-S/H

C_VS-S/H

300

kΩ

VS Sampling Phase-Shift

Capacitance⁽⁷⁾

VS Sampling Blanking Time of High

Level

Io over 100mA

t_{VS_BNK-H}

t_{VS_BNK-CC}

V_VS-Offset

1.65

2.05

150

1.80

2.20

200

2.00

2.35

250

µs

VS Sampling Blanking Time at CC

Controlling

VS Discharging Time Judgment

Threshold Voltage⁽⁷⁾

Voltage Sense Section

Temperature-Independent Bias

Current

I_TC

9.0

10.0

11.0

μA

VS Pin Source Current Threshold to

Enable Brown-Out

I_VS-BROWN-OUT

t_D-BROWN-OUT

I_VS-BROWN-IN

N_BROWN-IN

V_VS-OVP

260

310

360

μA

Brown-Out De-bounce Time

VS Pin Source Current Threshold to

Enable Brown-In

405

475

545

Brown-In De-bounce Time

cycle

Output Over-Voltage-Protection of V_S

Sampling threshold

2.70

2.80

2.90

Output Over-Voltage-Protection

Debounce Cycle Counts

N_VS-OVP

V_VS-UVP

t_VS-UVP

Cycle

Output Low Level Under-Voltage-

Protection of V_SSampling threshold

1.50

1.60

1.70

Output Under-Voltage Protection

Debounce Time

No-Load Control Section

Deep Green Mode Entry Threshold

Voltage of COMV⁽⁷⁾

V_{COMV-CV-DPGN-}

0.4

0.5

0.6

ENTRY

Criteria to Enter Deep Green Mode

V_{VS_EAV_Hi}

V_VS-EAV-H

2.550 2.600 2.650

2.550

Deep Green Mode Band-Band Control

High Threshold Voltage

Deep Green Mode Band-Band Control

Low Threshold Voltage

V_VS-EAV-L

V_{VS_EAV_Lo}

V_VS-EAV-DYN

2.525

Criteria to Exit Deep Green Mode

2.425 2.450 2.475

2.375 2.400 2.425

Dynamic Event Trigger Threshold

Voltage in Deep Green Mode

Minimum On-time at 264VAC

Minimum On-time at 230VAC

Minimum On-time at 115VAC

Minimum On-time at 90VAC

C_GATE=1nF

t_{ON-MIN-264VAC}

t_{ON-MIN-230VAC}

t_{ON-MIN-115VAC}

t_ON-MIN-90VAC

450

500

550

600

1250

1500

1350

1650

1450

1800

Continues on next page…

Publication Order Number:

FAN105BM6X

May 2017- Rev. 1.0

ELECTRICAL CHARACTERISTICS

V_DD=12 V and T_A=-40~85C unless noted.

Parameter

Test Conditions

Symbol

Min

Typ

Max Unit

Current Feedback Section

Reference Voltage of Constant Current

Feedback

V_CCR

A_PK

1.19

1.2 1.21

3.9

VCS Peak Value Amplifying Gain⁽⁷⁾

V/V

Attenuator ratio of Constant Current

Feedback Loop⁽⁷⁾

A_V-CC

1/3.5

Current Sense Section

Current Limit Threshold Voltage

V_CS-LIM

t_PD

0.70 0.75 0.80

100

GATE Output Turn-Off Delay⁽⁷⁾

Leading-Edge Blanking Time⁽⁷⁾

t_LEB

150

200 250 ns

GATE Section

Maximum On-Time

t_ON-MAX

V_GATE-L

1.5

8.0

μs

Gate Output Voltage Low

Internal Gate PMOS Driver ON

Internal Gate PMOS Driver OFF

Gate Output Clamping Voltage

AUX Section

V_DD-PMOS-ON

V_DD-PMOS-OFF

V_GATE-CLAMP

7.0

9.0

7.0

7.5

9.5 10.0

VDD level higher than 9V

7.5

8.0

Dynamic Response Enhancement (DRE)

function trigger threshold current at AUX

I_DRE-DET

110

140

170 μA

R_CDCis 330kΩ

R_CDCis 560kΩ

R_CDCis 920kΩ

R_CDCis 1.3MΩ

V_VS-CDC4

V_VS-CDC3

V_VS-CDC2

V_VS-CDC1

0.298 0.320 0.343

0.223 0.240 0.257

0.149 0.160 0.171

0.074 0.080 0.086

CDC compensation voltage at internal

reference

Notes:

7. Guaranteed by Design.

8. T_Aguaranteed range at 25C

Publication Order Number:

May 2017- Rev. 1.0

FAN105BM6X

Typical Performance Characteristics

1.06

1.04

1.02

1.00

0.98

0.96

0.94

1.009

1.006

1.003

1.000

0.997

0.994

0.991

-40 -30 -15

25 50 75 85 100 125

-40 -30 -15 0 25 50 75 85 100 125

Tempeature (°C)

Figure 3.Turn-On Threshold Voltage (V_DD-ON) vs.

Temperature

Figure 4.Turn-Off Threshold Voltage (V_DD-OFF) vs.

Temperature

1.3

1.2

1.1

1.0

0.9

0.8

0.7

1.06

1.04

1.02

1.00

0.98

0.96

0.94

-40 -30 -15

25 50 75 85 100 125

Tempeature (°C)

-40 -30 -15 0 25 50 75 85 100 125

Tempeature (°C)

Figure 5.Operating Supply Current (I_DD-OP) vs.

Temperature

Figure 6.Deep Green Mode Operation Current (I_DD-

_DPGN) vs. Temperature

1.06

1.04

1.02

1.00

0.98

0.96

0.94

1.06

1.04

1.02

1.00

0.98

0.96

0.94

-40 -30 -15

25 50 75 85 100 125

-40 -30 -15

25 50 75 85 100 125

Tempeature (°C)

Figure 7.Maximum Operation Frequency of QR

Blanking Time (f_OSC-BNK-MAX) vs. Temperature

Figure 8. Deep Green Mode Operation Frequency

(f_OSC-DPGN) vs. Temperature

Publication Order Number:

FAN105BM6X

May 2017- Rev. 1.0

Typical Performance Characteristics

1.009

1.006

1.003

1.000

0.997

0.994

0.991

1.009

1.006

1.003

1.000

0.997

0.994

0.991

-40 -30 -15

25 50 75 85 100 125

-40 -30 -15 0 25 50 75 85 100 125

Tempeature (°C)

Figure 9.Reference Voltage of CV Feedback (V_VR

vs. Temperature

)

Figure 10.Vs Sampling Blanking Time (t_VS-BNK-H) vs.

Temperature

1.060

1.040

1.020

1.000

0.980

0.960

0.940

1.009

1.006

1.003

1.000

0.997

0.994

0.991

-40 -30 -15

25 50 75 85 100 125

-40 -30 -15

25 50 75 85 100 125

Tempeature (°C)

Figure 11.Output Over-Voltage Protection of Vs

sampling Threshold(V_VS-OVP) vs. Temperature

Figure 12.Output Under-Voltage of Vs sampling

Threshold(V_VS-UVP) vs. Temperature

1.009

1.006

1.003

1.000

0.997

0.994

0.991

1.06

1.04

1.02

1.00

0.98

0.96

0.94

-40 -30 -15

25 50 75 85 100 125

-40 -30 -15 0 25 50 75 85 100 125

Tempeature (°C)

Figure 13.Current Limit Threshold Voltage(V_CS-LIM

)

Figure 14.Minmum Gate Turn On time(t_{ON-MIN-264VAC}

)

vs. Temperature

Publication Order Number:

May 2017- Rev. 1.0

FAN105BM6X

Typical Performance Characteristics

1.06

1.04

1.02

1.00

0.98

0.96

0.94

1.009

1.006

1.003

1.000

0.997

0.994

0.991

-40 -30 -15

25 50 75 85 100 125

-40 -30 -15

25 50 75 85 100 125

Tempeature (°C)

Figure 15.Maximum Gate Turn On Time (t_ON-MAX) vs.

Temperature

Figure 16.Dynamic trigger current threshold (I_ZTC) vs.

Temperature

1.009

1.006

1.003

1.000

0.997

0.994

0.991

1.06

1.04

1.02

1.00

0.98

0.96

0.94

-40 -30 -15 0 25 50 75 85 100 125

Tempeature (°C)

Figure 17.Cable Compensation Level 4 Reference

Voltage(V_VS-CDC4) vs. Temperature

Figure 18.Brown In Threshold Current (I_VS-BROWN-IN) vs.

Temperature

1.06

1.04

1.02

1.00

0.98

0.96

0.94

1.06

1.04

1.02

1.00

0.98

0.96

0.94

-40 -30 -15

25 50 75 85 100 125

-40 -30 -15

25 50 75 85 100 125

Tempeature (°C)

Figure 19.Clamp Voltage (V_GATE-CLAMP) vs.

Temperature

Figure 20.Brown Out Threshold Current (I_VS-BROWN-OUT) vs.

Temperature

Publication Order Number:

FAN105BM6X

May 2017- Rev. 1.0

FAN105BM6X

Typical Performance Characteristics

1.060

1.040

1.020

1.000

0.980

0.960

0.940

1.06

1.04

1.02

1.00

0.98

0.96

0.94

-40 -30 -15

25 50 75 85 100 125

-40 -30 -15 0 25 50 75 85 100 125

Tempeature (°C)

Figure 21.Blanking time of VSUVP(t_VS-UVP) vs.

Temperature

Figure 22.VDD Over Voltage Protection Threshold (V_DD-OVP

)

vs. Temperature

Publication Order Number:

May 2017- Rev. 1.0

FAN105BM6X

When the MOSFET is turned off, the energy stored in the

inductor forces the secondary diode (D_sec) to turn on. While

the diode is conducting, the output voltage (V_o), together

with diode forward voltage drop (V_F), are applied across the

Functional Description

secondary-side inductor (L_mN_s²/ N_p) and the diode current

FAN105B is an offline PWM and Primary-Side Regulated

(PSR) fly-back controller that can simplify feedback circuit

and secondary side circuit compare to traditional fly-back

converter. In addition, FAN105B detects Quasi-Resonant

valley switching to minimize the switching loss and get

better EMI performance.

(I_D) decreases linearly from the peak value (I_pkN_p/N_s) to

zero. At the end of inductor current discharge time (t_DIS), all

the energy stored in the inductor has been delivered to the

output.

When the diode current reaches zero, the transformer

auxiliary winding voltage (V_Aux) begins to oscillate by the

resonance between the primary-side inductor (L_m) and the

effective capacitor loaded across MOSFET.

FAN105B modulates pulse width and switching frequency

based on feedback signal auxiliary winding signal (VS) and

current sense signal (CS). Extremely accurately Constant

Voltage(CV) with Cable Drop Compensation (CDC) and

Constant Current (CC) could meet strict requirement from

market. The CV and CC output characteristic is shown as

Figure 23. There are 4 levels (80mV - 320mV) choices in

CDC compensation weighting that is easily set via external

SMD resistor.

During the inductor current discharge time, the sum of

output voltage and diode forward-voltage drop is reflected to

the auxiliary winding side as (V_o+V_F)  N_Aux/N_s. Since the

diode forward-voltage drop decreases as current

decreases, the auxiliary winding voltage reflects the output

voltage best at the end of diode conduction time, where the

diode current diminishes to zero. By sampling the winding

voltage at the end of the diode conduction time, the output

voltage information can be obtained. The internal error

amplifier for output voltage regulation (EAV) compares the

sampled voltage with internal precise reference to generate

error voltage (COMV), which determines the duty cycle of

the MOSFET in CV Mode.

Before Cable Compensation

After Cable Compensation

V_O

Maximum Specification

Minimum Specification

The output current is obtained by averaging the triangular

output diode current area over a switching cycle as:

N_PT_DIS



I_O I_D_AVG



 I_PK



(1)

N_ST_S

I_O

Figure 23.CV with CDC and CC V/I Curve at the Cable

End

The internal FAN105B circuits identify the peak value of the

drain current with a peak detection circuit and calculate the

output current using the inductor discharge time (t_DIS) and

switching period (t_S). This output information (EAI) is

compared with internal precise reference to generate error

voltage (COMI), which determines the duty cycle of the

MOSFET in CC Mode. With TRUECURRENT® technique,

constant output current can be precisely controlled.

FAN105B implements DeeP GreeN mode (DPGN) with

lowest switching frequency, limites IC current consumption

(450µA) for excellent system standby power performance.

Furthermore, the system design allowes two kinds of startup

circuit with resistor or high voltage FET.

With a given current sensing resistor, the output current can

be programmed as:

Protections are : over/under voltage protection (VSOVP,

VSUVP), Brown In and Brown Out, cycle by cycle over

current protection(OCP), current sense resistor short

protection, secondary rectifier short protection.

ꢂ ꢅ_ꢆ

ꢈ

ꢉꢉꢊ

ꢁ

ꢀ

ꢄ

(2)

ꢃ ꢅ_ꢇꢋ_ꢉꢇ

Basic CV/CC Control Principle

Of the two error voltages, COMV and COMI, the smaller

one determines the duty cycle. During Constant Voltage

regulation, COMV determines the duty cycle while COMI is

saturated to HIGH. During Constant Current regulation,

COMI determines the duty cycle while COMV is saturated to

HIGH.

Figure 24 shows the circuit diagram of a PSR fly-back

converter, FAN105B estimates output current through

primary side peak current from CS, output voltage via

auxiliary winding signal that proportional to secondary side

voltage, the current and voltage sampling are shown in

Figure 25. Generally, Discontinuous Conduction Mode

(DCM) with valley switching operation is preferred for PSR

since it allows better output regulation. The operation

principles of DCM/BCM flyback converter are as follows:

During the MOSFET turn on time (t_ON), input voltage (V_DL) is

applied across the primary-side inductor (L_m). Then

MOSFET current (I_DS) increases linearly from zero to the

peak value (I_pk). Meanwhile, the energy is drawn from the

input and stored in the inductor.

Publication Order Number:

May 2017- Rev. 1.0

FAN105BM6X

D_sec

V_DL

C_DL

N_P

N_S

as EAV at timing like gray point showed. Base on EAV level

to regulate Pulse width to achieve estimation output voltage.

R_SN1

C_SN1

C_o

V_o

D_SN1

R_Gate

GATE

MOSFET

GATE

Estimator

EAI

V_CCR

V_VR

R_CG

COMI

R_CS

N_A

PWM

Control

Block

V_Aux

V_Auxiliary

COMV

R_VS1

Estimator

EAV

N_A

N_P



V_BLK

C_VS

R_VS2

200mV

Figure 24.Simplified PSR Flyback Converter Circuit

I_DS(MOSFET Drain-to-Source Current)

VS (With Schottky)

I_PK

I_D(Diode Current)

N_P

N_S

I_PK



I_o I_D_AVG

VS (With SR control)

t_VS-BNK-L

t_DIS

t_S

VS (With Schottky)

t_ON

N_A

R_{VS 2}

V_O



 EAV

N_SR_VS1 R_{VS 2}

N_A

R_{VS 2}

V_F



N_SR_VS1 R_{VS 2}

Figure 26.VS sampling with Diode or Synchronous

Rectifier

A leading edge blanking time(t_VS-BNK-H/L) start from primary

switch turned off. Most of TA design have VS oscillation

after primary switch turned off, that is caused by the

resonance of leakage inductance and parasistic

capacitance at transformer. In order to avoid VS sampling

procedure get impacted by that ringing, the oscillation

should be settle before settle down before t_VS-BNK-Lended as

Figure 26 showed. t_DISis secondary rectifier current

discharging time which recommend better design is longer

than t_VS-BNK-Hduring miimum on time controlling. t_DISis

predictable by following formula:

T_ON

T_DIS

T_S

Figure 25.Cycling Current and VS Sampling in DCM

Quasi-Resonant Valley Switch

FAN105B Build-In Quasi-Resonant valley detecting function

and inductor discharging time detecting function. During

MOSFET turn off period, FAN105B checked falling of VVS,

TDIS information will update as falling of VVS checked.

FAN105B keep monitor both VVS and IVS after TDIS

checked. FAN105B maximum period of MOSFET on time

and off time could be reach 45µs, it was depending on

whether valley checked. Quasi-Resonant valley switching

could minimize MOSFET switching loss during switch on,

meanwhile, to eliminate EMI and Common mode switching

component noise. Charger system would be getting better

efficiency than non-valley switching methodology.

ꢒ

ꢓ

ꢞ

ꢙꢓ

ꢌ_ꢍꢎꢇꢁ ^ꢏ

ꢄ _ꢠ^ꢠ

ꢢ

(3)

ꢐꢑ ꢔꢕꢖꢗꢘꢕ ꢔꢚꢚꢖꢐꢛꢑꢜꢝ

ꢡ

ꢒ

ꢞ

ꢏ ꢙꢏ

ꢟ

ꢐ

Where parameter : t_OFF-DELAYis switch turn off delay time

that level is chaging in differences system criteria, t_ON-MINis

minimum turn on time in design that should consider

propagation delay from IC Gate to switch Gate.

Output voltage can be describe by below equation:

ꢫ

ꢣꢤ_ꢥꢁ ꢤ_ꢤꢦꢄ ꢒꢧ ꢨ ^ꢦ^ꢤꢩꢧꢞ ꢄ _ꢫ

(4)

Output Voltage Sampling

ꢩ

ꢦ

ꢤꢩꢪ

ꢬ

VS voltage which is reflected auxiliary winding and

proportional to output voltage. Therefore, It is possible to

regulate output voltage by sensing VS voltage. Figure 26

shown VS sampling waveform with secondary rectifier that

using Schottky diode or Synchronous Rectifier (SR).

Deep Green Mode (DPGN) Operation in CV

mode

FAN105B integrated mWSaver® technology that minimize

current consumption and frequency at DPGN mode is fixed

to minimum switching frequency (f_OSC-DPGN) and variable

Pulse width based on VS sampling voltage (EAV).

In order to regulate output voltage in accurately range,

FAN105B build-in VS sampling methodology for signal like

Figure 26 showed, FAN105B samples and hold VS voltage

Publication Order Number:

May 2017- Rev. 1.0

FAN105BM6X

V_VSregulated boundary are between V_VS-EAV-Hand V_VS-EAV-

_L. After exit DPGN, internal regulation reference voltage was

changed to V_VR

Programmable Brown In/ Brown Out

FAN105B implement Brown out and Brown In through high

side resistor setting at VS PIN. In actual system operation,

VS PIN is drain a current (I_VS) that proportional to line

voltage during MOSFET turns on. I_VScould predict by below

equation:

FAN105B DPGN entry and exit criteria showed as below:

DPGN entry need to meet both criteria as below:

ꢮ

 Minimum frequency (f_OSC-MIN) operation continues over

than N_DPGN-Entryswitching cycles.

ꢏꢇ

ꢁ ꢈ_ꢍꢭꢄ ^ꢠ^ꢜꢄ _ꢊ

(5)

ꢠ

ꢢ

ꢯꢡꢰ

 EAV > V_VS-EAV-H(2.550V)_.

Operating Current

The operating current in FAN105B is as small as 1.4mA.

The small operating current results in higher efficiency and

reduces the V_DDhold-up capacitance requirement. During

DPGN mode, the FAN105B consumption current is reduced

to 450µA, assisting the power supply meet standby power

standard requirements.

DPGN exit criteria, meet one of below criteria:

 EAV < V_VS-EAV-L(2.525V) and maximum on time at

DPGN.

 EAV < V_VS-EAV-DYN(2.4V).

During the DPGN mode controlling, FAN105B decreases

the operating current down to 450µA. Therefore, the

standby power could meet international standard

requirement when work with flexible start up circuit,

designer have flexible start up circuit that HV FET or start

up resistor depending on cost and better standby power

consideration

Protections

The FAN105B self-protection includes V_DDOver-Voltage-

Protection (V_DDOVP), Internal Chip Over-Temperature-

Protection (OTP), VS Over-Voltage Protection (VSOVP), VS

Under-Voltage

Protection

(VSUVP),

Protection(CSP), Brownout and Brown In protection, and

all of protection are implemented as Auto Restart(AR)

mode.

Cable Drop Compensation (CDC)

FAN105B integrates cable drop compensation function and

the compensation weighting is calculated based on t_DIS,

current sense voltage (V_CS), and CDC setting resistor (R_CDC

needed to between VDD and AUX pin. During startup, as

VDD reached V_DD-ON, CDC programming block detects AUX

pin current and determine cable drop compensation

weighting based on current weighting of AUX pin. Once

finished CDC compensation weighting detecting, the

information will stored until shunt-down by protections or

VDD lower than V_DD-OFF. The CDC weighting automatic

detected input current during start up. which provides a

constant output voltage at the end of the cable over the

entire load range in CV Mode. The table shows the

compensation weighting with corresponding R_CDCsetting as

below:

When When an Auto-Restart Mode protection is triggered,

switching is terminated and the MOSFET remains off,

causing V_DDto drop till V_DD-OFFand shut-down the system

then all protections are reset. After then V_DDwill be charged

again by the input AC voltage and once touch V_DD-ONthen

switching resumes. This is the reason why it is called Auto-

Restart, resumes switching automatically.

)

V_DDOver-Voltage-Protection(V_DDOVP)

When V_DDis raised up to higher level by some reasons,

transformer V_DDwinding turns are too many, load regulation

is not good between transformer winding, VS information is

not available anyhow and so on, and touches V_DD-OVP, then

FAN105B stops switching and protects IC from higher V_DD

voltage. This is different then output voltage is over than pre

determined level.

CDC Weighting and R_CDCSetting

V_VSCompensation

VS Under-Voltage Protection (VSUVP)

R_CDC

Label

weighting

FAN105B bulid-in VSUVP function that prevent TA keep

deliver power to phone side when output voltage is under

the set voltage at VS pin. VSUVP has a 40ms de-bounce

time and once VDD touches V_DD-ON, during the later 40ms

VSUVP is disabled because VSUVP should not be triggered

during the start up. VSUVP level can be calculated as

below:

1.3MΩ

920kΩ

560kΩ

330kΩ

V_VS-CDC1

V_VS-CDC2

V_VS-CDC3

V_VS-CDC4

0.08V

0.16V

0.24V

0.32V

ꢫ_ꢩ

ꢣꢤ_{ꢥꢱꢲꢤꢳ}ꢁ ꢤ_{ꢤꢩꢱꢲꢤꢳ}ꢄ ꢒꢧ ꢨ ^ꢦꢞ ꢄ _ꢫ

(6)

ꢤꢩꢧ

ꢦ_ꢤꢩꢪ

TA designer can easily to set up CDC weighting via choose

R_CDCfollowing above table. In the table, resisance of R_CDC

is recommended for corresponding compensation level.

Cable drop compensation voltage at output is proportional

to V_VScompensation weighting that is internal referce

voltage for CDC compensation.

ꢬ

VS Over-Voltage Protection (VSOVP)

The VSOVP is designed to prevent TA output voltage is

over then the rating of used components, like capacitor.

VSOVP has 4 switching cycles of denounce time and that

prevent mis-triggered of VSOVP by switching noise. The

protection level is changed in proportional to the CDC

Publication Order Number:

May 2017- Rev. 1.0

FAN105BM6X

weighting.VSOVP trigger level can be illustrates as

following formula :

V_DD

V_DD-OVP

ꢶ_ꢥ

ꢫ_ꢩ

ꢞ ꢄ ꢒꢧ ꢨ _ꢦ^ꢦꢞ ꢄ _ꢫ

(7)

V_DD-ON

ꢤꢩꢧ

ꢣꢤ_{ꢥꢱꢥꢤꢳ}ꢁ ꢒꢤ_{ꢤꢩꢱꢥꢤꢳ}ꢨ ꢤ_{ꢤꢩꢱꢴꢵꢴ}

ꢄ

ꢶ_ꢥꢖꢴꢴ

ꢤꢩꢪ

ꢬ

V_DD-OFF

CS pin Protection(CSP)

V_GATE,S1

In order to prevent MOSFET current over than safe

operating area, FAN105B build-in cycle by cycle over

current protection. The protection could protect MOSFET

damaged by saturation current and CS pin sensing error. As

CS PIN signal meet below conditions FAN105B will turn off

Gate immediately. Current Sensing Protection (CSP) criteria

shows as below:

V_DD-V_AUX

V_AUX-CL

V_CS<0.2V after switching turn on 4.5us at low line

or 1.5us at high line.

Figure 28. Start Up Sequence With AUX Controlling

V_CS>1.5V

Dynamic Response Enhancement (DRE) With

AUX

Over-Temperature Protection(OTP)

In order to guarantee FAN105B works within recommended

temperature. FAN105B build-in chip Over-Temperature –

Protection (OTP). As chip junction temperature over

thareshold T_OTP-HIC immediately terminated Gate switching

PSR flyback converter regulates output voltage within

requirement specification through detects VS signal which

proportional to output voltage, However VS signal can only

detects when system switched. In order to get better

standby power performance, the switching frequency is

decreases to quite low frequency, it can not maintaining out

voltage as load suddenly increases from extremely light

load to heavy load during minimum frequency operation.

signal untill chip junction termperature recover to T_OTP-L

Start Up Function With AUX

FAN105B supports high voltage start up with HV FET that

can make better standby power and shorter start up time.

Figure 27 shows start up controlling function block. Figure

28 shows start up relative signal sequence with AUX

controlling.

Therefore, FAN105B build in

a Dynamic Response

Enhancement (DRE) function to detects output voltage

dropping immediately when FAN105B pair with FAN6292B.

Figure 29 shows DRE function block. Figure 30 shows

DRE function relative signal working sequence. When

output voltage undershoot is acknowledged via FAN6292B

VIN pin, BLD/AUX pin pull-down current via S2 switch to

inform undershoot to FAN105B via a photo-coupler. Once

FAN105B sensed AUX current higher than I_DRE-DET, the

switching frequency is increases immediately.

At system power on moment, initial VDD voltage is zero,

internal PMOS switch is turn on and external HV FET also

turn on, C_VDDis charged through HV FET till VDD reach

V_DD-ON. While Internal PMOS switch S1 turn off and VGS of

HV FET will close to internal clamping voltage (V_AUX-CL

)

which less than HV FET VGS turn on threshold. Meanwhile

VDD energy supplement is turn to auxiliary winding. The

voltage gap between VDD and VAUX is keep at 5V till

VBUS

N_P

N_S

C_o1

LGATE

C_o2

controller shut-down by protection or VDD touching V_DD-OFF

SR Gate

VDD

R_AUX

V_DL

Opto-

R_Start

coupler

R_CDC

AUX

FAN105B

R_OPTO(3.3kΩ)

V_AUX-CL

No Load

Control

Leave

Bang-Bang

Control

TDIS

TON

V_ODrop

Detection

AUX

BLD / AUX

VIN

VDD

I_AUX

FAN6292B

C_VDD

V_DD-ON/ V_DD-OFF

Pulse

V_IN-AUX

Figure 29. Internal function for Start Up of AUX PIN

Figure 27. Internal function for Start Up of AUX PIN

Publication Order Number:

FAN105BM6X

May 2017- Rev. 1.0

FAN105BM6X

V_GATE

(FAN105B)

Accurately

Constant

Current

(CC)

Compensation

I_O

Heavy Load

FAN105B provides accurate constant current with

universal line voltage range, In order to achieve this

accurately output current regulated, FAN105B build in

circuits that compensate a DC level at CS signal

based on difference line voltage. It could avoid output

current gap of difference line voltage during constand

current controlling. For noise immunity, the

recommendation of CS pin series resistor is 10Ω.

V_BUS

V_IN-AUX

t_AUX-ON

t_OPTO-DELAY

I_AUX

I_DRE-DET

Figure 30.DRE function Detecting Sequency

Publication Order Number:

May 2017- Rev. 1.0

FAN105BM6X

REVISIONS

LTR

DESCRIPTION

DATE

11/4/2006

5 JULY 07

E.C.N.

BY/APP'D

H.ALLEN

RELEASE TO DOCUMENT CONTROL

DWG UPDATED TO CONFORM TO MO178

L.HUEBENER

0.15 C A-B

SYMM

2.9

1.9

(0.95)

(1.00MIN)

1.4

1.6

2.8

(2.60)

(0.70MIN)

0.15 C D

0.15 C

PIN 1 INDEX AREA

2X 3 TIPS

0.95

(1.90)

2X 0.3-0.5

0.20

C A-B D

LAND PATTERN RECOMMENDATION

SEE DETAIL A

1.45 MAX

1.30

0.90

0.08

0.22

0.10

0.15

0.05

R0.10MIN

NOTES:

GAGE PLANE

0.25

A. THIS PACKAGE CONFORMS TO JEDEC MO-178,

VARIATION AB.

B. ALL DIMENSIONS ARE IN MILLIMETERS.

C. DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS

OR GATE BURRS.

R0.10MIN

8°

0°

D. DOES NOT INCLUDE INTERLEAD FLASH OR

PROTRUSIONS.

E. DIMENSIONS AND TOLERANCING AS PER ASME

Y14.5M-1994

0.60

0.30

SEATING PLANE

0.60 REF

F. DRAWING FILE NAME: MA06EREV2

DETAIL A

SCALE: 2:1

APPROVALS

L.HUEBENER

DATE

5 JULY 07

17 JULY 07

H.ALLEN

6LD,SOT23,JEDEC

MO-178 VARIATION AB,

1.6MM WIDE

MKT-MA06E

1:1 NA

FORMERLY:

SHEET :

N/A

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