FAN2103MPX [ONSEMI]
-3A，24V 输入，集成式同步降压稳压器;
| 型号： | FAN2103MPX |
| 厂家： | 
ONSEMI |
| 描述： | -3A，24V 输入，集成式同步降压稳压器 信息通信管理 开关 稳压器 |
| 文件： | 总15页 (文件大小：1389K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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August 2014
FAN2103 — TinyBuck™
3 A, 24 V Input, Integrated Synchronous Buck
Regulator
Features
Description
The FAN2103 TinyBuck™ is an easy-to-use, cost- and
space-efficient, 3 A synchronous buck solution. It
enables designers to solve high current requirements in
a small area with minimal external components.
.
.
.
3 A Output Current
Over 95% Efficiency
Fully Synchronous Operation with Integrated
Schottky Diode on Low-side MOSFET Boosts
Efficiency
External compensation, programmable switching
frequency, and current limit features allow for design
optimization and flexibility.
.
Programmable Frequency Operation (200 KHz to
600 KHz)
The summing current mode modulator uses lossless
current sensing for current feedback and over-current,
and includes voltage feedforward.
.
.
.
.
.
.
.
.
Power-good Signal
Accepts Ceramic Capacitors on Output
External Compensation for Flexible Design
Wide Input Range: 3 V to 24 V
Output Voltage Range: 0.8 V to 90%VIN
Input Under-Voltage Lockout
Fairchild’s advanced BiCMOS power process, combined
with low RDS(ON) internal MOSFETs and a thermally
efficient MLP package provide the ability to dissipate
high power in a small package.
Output over-voltage, under-voltage, and thermal
shutdown protections plus power-good, help protect the
devices from damage during fault conditions.
Programmable Over-Current Limit
Under-Voltage, Over-Voltage, and
Thermal Protections
Related Application Notes
.
5x6 mm, 25-pin, 3-Pad MLP
.
.
.
TinyCalc™ Design Tool
AN-6033 — TinyCalc™ Design Tool Guide
Applications
AN-5067 – PCB Land Pattern Design and Surface
Mount Guidelines for MLP Packages
.
.
.
.
.
Graphics Cards
Battery-powered Equipment
Set-top Boxes
Point-of-load Regulation
Servers
Ordering Information
Operating
Temperature Range
Part Number
Package
Packing Method
FAN2103MPX
-10°C to 85°C
-40°C to 85°C
25-Pin Molded Leadless Package (MLP) 5 x 6 mm
Tape and Reel
FAN2103EMPX
© 2007 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN2103 • Rev. 1.0.9
Typical Application Diagram
Figure 1. Typical Application
Block Diagram
BOOT
VCC
Boot
Diode
Current Limit
Comparator
IILIM
VIN
ILIM
Def Level
COMP
Error
CBOOT
R
S
Q
Amplifier
PWM
Comparator
FB
VOUT
SW
Gate
Drive
Circuit
L
SS
VREF
COUT
Summing
Amplifier
RAMP
GEN
Current
Sense
EN
OSC
GND
RAMP
Figure 2. Block Diagram
© 2007 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN2103 • Rev. 1.0.9
2
Pin Configuration
RAMP
NC
SW
SW
P2
VIN
P1
SW
PGND
PGND
PGND
SW
SW
P3
GND
Figure 3. MLP 5 x 6 mm Pin Configuration (Bottom View)
Pin Definitions
Pin
Name
SW
Description
P1, 6-12
P2, 2-5
Switching Node.
VIN
Power Input Voltage. Connect to the main input power source.
Power Ground. Power return and Q2 source.
P3, 21-23
PGND
High-side Drive BOOT Voltage. Connect through capacitor (CBOOT) to SW. The IC includes
an internal synchronous bootstrap diode to recharge the capacitor on this pin to VCC when
SW is LOW.
1
BOOT
PGOOD
EN
Power-Good Flag. An open-drain output that pulls LOW when FB is outside a ±10% range
of the reference when EN is HIGH. PGOOD does not assert HIGH until the fault latch is
enabled.
13
14
ENABLE. Enables operation when pulled to logic HIGH or left open. Toggling EN resets the
regulator after a latched fault condition. This input has an internal pull-up when the IC is
functioning normally. When a latched fault occurs, EN is discharged by a current sink.
15
16
VCC
Input Bias Supply for IC. The IC’s logic and analog circuitry are powered from this pin.
Analog Ground. The signal ground for the IC. All internal control voltages are referred to
this pin. Tie this pin to the ground island/plane through the lowest impedance connection.
AGND
Current Limit. A resistor (RILIM) from this pin to AGND can be used to program the current-
limit trip threshold lower than the default setting.
17
ILIM
Oscillator Frequency. A resistor (RT) from this pin to AGND sets the PWM switching
frequency.
18
19
20
24
25
R(T)
FB
Output Voltage Feedback. Connect through a resistor divider to the output voltage.
Compensation. Error amplifier output. Connect the external compensation network between
this pin and FB.
COMP
NC
No Connect. This pin is not used.
Ramp Amplitude. A resistor (RRAMP) connected from this pin to VIN sets the ramp amplitude
and provides voltage feedforward functionality.
RAMP
© 2007 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN2103 • Rev. 1.0.9
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Parameter
VIN to PGND
VCC to AGND
BOOT to PGND
BOOT to SW
SW to PGND
All other pins
Conditions
Min.
Max.
28
Unit
V
AGND = PGND
6
V
35
V
-0.3
-5
6.0
V
Transient (t < 20 ns, f < 600 KHz)
30
V
-0.3
2.0
2.5
VCC+0.3
V
Human Body Model, JEDEC JESD22-A114
Charged Device Model, JEDEC JESD22-C101
ESD
kV
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
VCC
Parameter
Conditions
Min.
4.5
3
Typ.
Max.
5.5
Unit
V
Bias Voltage
VCC to AGND
5.0
VIN
Supply Voltage
VIN to PGND
FAN2103M
24
V
-10
-40
+85
+85
+125
°C
°C
°C
TA
TJ
Ambient Temperature
Junction Temperature
FAN2103EM
Thermal Information
Symbol
Parameter
Min.
Typ.
Max.
+150
+300
+215
+220
Unit
°C
TSTG
TL
Storage Temperature
-65
Lead Soldering Temperature, 10 Seconds
Vapor Phase, 60 Seconds
°C
TVP
TI
°C
Infrared, 15 Seconds
°C
P1 (Q2)
P2 (Q1)
P3
4
7
°C/W
°C/W
°C/W
°C/W
W
Thermal Resistance: Junction-to-Case
JC
4
35(1)
Thermal Resistance: Junction-to-Mounting Surface
Power Dissipation, TA = 25°C
J-PCB
PD
2.8(1)
Note:
1. Typical thermal resistance when mounted on a four-layer, two-ounce PCB, as shown in Figure 26. Actual results
are dependent on mounting method and surface related to the design.
© 2007 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN2103 • Rev. 1.0.9
4
Electrical Specifications
Recommended operating conditions are the result of using the circuit shown in Figure 1 unless otherwise noted.
Parameter
Conditions
Min.
Typ.
Max.
Unit
Power Supplies
SW = Open, FB = 0.7 V, VCC = 5 V,
fSW = 600 KHz
8
12
mA
VCC Current
Shutdown: EN = 0, VCC = 5 V
Rising VCC
7
10
µA
V
4.1
4.3
300
4.5
VCC UVLO Threshold
Oscillator
Hysteresis
mV
255
540
300
600
50
345
660
65
KHz
KHz
ns
RT = 50 K
RT = 24 K
Frequency
Minimum On-Time(2)
16 VIN, 1.8 VOUT, RT = 30 K,
RRAMP = 200 K
Ramp Amplitude, pk–pk
0.53
100
V
Minimum Off-Time(2)
150
ns
Reference
FAN2103M, 25°C
794
795
800
800
50
806
805
mV
mV
Reference Voltage (VFB)
Temperature Coefficient
FAN2103EM, 25°C
FAN2103M, -10 to +85°C
FAN2103EM, -40 to +85°C
PPM
PPM
70
Error Amplifier
DC Gain(2)
Gain Bandwidth Product(2)
80
12
85
15
dB
MHz
V
VCC = 5 V
Output Voltage (VCOMP
)
0.4
1.5
0.8
-850
3.2
Output Current, Sourcing
Output Current, Sinking
FB Bias Current
VCC = 5 V, VCOMP = 2.2 V
VCC = 5 V, VCOMP = 1.2 V
VFB = 0.8 V, 25°C
2.2
1.2
mA
mA
nA
-650
-450
Protection and Shutdown
Current Limit
RILIM Open
3.8
9
5.0
10
7.0
11
A
µA
ILIM Current
25°C, VCC = 5 V
Over-Temperature Shutdown
Over-Temperature Hysteresis
Over-Voltage Threshold
Under-Voltage Shutdown
Fault Discharge Threshold
Fault Discharge Hysteresis
Soft-Start
+160
+30
115
73
°C
Internal IC Temperature
°C
2 Consecutive Clock Cycles
16 Consecutive Clock Cycles
Measured at FB Pin
110
68
120
78
%VOUT
%VOUT
mV
250
250
Measured at FB Pin (VFB ~500 mV)
mV
VOUT to Regulation (T0.8)
Fault Enable/SSOK (T1.0)
Note:
5.3
6.7
ms
ms
Frequency = 600 KHz
2. Specifications guaranteed by design and characterization; not production tested.
© 2007 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN2103 • Rev. 1.0.9
5
Electrical Specifications (Continued)
Recommended operating conditions are the result of using the circuit shown in Figure 1 unless otherwise noted.
Parameter
Conditions
Min.
Typ.
Max.
Unit
Control Functions
EN Threshold, Rising
EN Hysteresis
1.35
250
800
1
2.00
V
mV
K
EN Pull-up Resistance
EN Discharge Current
FB OK Drive Resistance
Auto-restart Mode
µA
800
-8
FB < VREF
FB > VREF
IOUT < 2 mA
-14
+7
-11
%VREF
%VREF
V
PGOOD Threshold
(Compared to VREF
)
+10
+13
0.4
PGOOD Output Low
© 2007 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN2103 • Rev. 1.0.9
6
Typical Characteristics
1.010
1.005
1.000
0.995
0.990
1.20
1.10
1.00
0.90
0.80
-50
0
50
100
150
-50
0
50
100
150
Temperature (oC)
Temperature (oC)
Figure 4. Reference Voltage (VFB) vs. Temperature,
Normalized
Figure 5. Reference Bias Current (IFB) vs.
Temperature, Normalized
1500
1200
900
600
300
0
1.02
1.01
1.00
0.99
0.98
600KHz
300KHz
-50
0
50
100
150
0
20
40
60
80
100
120
140
Temperature (oC)
RT (K)
Figure 6. Frequency vs. RT
Figure 7. Frequency vs. Temperature, Normalized
1.04
1.02
1.00
0.98
0.96
1.60
1.40
1.20
1.00
0.80
0.60
Q1 ~0.32 %/oC
Q2 ~0.35 %/oC
-50
0
50
100
150
-50
0
50
100
150
Temperature (oC)
Temperature (oC)
Figure 9. ILIM Current (IILIM) vs. Temperature,
Normalized
Figure 8. RDS vs. Temperature, Normalized
(VCC = VGS = 5 V)
© 2007 Fairchild Semiconductor Corporation
FAN2103 • Rev. 1.0.9
www.fairchildsemi.com
7
Application Circuit
VIN
VCC
P2
25
+5V
8-20 VIN
15
1.0µ
X5R
10K
200K
PGOOD
3.3n
2 x 4.7
13
24
20
µ
VOUT
X7R
RAMP
NC
2.49K
COMP
62
2.49K
4.7n
56p
BOOT
SW
FB
ILIM
EN
1
19
17
14
18
* TDK
RLF7030T-3R3M4R1
4.7n
0.1µ
VOUT
P1
200K
4.7n
µ
3.3
1.5W
*
R(T)
30.1K
2.00K
4 x 22µ
X5R
AGND
PGND
P3
390p
16
Figure 10. Application Circuit: 1.8 VOUT, 500 KHz
Typical Performance Characteristics
Typical operating characteristics using the circuit shown in Figure 10. VIN=16 V, VCC=5 V, unless otherwise specified.
Efficiency
Power Loss
100
1.0
95
0.9
Loss12V (W)
90
0.8
Loss8V (W)
85
80
75
70
65
60
55
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
Loss18V (W)
Effi12V (%)
Effi8V (%)
Effi18V (%)
0.00
0.50
1.00
1.50
2.00
2.50
3.00
0.00
0.50
1.00
1.50
2.00
2.50
3.00
Load Current (A)
Load Current (A)
Figure 11. 1.8 VOUT Efficiency Over VIN vs. Load
Figure 12. 1.8 VOUT Dissipation Over VIN vs. Load
Regulation Characteristic
Efficiency
100
1.828
95
90
85
80
75
1.826
1.824
1.822
Vo8V (V)
1.820
Vo12V (V)
Vo18V (V)
V
V
=8V, 300KHz
=12V, 500Khz
IN
IN
70
65
1.818
0.00
0.50
1.00
1.50
2.00
2.50
3.00
0.00
0.50
1.00
1.50
2.00
2.50
3.00
Load Current (A)
Load Current (A)
Figure 13. 1.8 VOUT Regulation vs. Load
Figure 14. 3.3 VOUT Efficiency vs. Load
(Circuit Values Changed)
© 2007 Fairchild Semiconductor Corporation
FAN2103 • Rev. 1.0.9
www.fairchildsemi.com
8
Typical Performance Characteristics (Continued)
Typical operating characteristics using the circuit shown in Figure 10. VIN=12 V, VCC=5 V, unless otherwise specified.
Figure 15. SW and VOUT Ripple, 3 A Load
Figure 16. Startup with 1 V Pre-Bias on VOUT
Figure 17. Transient Response, 1.5-3 A Load
Figure 18. Re-start on Fault
(Circuit Values Changed)
Figure 19. Startup, 3 A Load
Figure 20.
Shutdown, 3 A Load
© 2007 Fairchild Semiconductor Corporation
FAN2103 • Rev. 1.0.9
www.fairchildsemi.com
9
Circuit Description
Initialization
Once VCC exceeds the UVLO threshold and EN is HIGH,
the IC checks for an open or shorted FB pin before
releasing the internal soft-start ramp (SS).
Bias Supply
The FAN2103 requires a 5 V supply rail to bias the IC
and provide gate-drive energy and controller power.
Connect a 1.0 µf X5R or X7R decoupling capacitor
between VCC and PGND. Whenever the EN pin is
pulled up to VCC, the 5 V supply connected to VCC
should be turned ON after VIN comes up. If the power
supply is turned ON using EN pin with an external
control after VCC and VIN come up, the VCC and VIN
power sequencing is not relevant.
If R1 is open (as shown in Figure 1), the error amplifier
output (COMP) is forced LOW and no pulses are
generated. After the SS ramp times out (T1.0), an under-
voltage latched fault occurs.
If the parallel combination of R1 and RBIAS is 1K, the
internal SS ramp is not released and the regulator does
not start.
Since VCC is used to drive the internal MOSFET gates,
supply current is frequency and voltage dependent.
Approximate VCC current (ICC) can be calculated using:
Soft-Start
Once internal SS ramp has charged to 0.8 V (T0.8), the
output voltage is in regulation. Until SS ramp reaches
1.0 V (T1.0), the “Fault Latch” is inhibited.
V
5
227
CC
I
4.58 [(
0.013)(f 128)]
(1)
CC
(mA )
where frequency (f) is expressed in KHz.
To avoid skipping the soft-start cycle, it is necessary to
apply VIN before VCC reaches its UVLO threshold.
Setting the Output Voltage
Soft-start time is a function of oscillator frequency.
The output voltage of the regulator can be set from
0.8 V to ~80% of VIN by an external resistor divider (R1
and RBIAS in Figure 1).
1.35V
EN
The internal reference is 0.8 V with 650 nA, sourced
from the FB pin to ensure that if the pin is open, the
regulator does not start.
2400 CLKs
0.8V
FB
The external resistor divider is calculated using:
Fault
Latch
Enable
1.0V
0.8V
VOUT 0.8V
0.8V
650nA
(2)
RBIAS
R1
SS
Connect RBIAS between FB and AGND.
3200 CLKs
4000 CLKs
Setting the Frequency
Oscillator frequency is determined by an external resistor,
RT, connected between the R(T) pin and AGND:
T0.8
T1.0
Figure 21. Soft-Start Timing Diagram
6
10
f
(3)
(KHz)
(65 R ) 135
T
The regulator does not allow the low-side MOSFET to
operate in full synchronous rectification mode until
internal SS ramp reaches 95% of VREF (~0.76 V). This
helps the regulator start against pre-biased outputs (as
shown in Figure 16) and ensures that inductor current
does not "ratchet" up during the soft-start cycle.
where RT is expressed in K.
6
(10 /f) 135
(4)
R
T
(K)
65
where frequency (f) is expressed in KHz.
VCC UVLO or toggling the EN pin discharges the SS and
resets the IC.
The regulator does not start if RT is left open.
© 2007 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN2103 • Rev. 1.0.9
10
Calculating the Inductor Value
Typically the inductor is set for a ripple current (IL) of
10% to 35% of the maximum DC load. Regulators
requiring fast transient response use a value on the high
side of this range, while regulators that require very low
output ripple and/or use high-ESR capacitors restrict
allowable ripple current:
VRILIM = 10µA*RILIM
To calculate RILIM
RILIM = VRILIM/ 10µA
(8)
(9)
:
The voltage VRILIM is made up of two components, VBOT
(which relates to the current through the low-side
MOSFET) and VRMPEAK (which relates to the peak
current through the inductor). Combining those two
voltage terms results in:
V
(1 - D)
OUT
IL
(5)
L f
where f is the oscillator frequency and:
(1- D)
RILIM = (VBOT + VRMPEAK)/ 10µA
(10)
V
OUT
L
(6)
IL f
RILIM = {0.96 + (ILOAD * RDSON *KT*8)} +
{D*(VIN – 1.8)/(fSW*0.03*10^-3*RRAMP)}/10µA
(11)
Setting the Ramp Resistor Value
where:
The internal ramp voltage excursion (ΔVRAMP) during tON
should be set to 0.6 V. RRAMP is approximately:
VBOT = 0.96 + (ILOAD * RDSON *KT*8);
VRMPEAK = D*(VIN – 1.8)/(fSW*0.03*10^-3*RRAMP);
ILOAD = the desired maximum load current;
(V 1.8) V
IN
OUT
R
2
RAMP(K)
(7)
6
18x10 V f
IN
RDSON = the nominal RDSON of the low-side MOSFET;
where frequency (f) is expressed in KHz.
KT = the normalized temperature coefficient for the
low-side MOSFET (on datasheet graph);
Setting the Current Limit
D = VOUT/VIN duty cycle;
The current limit system involves two comparators. The
MAX ILIMIT comparator is used with a VILIM fixed-voltage
reference and represents the maximum current limit
allowable. This reference voltage is temperature
compensated to reflect the RDSON variation of the low-
side MOSFET. The ADJUST ILIMIT comparator is used
where the current limit needs to be set lower than the
VILIM fixed reference. The 10 µA current source does not
track the RDSON changes over temperature, so change is
added into the equations for calculating the ADJUST
ILIMIT comparator reference voltage, as is shown below.
Figure 22 shows a simplified schematic of the over-
current system.
fSW = Clock frequency in kHz; and
RRAMP = chosen ramp resistor value in k.
After 16 consecutive, pulse-by-pulse, current-limit
cycles, the fault latch is set and the regulator shuts
down. Cycling VCC or EN restores operation after a
normal soft-start cycle (refer to the Auto-Restart
section).
The over-current protection fault latch is active during
the soft-start cycle. Use 1% resistor for RILIM
.
PWM
Loop Compensation
RAMP
COMP
+
_
VERR
The loop is compensated using a feedback network
around the error amplifier. Figure 23 shows a complete
Type-3 compensation network. Type-2 compensation
eliminates R3 and C3.
PWM
MAX
ILIMIT
+
_
VCC
VILIM
10µA
ADJUST
ILIMIT
ILIMTRIP
+
_
ILIM
RILIM
Figure 22. Current-Limit System Schematic
Since the ILIM voltage is set by a 10 µA current source
into the RILIM resistor, the basic equation for setting the
reference voltage is:
Figure 23. Compensation Network
© 2007 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN2103 • Rev. 1.0.9
11
Because the FAN2103 employs summing current-mode
architecture, Type-2 compensation can be used for
many applications. For applications that require wide
loop bandwidth and/or use very low-ESR output
capacitors, Type-3 compensation may be required.
Table 1. Fault / Restart Provisioning
EN pin
Controller / Restart State
OFF (disabled)
Pull to GND
No restart – latched OFF (after VCC
comes up)
VCC
RRAMP provides feedforward compensation for changes
in VIN. With a fixed RRAMP value, the modulator gain
increases as VIN is reduced, which could make it difficult
to compensate the loop. For designs with low input
voltages (3 V to 6.5 V), it is recommended that a
separate RRAMP and the compensation component
values are used as compared to designs with VIN
between 6.5 V and 24 V.
Open
Immediate restart after fault
New soft-start cycle after:
Cap to GND
tDELAY (ms) = 3.9 • C(nf)
With EN left open, restart is immediate.
If auto-restart is not desired, tie the EN pin to the VCC pin
or pull it high after VCC comes up with a logic gate to keep
the 1 µA current sink from discharging EN to 1.1 V.
Protection
The converter output is monitored and protected against
extreme overload, short-circuit, over-voltage, and under-
voltage conditions.
An internal “Fault Latch” is set for any fault intended to
shut down the IC. When the fault latch is set, the IC
discharges VOUT by enhancing the low-side MOSFET
until FB<0.25 V. The MOSFET is not turned on again
unless FB>0.5 V. This behavior discharges the output
without causing undershoot (negative output voltage).
FAULT
0.25/0.5V
PWM GATE
DRIVE
FB
PWM LATCH
Figure 25. Fault Latch with Delayed Auto-Restart
Over-Temperature Protection
Figure 24. Latched Fault Response
FAN2103 incorporates an over-temperature protection
circuit that sets the fault latch when a die temperature of
about 160°C is reached. The IC is allowed to restart
when the die temperature falls below 130°C.
Under-Voltage Shutdown
If FB remains below the under-voltage threshold for 16
consecutive clock cycles, the fault latch is set and the
converter shuts down. This fault is prevented from
setting the fault latch during soft-start.
Power Good (PGOOD) Signal
PGOOD is an open-drain output that asserts LOW when
VOUT is out of regulation, as measured at the FB pin
(thresholds are specified in the Electrical Specifications
section). PGOOD does not assert HIGH until the fault
latch is enabled (T1.0).
Over-Voltage Protection / Shutdown
If FB exceeds 115% • VREF for two consecutive clock
cycles, the fault latch is set and shutdown occurs.
A shorted high-side MOSFET condition is detected
when SW voltage exceeds ~0.7 V while the low-side
MOSFET is fully enhanced. The fault latch is set
immediately upon detection.
PCB Layout
The two fault protection circuits above are active all the
time, including during soft-start.
Auto-Restart
After a fault, EN is discharged with 1 µA to a 1.1 V
threshold before the 800 K pull-up is restored. A new
soft-start cycle begins when EN charges above 1.35 V.
Depending on the external circuit, the FAN2103 can be
provisioned to remain latched-off or automatically restart
after a fault.
Figure 26. Recommended PCB Layout
© 2007 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN2103 • Rev. 1.0.9
12
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